DE19705003A1 - Two-layer or multilayer circuit arrangement for SMD technique - Google Patents

Abstract

The multi-layer circuit construction has a copper foil 1 and acts as a stabiliser some 35 micron thick. A dielectric permanent resist layer 3 is formed on the copper layer and has openings in which the resistant metal layer has been etched away. A catalyser structure is overlaid 5 and on this is a second dielectric structure 31. The structure is completed by a further catalyser layer 51 and an etched conductive layer 42.

Description

The invention relates to a bi- or multilayer arrangement the features according to claims 1 or 6.

Bi- or multilayer arrangements with internal connections due to increased use of surface-mountable construction elements and a higher integration rate on assemblies level is increasingly used. There are different ones Processes with different manufacturing difficulties Degree of realization for the realization of multilayer arrangements.

In addition, it is known that the limited external surfaces the circuit pads used a relocation of the electrical Require connections to the interior of multilayers. With, it also reduces the structural width of the interconnects  Diameters of the inner connections result in quality problems that only result from high manufacturing costs can be solved.

The state of the art in the formation of vertical internal Contacts, the connections between one or more levels produce, for example, is characterized in that the same through a through hole or a blind hole take place, which is then metallized. With the me tallization can then simultaneously contact the resulting sleeve with the respective signal or control level will be realized. The formation of the so-called blind hole drilling is particularly critical when it is on a Soldering eye of the first or second inner layer ends. Here is a special precision with regard to the depth tolerances required what is considerable technical in series production Causes problems.

From DE-PS 38 43 528 it is known to have an inner layer for Blind hole multilayer by making a thin, highly ductile copper foil against one with raised surfaces in the desired contact pattern provided surface and pressed resulting embossed prints with a thermosetting resin fill out. The laminate that then forms raised areas can be used as the first inner layer in one Blind hole multilayer can be used. Because in such a trained Multilayer the soldering eye to be drilled just below the surface lies, the risk of contacting reduces an underlying inner layer. Regardless of the exp tert depth tolerance is more technological than subsequent Step next to drilling a connection or contact metal lization required. Here is the one described above Solution, especially for very small ones, in the course of miniatures desirable internal contacts and connections, ver Technically very complex and technologically difficult manageable. In addition, a perforated wall metallization works as a line discontinuity negative for the transferring Signals or signal waveform.  

One is from the German utility model G 91 02 817.5 internal connection to build multilayer circuits known, signal networks or on a carrier material conductor levels arranged according to the circuit structure are.

There are at the ends of the lateral, corresponding to the Circuit structure realized on a carrier material Signal network, at the point where internal connections were stale are technically necessary, protruding hills galvanic growth or by means of differential etching from a stronger metal foil or layer formed.

At least two hills with opposite hills Signal levels are then positioned to each other, with between Pre-crosslinked epoxy adhesive films are inserted into the signal levels are brought. These are then elaborate Pressure-temperature-time process pressed. Here, the Puncture epoxy adhesive film, which is simultaneously Forms contact between the opposite hills. This creates a multilayer, the inner connections has without drilling with subsequent formation a galvanic contact is required. Problems however, are that the opposite hills are exact must be positioned, and also a contact to external interconnects or signal levels is not possible.

DE 195 15 159 A1 describes a connection arrangement and a Method of making a connection arrangement for Mul tilayer circuits known. To contact an inside lying bilayer or multilayer core to the outer guide layer becomes at least one melted insulation layer and at least one conductive layer by means of vacuum lamination upset. Special contact bumps penetrate the insulation layer during the melting process and a Connection to the conductor located above the insulating layer layer. With the arrangement shown there, inside  Connections starting from an internal through contact bi- or multilayer, to outer guide layers or Signal levels can be realized. The insertion of blind holes drilling is no longer necessary. The processes of vacuum laminating a photoresist, the photo printing and the advent wrap the contact surfaces for the hill plating as well after the galvanic deposition of copper to form hill structures However, the required stripping of the photoresist is technolo very complex and leads to reduced production vity.

From US-PS 5 246 817 is a method for manufacturing of a multilayer known at which signal levels are isolated of dielectrics and with internal connections between the Layers are formed. To avoid bad Contacts of internal connections as well as adverse air inclusions that arise in known lamination processes, is proposed according to U.S. Patent No. 5,246,817, a dielek trical photoresist coating on a first control level to train. Then openings for connections are closed above the provided guide levels and a catalytic converter applied gate layer, including the openings Cover the photoresist layer. After electroplating the application of a so-called sacrificial layer, the openings or contact window for internal connections or guidance has levels.

With galvanic deposition in the aforementioned openings internal connections or interconnects or Management levels trained.

Then the sacrificial layer and the Catalyst layer so that the photoresist is exposed and a dielectric filler in the remaining spaces can be introduced.

In the solution described above, on the one hand Application and removal of sacrificial layers necessary in order to  To be able to carry out electroplating, which is an additional Chen effort entails and on the other hand, the through removing the irregularity resulting in lateral direction by applying a dielectric Film material are balanced, because only then a re fetching the deposition of the corresponding layer sequence Multilayer training is possible.

It is therefore an object of the invention, a bi- or multilayer to specify an arrangement which allows it to be done in a simple manner both internal connections and external contacts with to realize low technological effort.

The object of the invention is achieved with a counter stood according to the features of claim 1 or 6, wherein the subclaims at least useful configurations and Training includes.

The basic idea of the invention is from an ent removable, metallized subcarrier on which a photo-structured dielectric permanent reading layer is applied, whereby Verbin through typical photoprocesses openings, but also interconnects that become metal open layer of the auxiliary carrier, can be trained.

The resulting connection openings or verbin channels are filled with a typical electroplating process, so that pad layers or pad channels are created.

The galvanic filling takes place in such a way that a total of one flat surface is created.

On the pad layer and the photostructured dielectric The permanent reading layer then becomes a catalyst layer deposited, which makes it possible in a next step Guideways and / or internal connections for or in the multilayer to train.  

Then another photo-structured dielectri cal permanent read layer on the catalyst layer divorced, connecting openings or connecting channels to be released. This connection openings or connec Extension channels in turn serve to accommodate a galvanic one Filling, the further interconnect and / or inner connection layers or contacts.

The semi-additive layer sequence described above can be duplicated one or more times, starting with the Kata lysatorschicht, whereby in the finished bi- or multilayer order of the subcarriers, which stabilize during the Manufacturing process is used, is removable. After the Subcarrier is removed, the first is galvanically in the Separated pad layer on one side outside freely and can be surface-mountable for contacting Components or for normal bonding can be used.

This results in a so-called "pads only design" - Arrangement.

The particular advantage with the arrangement described above voltage according to the basic idea of the invention is that an absolutely laterally flat structure can be realized, and that the procedural implementation is particularly simple, that at least alternately every second contact layer galva is nisch fillable and after the catalytic converter also Signal line layer through the contact on the back Metal layer are galvanically fillable. This corresponds to ver a standard circuit board process on the driving side, which accordingly can be used without significant technological changes can.

According to a second basic concept of the invention, the Subcarrier made of a peelable thin copper foil that is on a carrier film is located. The permanent reading layer is applied to this subcarrier. The connection opening training including galvanic filling  is as in the first principle of the invention according to the first embodiment made.

Instead of the catalyst layer or the catalyst layers however, an anisotropic conductive adhesive film is used as the connection foil used for the layers with each other, so that poss interfering chemical processes that affect the long time stability of the multilayer can be avoided can.

In contrast to the known, this is the basic principle of Invention used photostructurable dielectric Per man resist material not meltable, but includes one Material that remains permanently like a solder mask and the complete embedding of pipes and internal Connections enabled. Further advantages result from the application of a substrate or base material as Subcarriers, e.g. B. a thin copper foil to stabilize sation is connectable with a thicker film, the last tere removable after pressing to the final multilayer is. Incidentally, it should be noted that the one described above Arrangement with regard to the lamination process steps is less critical.

As a photostructurable, i.e. H. photosensitive dielectric Permanent resist material becomes one based on epoxy resin used, which has a low dielectric constant, a low moisture absorption and high glass conversion temperature. The permanent resist is through several Deposition process applicable, e.g. B. in the immersion process, by spin coating or by curtain casting.

For example, the known catalyst is a palladium catalyst usable.

In contrast to complex chemical additive copper copper can drive technologically straightforward according to the invention be galvanically deposited.

The invention is intended below with reference to exemplary embodiments len and explained with the help of figures the.

Here show:

Fig. 1 shows a first example of a connection structure for redistribution layer based on a copper foil as an auxiliary support,

Fig. 2 shows a connection structure for redistribution layer on the basis of a subcarrier, which has a peelable copper foil located on a carrier film and

Fig. 3 is a bi- or multilayer arrangement after lamination with a conventional circuit board and after removal of the metallic subcarrier etch by difference.

The connection arrangement or the bi- or multilayer arrangement according to FIG. 1, which has this, is based on a copper foil 1 as a metallic auxiliary carrier. This subcarrier is used to stabilize the subsequent bi- or multilayer arrangement during the passage of the individual process steps and should therefore have a thickness of at least 35 microns. The electrolytically produced copper foil is processed up to a thickness of 140 µm, but thinner layers are preferred for cost reasons.

In the embodiment shown in FIG. 2, the copper foil 1 preferably consists of two layers which have been galvanically deposited on top of one another via a chromated separating layer. The thin copper foil 11 with a layer thickness of 5 μm or 9 μm remains connected to the bi- or multilayer arrangement subsequently created, while the thick carrier foil 12 serving for stabilization is pulled off at the separation layer with a layer thickness of approximately 70 μm.

In accordance with the exemplary embodiments, a dielectric permanent read layer 3 is applied to the copper foil 1 . The layer thickness usually varies between 25 and 75 µm depending on the application method and subsequent circuit application.

A photo-structuring then reveals openings to the copper foil 1 in the permanent resist layer 3 . A metal layer 2 which is resistant to copper etching agents can be deposited into these openings, so that after later etching back of the copper foil auxiliary support 1, a barrier layer stops the etching process in the area of the openings in the permanent resist. Au, Ni or Sn, for example, is suitable as a metal layer resistant to alkaline etchants. The required tightness is achieved from a layer thickness of 0.2 µm.

In the photostructured openings to the copper foil, a further galvanic filling is then carried out up to the upper limit of the permanent resist layer 3 . The resulting layer thickness scatter for pads or conductor tracks is limited to 5% by a suitable bath geometry and current densities in the range from 0.3 to 1.0 A / dm².

The conductivity of copper foil 1 can be used for galvanic filling.

As a result of the galvanic filling process, the aforementioned pad or interconnect layer is formed, the surface of which is at the same level as that of the permanent tress layer 3 .

Depositing a Kata is then lysatorschicht on the pad or conductive line layer 4 and the surface of the permanent resist layer 3 made 5.

This catalyst layer 5 is used to optimize the subsequent repeated galvanic deposition to form interconnects and / or further internal connections.

A further, second photostructured dielectric permanent read layer 31 is now applied to the catalyst layer 5 .

There existing openings or channels are in turn galvanically filled, so that the mentioned interconnects and / or internal connections 41 arise. The galvanic application step can be repeated so that the necessary thicknesses can be achieved according to the desired electrical properties of the bi- or multilayer arrangement, which is shown in section in FIG. 1.

If necessary, can be electrically contacted for training vertical line crossings a double photostructuring with intermediate removal of the photoresist and he new galvanic deposition analogous to known techniques consequences.

On the process side, in order to form the next level, a catalyst layer 51 is made on the surface of the conductive tracks and / or internal connections 41 and the permanent resist layer 31 .

Now a permanent resesis layer 32 , which is accordingly photostructured, can be deposited, and the resulting openings can be filled using an electroplating process with the aim of realizing further guide layers 42 .

It is obvious that the process described above the formation of a multilayer with the appropriate connection arrangement in a technologically manageable way Plenty of layers, so that the demands on a higher integration rate at the assembly level is sufficient.  

In the exemplary embodiment of the connection arrangement for redistribution layers of a bi- or multilayer arrangement according to FIG. 2, an auxiliary carrier 1 is assumed, which consists of a removable, thin copper foil 11 , arranged on a carrier foil 12 .

The process of depositing the dielectric permanent layer 3 and its photostructuring is carried out in the same way as explained using the exemplary embodiment according to FIG. 1.

The same applies to the formation of the pad or interconnect layer 4 by galvanic filling.

In contrast to the embodiment described above, an anisotropic conductive adhesive film 13 is used as a connecting film for the layers with one another instead of the catalyst layer according to FIG. 2.

In the last process step, after removal of the carrier foil 12, the thin copper foil 11 is free for a rear side metallization. This thin copper foil 11 can also be used for optimal heat dissipation, ie for heat coupling, to an outer housing and for electrical contacting.

By using an anisotropic conductive adhesive film chemical influences due to the use of Kataly sator coating agent, reduced and that for the galvanic Separating the necessary pre-treatment process turns out less expensive.

The exemplary embodiments according to FIGS. 1 and 2 ensure that a layer-by-layer complete embedding of lines and internal connections can be achieved by using a photostructurable permanent resist. Adhesion problems and stray light when exposing the resist material, which arise from wavy, uneven surfaces, are excluded in the exemplary embodiments shown.

In the exemplary embodiment of the connection arrangement according to FIG. 3, a metallic auxiliary carrier 12 is again assumed. However, the connection arrangement here consists of two stacked pad layers 4 . After the first pad layer 4 is electroplated in the permanent resist 31 , a second layer of permanent resist 31 is applied and again a pad layer 4 is electroplated therein.

By tapering the pad structures in the second pad layer, more or larger lateral gaps remain in the permanent dielectric 31 between the pad structures, so that conductor tracks 43 can be passed between the pads of the second pad layer with the next interconnect layer.

Short circuits, which could arise due to incorrect registration during the photostructuring of the dielectric 31 for the interconnect level 42 , are avoided in this way.

In addition, the dielectric distance between the conductors web layers doubled. In signal-critical radio frequency The bi- or multilayer arrangement is therefore used according to applications built this variant.

After catalyzing the permanent resist layer 31, the interconnect 42 was not embedded again in the permanent dielectric, but instead was reinforced on a thin copper layer as a platinum base in a semi-additive way. After the plating base has been removed by means of differential etching, the bi- or multilayer arrangement with the carrier film 12 is positioned outwards in a press package consisting of etched inner layers and prepregs, inserted and pressed or laminated.

The conductor track 42 is embedded by one or more prepregs, so that, as in exemplary embodiments 1 and 2, a planar circuit arrangement with completely embedded conductor tracks and / or internal connections is created. As a result of the method as described above with reference to FIG. 3a, as shown in FIG. 3b, a connection arrangement is formed as a bilayer on a multilayer, pressed by conventional methods of printed circuit board technology.

The inner layers were made in advance as a multilayer in copper technology prefabricated up to layer L3. The connection arrangement according to Exemplary embodiment now realizes for this multilayer outer layers L2 and L1 as well as the inner connections between them L1 / L2.

Since L1 and L2 were previously embedded on the now inner side of the copper foil in a permanent dielectric in accordance with the embodiment according to FIG. 3a, these layers are mirror-inverted to the rest of the multilayer. This is not critical, but must be considered when designing the exposure films.

Due to the layer structure described, the multilayer does not differ from a common multilayer circuit after layer pressing. The auxiliary carrier 12 is pulled off, leaving only a thin copper foil 11 , for. B. between 5 and 12 microns thick, the permanent dielectric and the embedded contact pads for contacting electronic components 6 such as flip chips or ball grid arrays covered. The further steps for the completion of the circuit carrier correspond to the known prior art.

By drilling and making internal connections between the Layers of the multilayer core can also be the layer L2 of the connection arrangement with other layers or to the rear of the Multilayer core via so-called through-contact (DK) pads be connected. When exposing DK pads and other rough ones Structures, e.g. B. electromagnetic shielding on the Top and bottom of the multilayer by etching the outside lying copper foil are also the pads for the later assembly with components free.  

The connections L1 / L2 to the next layer leave no visible traces in these pads, so that bond contacts can also be formed at these points without difficulties. Other micro-contacting methods such as the flip-chips 6 mentioned can also be reliably implemented on these embedded pads.

In contrast to known arrangements, which are metallic Use sacrificial layer is a according to embodiments commercially available copper foil or a laminated copper foil used on the then semi-additive signal line and Kon tact layers can be deposited, so that essential Process simplifications result. In the case when, according to Aus examples, the copper foil etched or peeled off there are extremely smooth and flat pads in the area of the galvanically filled openings, so that there are essential Quality improvements in the electrical contacting of result in surface-mountable components.

Reference list

1 copper foil
2 etching resist layer
3 permanent reading layer
4 pad or interconnect layer
5 catalyst layer
6 electronic assembly
11 thin copper foil
12 carrier film
13 conductive adhesive film
31 Permanent reading layer
41 interconnects and / or internal connections
42 , 43 interconnect
51 catalyst layer

Claims (7)

1. Bi- or multilayer arrangement, consisting at least of
a metallic auxiliary carrier ( 1 ) with a photo-structured, dielectric permanent readout layer ( 3 ) which is arranged on the auxiliary carrier ( 1 ) and wherein the dielectric permanent readout layer ( 3 ) leaves connection openings open;
a pad or interconnect layer ( 4 ) galvanically deposited in the connection openings;
one on the pad or interconnect layer ( 4 ) and the dielectric permanent residual layer ( 3 ) deposited catalyst layer ( 5 ) for forming interconnects and / or internal connections ( 41 );
a further photostructured dielectric permanent resist layer ( 31 ) which is arranged on the catalyst layer ( 5 ) and leaves further connection openings open;
an interconnect and / or inner connecting layer ( 41 ) and
optionally further analog layer sequences, starting with the catalyst layer ( 51 ), the auxiliary carrier ( 1 ) being removed in the finished bi- or multilayer arrangement and the exposed pad or interconnect layer ( 4 ) forming an outer contact surface. 2. bi- or multilayer arrangement according to claim 1, characterized in that the auxiliary carrier ( 1 ) is an etchable copper foil. 3. bi- or multilayer arrangement according to claim 2, characterized in that on the copper foil ( 1 ) in the region of the connection openings, an intermediate layer resistant to copper etchant is arranged. 4. Bi- or multilayer assembly of claim 1, characterized in that the auxiliary carrier is applied from a to a carrier film (12), removable-thin copper foil (11). 5. bi- or multilayer arrangement according to claim 1, characterized in that an anisotropic conductive adhesive film ( 13 ) is provided instead of the catalyst layer ( 5 ; 51 ). 6. Bi- or multilayer arrangement, consisting at least of
a metallic auxiliary carrier ( 12 ) with a photostructured, dielectric permanent readout layer ( 31 ) which is arranged on the auxiliary carrier ( 12 ) and wherein the dielectric permanent readout layer ( 31 ) leaves connection openings free;
a first pad or interconnect layer ( 4 ) galvanically deposited in the connection openings;
a second dielectric permanent read layer ( 31 ) deposited on the first pad or interconnect layer ( 4 ) to form a second pad or interconnect layer ( 4 ), the vertical structure of the second pad or interconnect layer ( 4 ) compared to the first pad or Conductor layer ( 4 ) is tapered to obtain larger lateral gaps in the permanent dielectric, so that conductor tracks ( 43 ) can be guided through here. 7. bi- or multilayer arrangement according to claim 6, characterized in that the layer sequence is pressed with a known multilayer, the at least bilayer layer sequence forming the outer layers of the multilayer and after removal of the auxiliary carrier ( 12 ) the first pad layer ( 4th ) is available as a contact layer for the connection of electronic modules ( 6 ) such as flip chips, ball grid arrays or the like.