DE19650994C1 - Pulse-width modulation (PWM) of rated voltage waveform for three-level four-quadrant control-servo (4QS) e.g. for railway engineering - Google Patents

Abstract

The method involves using pulse-width modulation (PWM) of a voltage in which a reference voltage is compared with a triangular (delta-form) waveform modulation signal. Timed sampled (tk) reference voltage values (u*) are compared with switching lines having maximum (ud) and minimum values (-ud) of the modulating signal.

Description

The invention relates to a method according to the preamble of the An Proverb 1. Such a method is from that in the appendix in the literature list the dissertation of H.P. Worm "increase in out use of high-performance pulse inverters using the three-point method ", Bergische University Comprehensive University Wuppertal, 1983, especially pages 4 to 9 and pages 154/155.

For the control of inverters with a DC link Frequently pulse pattern generators are used which have a desired target voltage by pulse width modulation over a defined time interval. Triangular modulation is a proven method of pulse width modulation for controlling pulse inverters or four-quadrant actuators (4QS) in 2-level technology [1, 2]. Pulse changes are used to increase performance richter or 4QS also partially implemented in 3-level technology [3]. To the Control of these inverters in 3-level technology can also be triangular Design modulation processes that are based on the principle of triangular modulation for Inverters in 2-level technology are similar [4, 5]. A disadvantage of this triangle However, the modulation method is the lack of consideration of the minimum input and Minimum switch-off times of the power semiconductors, whereby the calculated Pulse pattern is falsified during implementation by the converter. Especially These minimum times are considerable for high-performance GTO inverters (<100 µs), which means that these minimum times are neglected in the calculation of the pulse pattern causes unwanted harmonics. One possible ability to avoid falling below the minimum times due to the pulse pattern, is the limitation of the specified target voltage to a sinusoidal one Voltage that only in terms of its angular velocity and amplitude Regulation is adjusted [6]. This sinusoidal target voltage is now so linked to the pulse pattern that the shortfall is exceeded is closed. A disadvantage of this method is that the regulation of the angle  the sinusoidal voltage only indirectly via the angular velocity can set and the achievable control dynamics is thus reduced. Furthermore, only sinusoidal target voltages can be realized. Soon proportions and higher harmonics are not possible with this definition bar.

In railway technology 4QS several modules via galvanically ent coupled transformer windings are often connected to the railway network (for example, GTO inverter 3-level technique. Figure 1 u. 2). In Figure 1, the converter windings of the transformer are connected in series so that the pulsating voltages of the 4QS modules add up. By staggering the 4QS modules with each other, the harmonics in the rail network can be significantly reduced - with the 3-level technology, the low permissible harmonic limit values of the rail can be maintained even at low pulse frequencies if the pulse pattern is implemented correctly.

The invention has for its object a method of the aforementioned Specify type, which a largely freely definable target voltage under On Maintaining the maximum pulse frequency modulated without losing the minimum times to fall below the power semiconductor. Furthermore, the burden the center of the DC link by coordinating the 4QS modules to optimize others.

This object is characterized according to the invention by the in claim 1 Features resolved.

The minimum input and Minimum switch-off times of the power semiconductors, compliance with the pre given maximum pulse rate and an optimal symmetrical load of the Intermediate circuit center while providing the possibility of intervention for DC link voltage balancing.

In detail, the method according to the invention is used as follows:

Pulse pattern generator for a four-quadrant actuator

In triangular modulation, the switching times of the pulse pattern are derived from the comparison of the desired voltage to be modulated with a triangular modulation carrier (or triangular signal). In this way, Figure 3 modulates the setpoint voltage u *, which is time-discretely, by means of a pulse pattern with two switching states (2-level pair of branches). The time-discrete setpoint voltage u * can be updated at each peak of the triangular signal, because in the time interval [t _k , t _{k + 1} ] between two peaks, the triangular modulation generates a switching edge with which the setpoint voltage is set on average over this time interval ( Regular sampling). The length T _A (k) of the time interval [t _k , t _{k + 1} ] is therefore equal to half the period of the triangular signal, the mean pulse frequency f _{P being} determined via the frequency of the triangular signal:

A 3-level branch pair - two 3-level branch pairs form a 3-level 4QS - now has three switching states +, 0 or - and can use these three different potentials ½u _d , 0 V, -½u _d (with u Connect _d1 = u _d2 = ½u _d ) to terminals A and B ( Fig. 2). For triangular modulation, two of the triangle signals used in Figure 3 are required, which are phase-shifted from each other by 180 ° ( Figure 4). If the time-discrete setpoint voltage crosses a triangular signal, the 3-level branch pair changes the switching state. Which switching state is to be assumed after crossing a triangular signal must be entered in the arrangement of the triangular signals ( Figure 4), since the individual triangular signal can no longer be assigned a potential setting command for a specific bridge branch, which must be switched in the event of a crossing through the setpoint voltage . The individual triangle signals are therefore no longer considered in the following, since they are only relevant for an analog implementation of the pulse pattern generator anyway. Only the switching lines formed by the triangular signals are decisive for the pulse pattern. (However, the specification of phase shifts still refers to the individual triangle signals.) The time intervals [t _k , t _{k + 1} ], over which the time-discrete set voltage u * is specified, are now determined from the peaks and the crossing points of the triangle signals ( Fig 4). Over these time intervals, the target voltage u * is set on average with one switching edge. The length of the time interval T _A (k) is therefore:

A 3-level 4QS consists of two 3-level branch pairs ( Figure 2), which can switch independently of one another. Table 1 shows the respective voltage u _AB = v _A -v _B , the load on the intermediate circuits and the current-carrying semiconductors for the total of 3 ² = 9 possible switching states of a 3-level 4QS. The _{DC link voltages} u _d1 and u _d2 are assumed to be the same size.

Load on the intermediate circuits and the semiconductors of a 3-level 4QS depending on the switching status (for designations see Figure 2)

Load on the intermediate circuits and the semiconductors of a 3-level 4QS depending on the switching status (for designations see Figure 2)

In order to achieve an offset timing of the branch pairs, the two triangular signals of the 3-level branch pairs ( Figure 4) with which the switching lines are constructed are shifted in phase by 90 °. The switching states of the 3-level 4QS can be entered in the arrangement of the switching lines ( Figure 5) (+, 0 or - for branch pairs A and B, e.g.: + - for v _A = ½u _d , v _B = -½u _d ). There are now various switching states that are redundant with regard to the voltage u _AB generated at terminals A, B ( Figure 2): +0 and 0- for u _AB = ½u _d , 0+ and -0 for u _AB = -½u _d , - and 00 and ++ for u _AB = 0 V (u _d1 = u _d2 provided) (see Table 1). As a result, there are various ways of assigning these switching states to the triangular signals. Figure 5 shows two variants a and b of the assignment of the switching states with which the same voltage u _{AB is} generated for any time-discrete setpoint voltage. In analogy to triangular modulation for a 3-level bridge branch ( Fig. 4), the discrete-time setpoint voltage can in turn be updated for each crossing point of the switching lines, because it generates the time interval [t _k , t _{k + 1} ] between two crossing points Triangular modulation is a switching edge with which the target voltage is set on average over this time interval. The following applies to the length of the time interval T _A (k):

So all switching edges can be used as a setting for the control. These time intervals [t _k , t _{k + 1} ] can be selected at the same time as sampling intervals of the control.

The modulation process ( Fig. 5) must ensure a symmetrical load on the power semiconductors and the intermediate circuits when converting the target voltage and also comply with the limit values specified by the power unit with regard to the maximum pulse frequency and minimum times T _{min of} the GTO. The switching states, which are redundant with respect to the generated voltage u _AB, have different loads on the power semiconductors and intermediate circuits. If the target voltage and the load-dependent current are assumed to be sinusoidal and the switching lines of the modulation process are synchronous with the period of the target voltage, symmetrical loading of the power semiconductors and intermediate circuits can be achieved with an alternating distribution of the switching states that are redundant with respect to u _AB . The modulation variants ( Figure 5) show two options for the alternating distribution of these switching states.

To maintain the maximum permissible pulse frequency of the GTO, it is assumed that the modulation method generates exactly one switching edge in each time interval t ∈ [t _k , t _{k + 1} ] and the switching edges are distributed evenly on average to the GTO. Under this condition, the pulse frequency of the GTO is equal to the frequency of the individual triangle signals that form the switching lines and can therefore be easily determined. When looking at the curves of the target voltage u * and the voltage u _AB generated with the modulation method, which is exemplarily sketched in Figure 5, it becomes clear that in addition to the switching edges mentioned above, additional switching edges occur in the time intervals t ∈ [t _k , t _{k + 1} ] , if the time-discrete target voltage u * at the sampling times (e.g. at t _{k + 1} and t _{k + 7} ) intersects the crossing points of the switching lines. If these additional switching edges are permitted, it is difficult to ensure the maximum pulse frequency. To avoid these additional switching edges, changes in the target voltage beyond the crossing points must be prohibited, even if the desired target voltage is not exactly achieved as a result. Figure 7 shows an example of how the desired setpoint voltage is modified in order to avoid additional switching edges (dashed line for the desired setpoint voltage u *, solid line for the modified setpoint voltage).

Finally, the modulation process to ensure error-free implementation of the target voltage u * must adhere to the permissible minimum switch-on and switch-off times of the GTO. Otherwise, the pulse formation is forced to falsify the pulses calculated for the target voltages. In Figure 5, the voltage u _AB generated has switching edges that follow one another very closely in the vicinity of the sampling times t _{k + 3} , t _{k + 6} and t _{k + 8} . If the modulation process realizes these switching edges with a 3-level pair of branches, there is a risk of violating the minimum times of the GTO. In the vicinity of t _{k + 8} , both modulation variants use the switching sequence + -, 0-, + - in order to implement the target voltages, which are close to the modulation limit of the modulation process. Both variants therefore carry out two circuits in succession with branch pair A, which violates the minimum times. However, this is unavoidable at high levels and can only be avoided by limiting the target voltage. This is different for the switching edges around t _{k + 3} , which are implemented in the modulation variant a with the switching sequence 0+, - +, -0 and in variant b with the switching sequence 0+, - +, 0+. While the two switching edges in variant a are implemented with different branch pairs, variant b only uses branch pair A and it is possible that the minimum times are undershot. The reverse occurs for the switching edges around t _{k + 6} . Here variant a with 00, +0.00 only uses branch pair A and variant b with 00, 0-, - both branch pairs, ie variant a threatens to fall below the minimum times. In general:

• - Modulation variant a is unsuitable for target voltages u * near 0 V.
• - Modulation variant b _is unsuitable for target voltages u * close to ± ½u _d .

In order to achieve a modulation of the target voltage u * without falling below the minimum GTO times, the pulse pattern generator must not work rigidly according to one modulation variant, but must switch flexibly between the two modulation variants a and b: If the pulse pattern generator uses variant a, then Each sampling time with the switching states +0, 0+, 0- or -0 checked whether the specified target voltage u * could fall below the minimum time T _min in the following sampling steps (whereby T ' _min becomes sufficient with safety margin to T _min is selected):

In this case, switch to modulation variant b in accordance with the arrows shown in Figure 5, without additional switching being required. Now the pulse pattern generator uses modulation variant b for the next six scanning steps and then switches back to variant a according to the arrows when condition (4) is no longer fulfilled. If (4) is not fulfilled, modulation variant b is continued for a further six scanning steps. Figure 6 shows two different changes between the modulation variants. With the novel method of triangular modulation for 3-level 4QS described here, errors in the modulation of an approximately sinusoidal target voltage u * due to the minimum times being undershot can be avoided without generating additional switching edges. The setpoint voltage u * can therefore not be achieved exactly if it reaches too close to the modulation limit (e.g. at t _{k + 8} in Fig. 5) or if it changes in one scanning step beyond a crossing point of the switching lines becomes.

The balancing of the DC link voltages can be easily implemented with both modulation variants by giving up the strict sequence of the switching states and exchanging redundant switching states with regard to u _AB . For example, in variant a, the switching states 0- and -0 can be replaced by the switching states +0 and 0+ in individual time intervals (e.g. in the interval [t _k + ₃ , t _k + ₅ ] ( Fig. 5)) create an imbalance in the load on the individual intermediate circuits and thus achieve dynamic symmetry. The procedure for variant b is the same, but a group of two identical switching states must always be changed here (such as 0- and -0 in the interval [t _k +5, t _{k + 9} ] ( Figure 5) ). If switching states are exchanged in variant a, the current target voltage must be checked beforehand. If this is in the vicinity of ± ½u _d , there is a risk that the minimum times may not be met, contrary to the normal case, since the switching branch pairs no longer alternate due to the exchange.

Pulse pattern generator for two four-quadrant actuators

The modulation method developed for a 3-level 4QS is expanded in the following for the control of two 3-level 4QS, which are connected in series via the rail network transformer. (The 4QS modules 1 and 3 are connected to the converter-side windings, while the other two windings are open ( Figure 1).) For the triangular modulation, the switching lines according to Figure 5 are used for each 3-level 4QS, whereby in the sense of offset, the individual triangle signals of the switching lines (with ± u _d as peak values) for the first and second 3-level 4QS are shifted in phase by 45 ° ( Fig. 6). In section 1, the times t _k for updating the time-discrete set voltage u * time were selected to be the same as the crossing points of the switching lines of a 3-level 4QS ( Figure 5). In the switching lines for two 4QS modules constructed by phase shifting, the crossing points continue to occur simultaneously ( Figure 6). The voltage setpoints u of the two 4QS modules can thus be specified simultaneously at the common times t _k .

For the investigation of the DC link center load of the pulse pattern of the individual 3-level 4QS and the resulting total load of the DC link center of both 3-Level 4QS, the auxiliary variables pn _{i are} introduced, which are defined as follows: At the time intervals at which the Pulse pattern that the switching states +0 and 0+ can assume is pn _i : = 1 and at the other time intervals in which the switching states -0 and 0- can occur, pn _i : = - 1 ( Figure 6). The actual load on the intermediate circuit center cannot be read from the auxiliary variables pn _i alone, since the duration of the switching states (+0, 0+, -0, 0-), which is dependent on the modulated target voltage, and the current profile are not taken into account. Nevertheless, the symmetry of the load on the intermediate circuit center can be analyzed on the basis of the auxiliary variables pn _i if target voltages and currents are assumed to be approximately sinusoidal. With pn _i = 1, only the positive DC link is loaded depending on the sign of the current and set voltage, while with pn _i = -1 the negative DC link is loaded in the same way and the asymmetry is thus compensated for if current and set voltage are assumed to be unchanged . Looking at pn ₁ and pn ₃ , the center load alternates with the modulation variant a compared to the variant b with twice the frequency. Since the pulse pattern generator to avoid the underflow of minimum times each procedure b for multiples of six time intervals after modulation variant, the symmetry of each center load is pn ₁ and pn ₃ independent of the modulation variation and also the symmetry of the sum of the loads pn ₁ + pn ₃ ensured ( picture 6).

Since the individual target voltages u * _{2B, 1} and u * _{2B, 3 of} the 3-level 4QS are almost identical in steady-state operation, the condition (4) for using the modulation variant b for both 3-level 4QS becomes roughly the same be fulfilled. To optimize the common DC link center load pn ₁ + pn ₃ , it is advantageous to coordinate the change of the modulation variant of the two 4QS modules with each other: Due to the offset timing, there is only one 3-level 4QS at any time t _k a switching state (+0, 0+, 0- or -0) to which the modulation variant can be changed without causing additional switching edges. If the condition (4) for a change is met at a point in time t _k , the modulation variant of the 3-level 4QS with the corresponding switching state is changed at this point in time and also the modulation variant of the other 3-level at the following point in time t _{k + 1} -4QS changed. The switching states relevant for the center point load (+0, 0+, 0-, -0) are selected so that pn ₁ and pn ₃ cancel each other out as much as possible. Figure 6 shows two changes in the modulation variant for the pair of 3-level 4QS that are optimal with regard to the center load.

To avoid additional switching edges, changes in the target voltage beyond the crossing points of the switching lines are not permitted (Section 1). However, this means that the desired target voltage, as in the example in Figure 7, cannot be achieved exactly. If this voltage error is not corrected, undesirable harmonics arise. The correction of the voltage error in the subsequent time interval only achieves an insufficient improvement in the harmonic content. An effective correction of the voltage error can only be achieved by coordinating the two 3-level 4QS: Due to the offset timing of the 3-level 4QS, the crossing points of the switching lines of the modulation methods are also offset from one another ( Figure 7). If approximately the same target voltages are required for the two 3-level 4QS, the target voltage will only be limited by the crossing points in one of the two 3-level 4QS, while the other can be used to compensate for the resulting incorrect voltage ( Image 7).

Pulse pattern generator for four four-quadrant actuators

To expand the modulation process for a pair of two 3-level 4QS (section 2) to two pairs of a total of four 4QS modules, the individual triangle signals of the switching lines (with ± u _d as peak values) of the respective pair are used ( Figure 6) ( 4QS module 1 and 3 or 2 and 4 in Figure 1) shifted again by 22.5 ° against each other in phase. While in the modulation method for two 3-Le vel-4QS there are still common times t _k for updating the time-discrete set voltage u ( Figure 6), the times t _k ^g and t _k ^{h of} the two pairs of 4QS modules are now offset from one another ( Image 8). If the lengths T _A ^g (k), T _A ^h (k) of the time intervals [t _k ^g , t _{k + 1} ^g ], [t _k ^h , t _{k + 1} ^h ] are varied during operation, then for Ensure the offset clocking are taken care of. The lengths of the time intervals are therefore determined depending on one another:

Finally, the DC link center load on the four 3-level 4QS should be considered again. For the pairs of the 3-level 4QS, the common center load was already optimized in section 2 ( Figure 6). To optimize the overall center load of the four 3-level 4QS, the already defined center loads of the pairs pn ₁ + pn ₃ and pn ₂ + pn ₄ are offset against each other in such a way that they cancel each other out as much as possible. Figure 9 shows two options for the displacement of pn ₁ + pn ₃ and pn ₂ + pn ₄ (curves according to Figure 6a), of which the second option has a significantly lower load in the total center load and is therefore preferable. (For other combinations of the courses of pn ₁ + pn ₃ and pn ₂ + pn ₄ na ₉ h Fig. 6a and 6b, the second option is also the cheaper one). The resulting assignment of the switching states to the switching lines is shown in Figure 8.

literature

[1] Yoone, H.K .; Mehrdad E .: An Algebraic Algorithm for Microcomputer-Based (Direct) Inverter Pulse Width Modulation; IEEE Trans. Ind. Appl., Vol IA-23, No. 4, July / August 1987 654-660.

[2] Bose, B.K .; Sutherland, H.A .: A High-Performance Pulsewidth Modulator for an Inverter Fed Drive System Using a Microcomputer; IEEE Trans. Ind. Appl., Vol IA-19, No. 2, March / April 1983 235-243.

[3] Wurm, H. P .: Increasing the utilization of high-lei pulse inverters by the three-point method; Dissertation, Bergische Universität-Ge velthochschule Wuppertal, 1983, in particular pp. 4 to 9 and pp. 154/155.

[4] Garrara, G .; Gardella, S .; Marchesoni M .; Salutari, R .; Sciutto, G .: A new Multilevel PWM Method: A Theoretical Analysis; IEEE Trans. Power Electron., Vol. 7, No. 3, July 1992.

[5] Velaerts, B .; Mathys, P .; Tatakis, E .; Bingen, G .: A novel Approach to the Generation and Optimization of Three-Level PWM Wave Forms; Pesc 1988, p. 1255-1262.

[6] Stanke, G .: Investigation of modulation methods for pulse converters with high dynamic requirements with limited switching frequency; Dis at the Rheinisch-Westfälische Technische Hochschule Aachen 1987, especially pp. 18 to 33.

Claims (3)

1. Method for pulse width modulation of a target voltage specified by a control by comparing this target voltage with a triangular modulation signal for one or more 3-level four-quadrant actuators (4QS modules), which are decoupled via galvanically independent transformer windings,
characterized in that
the time-discrete setpoint voltage u * is compared with switching lines which are formed from four triangular signals, each offset by 90 °, with u _d as the maximum value and -u _d as the minimum value, where u _{d is} the sum of the two intermediate circuit voltages U _d1 and U _d2 ,
that the sampling times t _k , at which the time-discrete target voltage u * is updated, are selected synchronously with the crossing points of the switching lines,
that the respective switching state of the 4QS module is assigned to the areas formed by the switching lines, in which the 4QS module changes at the moment when the target voltage u * crosses the switching lines delimiting the area and reaches this area,
that these switching states are distributed according to two different variants a and b of the formed by the shift lines areas that gene using this distribu u for each constant desired voltages * = - _^2/3 u _d, ¹ / U _{D 3,} ¹ / ₃ u _{d, ^2/3 of} u _d u _d = u _d1 + u _d2 and u _d1 = u _d2 at the sampling instants t _k, the potentials v _A (t _k) and V _b (t _k) to the off transitions of the 3 -Level bridge branches for variant a after
and for variant b after
surrender
that the pulse pattern generation during operation can either be carried out according to variant a or b of the distribution of the switching states of the 4QS module and a change between the variants is permitted at those sampling times t _{k + 1} at which the switching states of variant a and b match,
that in principle if condition (1) is fulfilled
Variant b is used and if (1) variant a is not used, where u * (t _k ) and u * (t _{k + 1} ) are two consecutive time-discrete target voltages and the maximum minimum switch-on and switch-off time for T _min Power semiconductor is selected,
that each variant, regardless of this condition, always uses exactly as many sampling intervals that the alternating sequence of the assignment of the switching states +0 and 0-- (or 0+ and -0) for variant a and the alternating sequence +0, + +, +0 and 0-, -, 0- (or 0+, ++, 0+ and -0, -, -0) for variant b is completed
and that
for symmetrizing the DC link center point voltage from the alternating sequence of the assignment of switching states +0 and 0- (or 0+ and -0) in variant a and from the alternating sequence +0, ++, +0 and 0-, - , 0- (or 0+, ++, 0+ and -0, -, -0) in variant b by deviating individual assignments of the switching states +0 (or 0+) and 0- in variant a (or -0) are exchanged for each other and in variant b the consecutively assigned switching states +0, ++, +0 (or 0+, ++, 0+) and 0-, -, 0- (or . -0, -, -0) can be exchanged for each other. 2. The method according to claim 1, characterized in that
when using two 4QS modules, which are magnetically connected in series or in parallel via two open transformer windings, the switching lines of the 4QS modules are offset against one another in such a way that the respective switching lines of the 4QS modules form groups of triangle signals offset by 90 ° are additionally offset from one another by 45 °,
that the changes of variants a and b of the assignment of the switching states to the switching lines used are carried out in two successive sampling times for both 4QS modules,
that a change from variant a to variant b is initiated for the 4QS modules as soon as condition (1) is fulfilled for one of the two time-discrete set voltages of the 4QS modules u * _{2B, 1} or u * _{2B, 3} and a change from Variant b to variant a is initiated for the 4QS modules if this condition is no longer fulfilled, after a fixed number of scanning steps, the method is changed back to variant a if condition (1) for one of the two target voltages is no longer fulfilled ,
that the sequence of assignment of the alternating switching states of each 4QS module, which is determined with the variant used, is completed regardless of the condition mentioned,
that when initiating a change in the assignment of the switching states from variant a to variant b with the alternating sequence of switching states +0, ++ +0 and 0-, -, 0- (or 0+, ++, 0+ and -0, -, -0) of variant b of the last changing 4QS module is just started so that it is inverse to the alternating sequence of switching states of the first changing 4QS module,
that the specified time-discrete nominal voltages of the 4QS modules u * _{2B, 1} and u * _{2B, 3} are limited so that they only change within a range of switching lines at the sampling times and no switching states occur at the sampling times
and that the fault voltage occurring in the target voltage of one 4QS module due to such limitations is added to the target voltage of the other 4QS module and is thus compensated for. 3. The method according to claim 1 or 2, characterized in that
when using four 4QS modules that are magnetically connected in series or in parallel via four open transformer windings, the switching lines of the 4QS modules are offset against one another so that the respective switching lines of the 4QS modules are formed by groups Triangle signals offset by 90 ° are additionally offset by 22.5 ° against each other,
that the time-discrete nominal voltages of the pairs of 4QS modules u * _{2B, 1} , u * _{2B, 3} and u * _{2B, 2} , u * _{2B, 4} are specified according to the crossing points of the switching lines at mutually offset sampling times,
that the alternating sequences of the assignments of the switching states +0 (or 0+) and 0- (or -0) according to variant a to the switching lines of the pairs of 4QS modules with synchronous sampling times are selected so that if for a pair too the switching states +0 (or 0+) are selected two consecutive sampling times, the switching states 0- (or -0) are selected for the other pair at the sampling times offset by 22.5 °
and that the change between the variants of the assignment of the switching states is carried out independently for the respective pair of 4QS modules with synchronous sampling times.