WO2014082221A1 - Multi-level converter apparatus with efficiency improving current bypass - Google Patents

Multi-level converter apparatus with efficiency improving current bypass Download PDF

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Publication number
WO2014082221A1
WO2014082221A1 PCT/CN2012/085439 CN2012085439W WO2014082221A1 WO 2014082221 A1 WO2014082221 A1 WO 2014082221A1 CN 2012085439 W CN2012085439 W CN 2012085439W WO 2014082221 A1 WO2014082221 A1 WO 2014082221A1
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WO
WIPO (PCT)
Prior art keywords
common node
connected
configured
dc
transistors
Prior art date
Application number
PCT/CN2012/085439
Other languages
French (fr)
Inventor
Leisure CAO
Zhongyong XU
David ZHENG
Ben Yang
George W. Oughton, Jr.
Original Assignee
Eaton Corporation
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Priority to PCT/CN2012/085439 priority Critical patent/WO2014082221A1/en
Publication of WO2014082221A1 publication Critical patent/WO2014082221A1/en

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Classifications

    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/483Converters with outputs that each can have more than two voltages levels
    • H02M7/487Neutral point clamped inverters
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00Details of apparatus for conversion
    • H02M2001/0048Circuits or arrangements for reducing losses
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/02Conversion of ac power input into dc power output without possibility of reversal
    • H02M7/04Conversion of ac power input into dc power output without possibility of reversal by static converters
    • H02M7/06Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes without control electrode or semiconductor devices without control electrode
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02BCLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion
    • Y02B70/14Reduction of losses in power supplies
    • Y02B70/1491Other technologies for reduction of losses, e.g. non-dissipative snubbers, diode reverse recovery losses minimisation, zero voltage switching [ZVS], zero current switching [ZCS] or soft switching converters

Abstract

An apparatus includes a multi-level converter circuit (e.g., a neutral-point-clamped (NPC) converter circuit) configured to selectively couple first and second DC buses to a common node. The apparatus further includes first and second bypass circuits (e.g., diodes) coupling the common node to respective first and second ones of the DC busses. The first and second bypass circuits may be configured to provide unidirectional conduction paths between the common node and respective ones of first and second DC buses. In some embodiments, the multi-level converter circuit and the first and second bypass circuits are configured to support four quadrant operation, wherein the first and second bypass circuits conduct current in a first two quadrants and block current in a second two quadrants. The apparatus may be used, for example, as a rectifier and/or inverter in an uninterruptible power supply (UPS).

Description

MULTI-LEVEL CONVERTER APPARATUS

WITH EFFICIENCY IMPROVING CURRENT BYPASS

BACKGROUND

[0001] The inventive subject matter relates to power electronic circuits and, more particularly, to converter apparatus.

[0002] Power inverters, uninterruptible power supply (UPS) systems, motor drives, battery chargers and other power conversion devices commonly use converter circuits that transform an AC voltage to a DC voltage or vice versa. For example, an online UPS system may include a rectifier configured to be connected to an AC source and configured to generate a DC voltage on a DC bus, and an inverter connected to the DC bus and configured to generate an AC voltage to be applied to a load.

In some applications, such as high-power or high-voltage applications, multi-level converters, such as neutral-point-clamped (NPC) converters, may be used as rectifiers and/or inverters. Various multi-level converter circuits are described, for example, in U.S. Patent No.

5,361,196 to Tamamachi et al., U.S. Patent No. 6,795,323 to Tanaka et al., U.S. Patent No. 6,838,925 to Nielsen, U.S. Patent No. 7,145,268 to Edwards et al. and U.S. Patent No.

7,573,732 to Teichmann et al. Uses of multi-level converters in UPS applications are described in U.S. Patent Application Serial No. 13/105,700 entitled Power Conversion Apparatus and Methods Employing Variable-Level Inverters, filed May 22, 2011 and assigned to the assignee of the present application and U.S. Patent Application Serial No. 13/537,316 entitled Multi-Level Inverter Apparatus and Methods Using Variable Overcurrent Response, filed June 29, 2011 and assigned to the assignee of the present application.

SUMMARY

[0003] Some embodiments of the inventive subject matter provide an apparatus including a multi-level converter circuit configured to selectively couple first and second DC buses to a common node. The apparatus further includes first and second bypass circuits coupling the common node to respective ones of the first and second DC busses. The first and second bypass circuits may be configured to provide unidirectional conduction paths between the common node and respective ones of the first and second DC buses. The first and second bypass circuit may include, for example, respective first and second diodes. In some embodiments, the multi-level converter circuit and the first and second bypass circuits are configured to support four quadrant operation, wherein the first and second bypass circuits conduct current in a first two quadrants and block current in a second two quadrants.

[0004] The multi-level converter circuit may include first and second pluralities of serially-connected switching devices connected between the common node and respective ones of the first and second DC buses and configured to selectively provide respective first and second switched conduction paths between the common node and a neutral node. The multi-level converter circuit may further include a control circuit configured to control the first and second pluralities of serially-connected switching devices. The control circuit may be configured to modulate respective first switching devices from respective ones of the first and second pluralities of switching devices to operate the multi-level converter circuit as a multi-level converter while the first bypass circuit is conducting current between the first DC bus and the common node. The control circuit may be further configured to modulate respective second switching devices from respective ones of the first and second pluralities of switching devices while the second bypass circuit is conducting current between the second DC bus and the common node.

[0005] Further embodiments provide an apparatus including first and second diodes connected between respective first and second DC buses and a common node. A first plurality of serially-connected transistors is connected between the common node and the first DC bus. A second plurality of serially-connected transistors is connected between the common node and the second DC bus. A third diode is connected between a neutral node and a node of the first plurality of transistors, and a fourth diode is connected between the neutral node and a node of the second plurality of transistors. The apparatus further includes at least one inductor having a first terminal connected to the common node, and a control circuit configured to control the first and second pluralities of transistors.

[0006] The control circuit may be configured to provide four quadrant operation, wherein the first and second diodes are configured to conduct current in a first two quadrants and to block current in a second two quadrants. The control circuit may be configured to modulate respective first transistors of the first and second pluralities of transistors to regulate a voltage of the first DC bus when the first diode is conducting current between the first DC bus and the common node. The control circuit may be further configured to modulate respective second transistors of the first and second pluralities of transistors to regulate a voltage of the second DC bus when the second diode is conducting current between the second DC bus and the common node. [0007] Additional embodiments provide an uninterruptible power supply (UPS) system including a first converter configured to be connected to an AC source, a second converter configured to be connected to a load and first and second DC buses coupling the first and second converters. At least one of the first and second converters includes a multilevel converter circuit configured to selectively couple the first and second DC buses to a common node and first and second bypass circuits coupling the common node to respective first and second ones of the DC buses.

[0008] The at least one of the first and second converters may include first and second diodes connected between respective ones of the first and second DC buses and the common node, a first plurality of serially-connected transistors connected between the common node and the first DC bus, a second plurality of serially-connected transistors connected between the common node and the second DC bus, a third diode connected between a neutral node and a node of the first plurality of transistors, and a fourth diode connected between the neutral node and a node of the second plurality of transistors.

[0009] In some embodiments, the first converter may include a first multi-level converter circuit configured to selectively couple the first and second DC buses and a neutral node to a first common node, first and second bypass circuits coupling the first common node to respective first and second ones of the DC busses and a first inductor connected between the first common node and the AC input. The second converter may include a second multilevel converter circuit configured to selectively couple the first and second DC buses and the neutral node to a second common node and a second inductor connected between the second common node and the AC output. In some embodiments, the at least one of the first and second converters may be configured to operate as a rectifier.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] FIG. 1 is a schematic diagram illustrating a converter according to some embodiments of the inventive subject matter.

[0011] FIG. 2 is a schematic diagram illustrating operations of the converter of FIG. 1 according to further embodiments.

[0012] FIGs. 3-6 are schematic diagrams illustrating current flows in the converter of FIG. 1 for various operational quadrants.

[0013] FIGs. 7-11 are schematic diagrams illustrating various arrangements of power conversion circuitry for uninterruptible power supplies according to further embodiments. DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

[0014] Specific exemplary embodiments of the inventive subject matter now will be described with reference to the accompanying drawings. This inventive subject matter may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the inventive subject matter to those skilled in the art. In the drawings, like numbers refer to like elements. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. As used herein the term "and/or" includes any and all combinations of one or more of the associated listed items.

[0015] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the inventive subject matter. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless expressly stated otherwise. It will be further understood that the terms "includes," "comprises," "including" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

[0016] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this inventive subject matter belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0017] Some embodiments of the inventive subject matter arise from a realization that improved performance may be achieved in rectifiers, inverters and other converters by using a multi-level converter circuit in combination with reduced-loss bypass paths that may be used to provide bulk current transfer while the multi- level converter provides voltage regulation using currents that may be reduced in comparison to conventional multi-level converter architectures. In some embodiments, for example, such a structure may provide four-quadrant operation in which the bypass circuits support current flow in two quadrants and block current flow in two other quadrants. In some applications, such as in uninterruptible power supply (UPS) applications, such converter structures may be used advantageously to provide improved efficiency. In particular, in online type UPS systems that include a rectifier/inverter chain, using a converter structure according to some embodiments for the rectifier may significantly reduce converter losses. Such converter structures may also reduce voltage spikes arising from interconnection inductance, thus reducing stress on components and enabling the elimination of snubber circuits and other protective measures.

[0018] FIG. 1 illustrates a converter apparatus 100 according to some embodiments of the inventive subject matter. The apparatus 100 includes a power conversion circuit 110 including a multi-level neutral-point-clamped (NPC) converter circuit 112 including a first plurality of serially-connected transistors Tl, T2 connected to a positive DC bus DC+ and a second plurality of serially-connected transistors T3, T4 connected to a negative DC bus DC-. The first plurality of transistors Tl, T2 and the second plurality of transistors T3, T4 are connected to one another at a common node 101. Respective neutral point clamping diodes D2, D3 are connected between intermediate nodes 102, 103 at which the transistors Tl, T2 and T3, T4 are joined and to a neutral node N. Integral or discrete antiparallel diodes D5, D6 may be connected across the inner transistors T2, T3 to prevent reverse conduction therethrough in the event of a transient negative collector-to-emitter voltage that might damage these transistors. An input inductor L is connected between the common node 101 and a filter capacitor Cf at a node 104 that may serve as a connection point for an AC source and/or load. Respective energy storage capacitors Cp, Cn are connected to respective ones of the DC buses DC+, DC-. The transistors Tl, T2, T3, T4 are illustrated in FIG. 1 as insulated gate bipolar transistors (IGBTs), but it will be appreciated that other devices, such as power MOSFETs, may be used instead of or in combination with IGBTs. It will also be understood that respective diodes may be connected across respective ones of the transistors Tl, T2, T3, T4, in the form or individual discrete diodes or in the form of diodes integrally packaged with the transistors Tl, T2, T3, T4 in, for example, a so-called "co-pack" arrangement.

[0019] The apparatus 100 further includes first and second bypass circuits that are configured to provide unidirectional conduction between the common node 101 and the DC buses DC+, DC-. In the apparatus 100, these bypass circuits take the form of diodes Dl, D4 connected between respective ones of the DC buses DC+, DC- and the common node 101. When forward biased, the bypass diodes Dl, D4 divert current around respective upper and lower portions of the multi-level NPC converter circuit 112. It will be appreciated that, while the apparatus 100 utilizes diodes Dl, D4 to partially bypass the NPC multi-level converter circuit 110, other circuit arrangements may be used to perform a similar function, such as actively switched devices. It will also be understood that, while FIG. 1 illustrates use of a NPC converter 112, other types of multi-level converters may be used in some embodiments of the inventive subject matter.

[0020] Still referring to FIG. 1, a control circuit 120 controls the transistors Tl, T2, T3, T4. In particular, the control circuit 120 may, for example, pulse-width modulate the transistors Tl, T2, T3, T4 to regulate voltages produced at the DC buses DC+, DC- responsive to an AC voltage Vac applied to the inductor L. As shown in FIG. 2, when the AC voltage Vac is positive, a substantial portion of a positive input current IL flows through the diode Dl to the positive DC bus DC+, bypassing transistors T1,T2. Multi-level operation is provided by modulating the upper outer transistor Tl and the lower inner transistor T3 in a complementary fashion to selectively route current to the neutral node and thereby control the DC voltage on the positive DC bus DC+. Similarly, when the AC voltage Vac is negative, current flows from the negative DC bus DC- through the diode D4. Upper inner transistor T2 and lower outer transistor T4 may be modulated to regulate the voltage produced on the negative DC bus DC-.

[0021] In some embodiments, the control circuit 120 may operate the transistors Tl, T2, T2, T4 to provide four-quadrant operation wherein the bypass diodes Dl, D4 conduct current in two of the quadrants and block current in two other of the quadrants. FIG. 4 illustrates a first quadrant operation in which the AC voltage Vac is positive and the current IL is positive (i.e., flowing from the inductor L into the common node 101). In this quadrant, current flows through the bypass diode Dl to the positive DC bus DC+ and through the lower inner transistor T3 to the neutral node N. In a second quadrant of operation shown in FIG. 4 in which the AC voltage Vac is positive and the current IL is negative, current flows from the positive DC bus DC+ to the inductor L via the upper outer and inner transistors Tl, T2 and from the neutral node N through the upper inner transistor T2 to the inductor L. In a third quadrant of operation illustrated in FIG. 5 in which the AC voltage Vac is negative and the current IL is negative, current flows from the negative DC bus DC- through the bypass diode D4 to the inductor L and from the neutral node N through the upper inner transistor T2 to the inductor L. In fourth quadrant operations illustrated in FIG. 6 wherein the AC voltage Vac is negative and the current IL is positive, current flows from the inductor L through the lower inner and outer transistors T3, T4 to the negative DC bus DC- and from the inductor L through the lower inner transistor T3 to the neutral node N. [0022] It will be appreciated that the first and third quadrant operations shown in FIGs. 3 and 5 may correspond to operating the converter 100 as a rectifier delivering real power to the DC buses DC+, DC- from an AC source or as an inverter delivering reactive power from the DC buses DC+, DC- to an AC load. In the first and third quadrant operations, a substantial portion of the current delivered may pass via the bypass diodes Dl, D4, which can reduce switching and conduction losses in the transistors Tl, T2, T3, T4, as these devices may carry a lower share of current to a similar multi-level converter without such bypass paths. The presence of the bypass diodes Dl, D4 can also reduce voltage spikes across the inner transistors T2, T3, which may, for example, eliminate the need for snubbers or other protection circuitry. The first and third quadrant operational characteristics may be particularly advantageous in UPS systems, wherein such a converter structure may be used for the input rectifier and thus realize significant reduction in rectifier losses in comparison to conventional multilevel rectifier circuits.

[0023]For example, FIG. 7 illustrates a UPS system 700 including a power converter 710 including a rectifier circuit 712 along the lines described above connected to positive and negative DC busses DC+, DC-. The rectifier circuit 712 may be configured to be connected, for example, to an AC source, such as a utility source. Storage capacitors Cp, Cn are connected between respective ones of the DC buses DC+, DC- and a neutral N. The rectifier circuit 712 includes an NPC multi-level converter circuit including transistors Tl, T2, T3, T4 and diode D2, D3, along with bypass diodes Dl, D4, input inductor L and filter capacitor Cf. Although not shown, respective integral or discrete antiparallel diodes may also be connected across the inner transistors T2, T3 to prevent reverse conduction, as explained above with reference to FIG. 1. The power converter 710 further includes an inverter circuit 714 having a similar architecture, including a multi- level converter circuit including transistors ΤΓ, Τ2', Τ3', T4' and diodes D2', D3'. The inverter circuit 714 further includes bypass diodes Dl', D4', output inductor L and filter capacitor Cf. The inverter circuit 714 may be configured to be connected to an AC load.

[0024] A control circuit 720 drives the transistors Tl, T2, T3, T4, Tl', Τ2', Τ3', T4' of the rectifier 712 and the inverter 714 to control the DC voltages on the DC buses DC+, DC- produced by the rectifier 712 and the AC output voltage produced by the inverter 714. It will be appreciated that the rectifier 712 and inverter 714 may also be operated in other modes, e.g. , the rectifier 712 may operated in modes that support power backfeed, input short circuit protection, battery self test, harmonic compensation, etc., and the inverter 714 may be operated in modes that support reactive power compensation, harmonic compensation, etc. The UPS system 700 may also include other components, such as switches (e.g. , contactors) for controlling external coupling of the rectifier 712 and/or the inverter 714, a battery and/or battery converter connected to the DC buses DC+, DC- and/or a bypass switch for bypassing the rectifier 712 and the inverter 714. It will be further appreciated that, although FIG. 7 illustrates one phase, multiple such phases may be used in a multi-phase UPS system. For example, a three-phase UPS system may incorporate three rectifiers like the rectifier 712 and three inverters like the inverter 715 commonly connected to positive and negative DC buses and operated with appropriate transistor modulation to provide three-phase operation.

[0025] FIG. 8 illustrates an alternative power converter 810 for a UPS system according to further embodiments. The power converter 810 includes an inverter circuit 814 having an arrangement along the lines described above connected by DC buses DC+, DC- to a rectifier 812 including a conventional "T-type" NPC multi-level converter circuit. The multi-level converter of the rectifier 812 includes upper and lower transistors Tl, T4 that couple respective ones of the DC buses DC+, DC- to an input inductor L, diodes Dl, D4 connected in parallel with respective ones of the transistors Tl, T4, and a neutral clamping circuit including transistors T2, T3 and diodes D2, D3. The inverter 814 includes a multilevel converter including transistors ΤΓ, Τ2', Τ3', T4' and diodes D2', D3', along with bypass diodes Dl', D4', an output inductor L and a filter capacitor Cf. Although not shown, respective integral or discrete antiparallel diodes may also be connected across the inner transistors Τ2', T3' to prevent reverse conduction, as explained above with reference to FIG. 1.

[0026] FIG. 9 illustrates another converter 910 for a UPS system according to further embodiments. A rectifier 912 includes an NPC multi- level converter circuit including transistors Tl, T2, T3, T4 and diodes D2, D3. The rectifier 912 further includes bypass diodes Dl, D4, an input inductor L and a filter capacitor Cf. Although not shown, respective integral or discrete antiparallel diodes may also be connected across the inner transistors T2, T3 to prevent reverse conduction, as explained above with reference to FIG. 1. DC buses DC+, DC- connect the rectifier 912 to an inverter 914 including a conventional "I-type" NPC multi-level converter. The inverter 914 includes transistors ΤΓ, Τ2', Τ3', Τ4', diodes Dl', D2', D3', D4', D5', D6', an output inductor L and a filter capacitor Cf.

[0027] FIG. 10 illustrates a converter 1010 for a UPS system according to still further embodiments. A rectifier 1012 includes an NPC multi-level converter circuit including transistors Tl, T2, T3, T4, wherein the inner transistors T2, T2 are MOSFETs (e.g. , power MOSFETs, cool MOSFETs, silicon carbide (SiC) MOSFETs, gallium arsenide (GaN) MOSFETs, etc.) and the outer transistors Tl, T4 are IGBTs. The rectifier 1012 further includes diodes D2, D3, along with bypass diodes Dl, D4, an input inductor L and a filter capacitor Cf. DC buses DC+, DC- connect the rectifier 1012 to an NPC multi-level converter circuit 1014, which includes transistors ΤΓ, Τ2', Τ3', Τ4', where the inner transistors Τ2', T3' are IGBTs and the outer transistors ΤΓ, T4' are power MOSFETs. The inverter 1014 further includes diodes Dl', D2', D3', D4', D5', D6', an output inductor L and a filter capacitor Cf.

[0028] FIG. 11 illustrates a converter 1110 for a UPS system according to still further embodiments. A rectifier 1112 includes an NPC multi-level converter circuit including transistors Tl, T2, T3, T4. The rectifier 1112 further includes diodes D2, D3, along with bypass diodes Dl, D4, an input inductor L and a filter capacitor Cf. DC buses DC+, DC- connect the rectifier 1012 to a "T-type" multi-level inverter circuit 1114, which includes transistors ΤΓ, Τ2', Τ3', Τ4', diodes Dl', D2', D3', D4', D5', D6', an output inductor L and a filter capacitor Cf.

[0029] It will be appreciated that the descriptions of FIGs. 7-10 are provided for purposes of illustration, and that converter circuitry according to embodiments of the invention may be implemented in UPS systems in a variety of other ways. It will be further appreciated that converter apparatus according to further embodiments may be implemented in other electronic systems, such as in wind or solar power converters, power supplies, line conditioners, VAR compensators, welding equipment, battery chargers, motor drives and the like.

[0030] In the drawings and specification, there have been disclosed exemplary embodiments of the inventive subject matter. Although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the inventive subject matter being defined by the following claims.

Claims

WHICH IS CLAIMED:
1. An apparatus comprising:
a multi-level converter circuit configured to selectively couple first and second DC buses to a common node; and
respective first and second bypass circuits coupling the common node to respective ones of the first and second DC buses.
2. The apparatus of claim 1, wherein the first and second bypass circuits are configured to provide unidirectional conduction paths between the common node and respective ones of the first and second DC buses.
3. The apparatus of claim 1, wherein the multi-level converter circuit comprises: first and second pluralities of serially-connected switching devices connected between the common node and respective ones of the first and second DC buses and configured to selectively provide respective first and second switched conduction paths between the common node and a neutral node; and
a control circuit configured to control the first and second pluralities of serially- connected switching devices.
4. The apparatus of claim 3, wherein the control circuit is configured to modulate respective first switching devices from respective ones of the first and second pluralities of switching devices to operate the multi-level converter circuit as a multi-level converter while the first bypass circuit is conducting current between the first DC bus and the common node.
5. The apparatus of Claim 4, wherein the control circuit is configured to modulate the first switching devices to regulate a voltage of the first DC bus.
6. The apparatus of claim 4, wherein the control circuit is further configured to modulate respective second switching devices from respective ones of the first and second pluralities of switching devices while the second bypass circuit is conducting current between the second DC bus and the common node.
7. The apparatus of Claim 6, wherein the control circuit is configured to modulate the second switching devices to regulate a voltage of the second DC bus.
8. The apparatus of claim 1, wherein the first and second bypass circuits comprise respective diodes.
9. The apparatus of claim 1, wherein the multi- level converter circuit and the first and second bypass circuits are configured to support four quadrant operation, and wherein the first and second bypass circuits conduct current in a first two quadrants and block current in a second two quadrants.
10. The apparatus of claim 1, wherein the multi-level converter circuit comprises a neutral point clamped (NPC) converter circuit.
11. An apparatus comprising:
first and second diodes connected between respective first and second DC buses and a common node;
a first plurality of serially-connected transistors connected between the common node and the first DC bus;
a second plurality of serially-connected transistors connected between the common node and the second DC bus;
a third diode connected between a neutral node and a node of the first plurality of transistors;
a fourth diode connected between the neutral node and a node of the second plurality of transistors;
at least one inductor having a first terminal connected to the common node; and a control circuit configured to control the first and second pluralities of transistors.
12. The apparatus of claim 11, wherein the control circuit is configured to provide four quadrant operation, and wherein the first and second diodes are configured to conduct current in a first two quadrants and to block current in a second two quadrants.
13. The apparatus of claim 11, wherein the control circuit is configured to modulate respective first transistors of the first and second pluralities of transistors to regulate a voltage of the first DC bus when the first diode is conducting current between the first DC bus and the common node.
14. The apparatus of claim 13, wherein the control circuit is further configured to modulate respective second transistors of the first and second pluralities of transistors to regulate a voltage of the second DC bus when the second diode is conducting current between the second DC bus and the common node.
15. The apparatus of claim 11, wherein the first and second pluralities of transistors comprise IGBTs and/or MOSFETs.
16. An uninterruptible power supply (UPS) system comprising:
a first converter configured to be connected to an AC source:
a second converter configured to be connected to a load;
first and second DC buses coupling the first and second converters,
wherein at least one of the first and second converters comprises a multi-level converter circuit configured to selectively couple first and second DC buses to a common node and first and second bypass circuits coupling the common node to respective first and second ones of the DC busses.
17. The UPS system of Claim 16, wherein the at least one of the first and second converters comprises:
first and second diodes connected between respective ones of the first and second DC buses and the common node;
a first plurality of serially-connected transistors connected between the common node and the first DC bus;
a second plurality of serially-connected transistors connected between the common node and the second DC bus;
a third diode connected between a neutral node and a node of the first plurality of transistors;
a fourth diode connected between the neutral node and a node of the second plurality of transistors.
18. The UPS system of claim 16:
wherein the first converter comprises:
a first multi-level converter circuit configured to selectively couple the first and second DC buses and a neutral node to a first common node and first and second bypass circuits coupling the first common node to respective first and second ones of the DC busses; and
a first inductor connected between the first common node and the AC input; and
wherein the second converter comprises:
a second multi-level converter circuit configured to selectively couple the first and second DC buses and the neutral node to a second common node; and
a second inductor connected between the second common node and the AC output.
19. The UPS system of claim 16, wherein the at least one of the first and second converters is configured to operate as a rectifier.
20. The UPS of claim 16, wherein the multi-level converter circuit comprises a NPC converter circuit.
PCT/CN2012/085439 2012-11-28 2012-11-28 Multi-level converter apparatus with efficiency improving current bypass WO2014082221A1 (en)

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US20180076628A1 (en) * 2012-05-10 2018-03-15 Futurewei Technologies, Inc. Multilevel Inverter Device and Method
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