DE19523031A1 - System for transmitting data over a differential bus - Google Patents

Abstract

The invention concerns a system for transmitting data via a differential bus by means of duplex signals. This system is not only interference-free but also has the advantage that when various simple errors occur, i.e. errors which affect only one of the two lines or with which both differential bus lines short circuit, data can still be transmitted, although with reduced reliability. To this end, both lines lead to a plurality of comparators having various threshold values, whereby the type of error which has occurred can be established and it can then be determined according thereto from which comparator output the recovered data signal has to be derived.

Description

The invention relates to a system for transmitting binary data between one Number of stations that have a common first and a common second Line are interconnected, with a logical value of the binary The first line is low and the second line is high Level and at the other logical value of the binary data the first line high level and the second line has a low level and the logic value of the binary data for output at a data output of the level at least a line is derived.

The lines used in such systems to transmit data are often referred to as differential bus because the logical value of the transmitted binary data by the difference between the levels on the two Lines is shown taking into account the sign of the difference. Such a differential bus has the advantage of being interspersed from outside electromagnetic interference levels in essentially on both lines influence in the same way so that the difference in levels is almost unchanged remains. This results in a very interference-free data transmission. Come in addition, that those emitted by the two lines when level changes Essentially compensate for electromagnetic interference.

Multi-station systems connected by a differential bus, are often used in an environment where the two lines in particular also exposed to mechanical loads, so that it too Damage to these lines can occur. An example of this is use of such a system in motor vehicles. Add to that the two  Pipes also at least partially in close proximity to metallic parts that are grounded.

The object of the invention is therefore to provide a system of the type mentioned to specify, in which at least one of the data transmission is still possible for both heads, albeit with reduced interference immunity.

This object is achieved in that in each station at least one first comparator is provided, which has two lines is coupled to the level on the first line from the level on the second Subtract line and an output signal with a first value at one to deliver the first comparator output if the one formed by the subtraction Difference exceeds a first threshold, said first threshold is selected so that the output signal at the first comparator is also its Value changes if a level change occurs on only one of the two lines and the other line has a level corresponding to the one logic value of the binary Has data.

By using a comparator that not only shows the difference in level forms two lines, but this difference also with a certain first If the threshold value is compared, the one transmitted at the output of this comparator Data signal reproduced even if one of the two lines is interrupted is. Since each line is known to have such a low resistance via a resistor or high level is connected, that the level on the line is logical Correspond to the value of the binary data if there is no signal from any station on the Lines are fed, and these resistors preferably at each station are arranged, an interrupted line has a largely defined level, so the uninterrupted line continues for the transmission of data is usable. The measures according to the invention therefore result in a  Interruption of only one line does not yet result in a data transmission disturbance. Also a connection between the first line and an earthed metal part, d. H. Ground short of the first line, does not lead to a fault in the Data transmission.

The errors described, in particular an interruption of one of the two Lines, can be considered the most likely errors. There are however, further errors are possible, in particular the second line can also get in contact with a grounded metal part or both lines can be one To have a short circuit between them. In order to get one even in such an error case To enable data transmission in principle is a configuration of the Invention characterized in that a second comparator is provided which is coupled to the first line to provide an output signal having the first value generate a second comparator output when the level is at the first Line is above a second threshold, and that a first memory is provided, which has a first delay element with a first Delay time is coupled to the first comparator output and from which one Output is coupled with a switch to the data output from the first Comparator output to switch to the second comparator output if during the output signal on a time period corresponding to the first delay time first comparator output always has the first value.

With these errors, however, it is not possible to transfer data even in the To perform the moment of the occurrence of the error undisturbed, but it is a a certain amount of time is necessary to carry out the required switchover. A transmission of data signals without a simultaneous transmission of a Clock signal must namely be done in such a way that the clock signal from the Data signal can be taken or is given at all stations. Therefor a number of different encodings are known (e.g. NRZ modulation) where the failure of a normal data signal is recognized after just a few cycles  can be. In this case, the first delay time can be chosen short, so that switching can be done quickly. With other encodings in contrast, the logical value of the data signals is formed by a continuous signal, so that consecutive data with the same logical value a constant signal without Form signal transitions while the signal transitions are only for synchronization a clock generator can be used on the receiver side. Through special Coding measures are taken to ensure that the number is consecutive Data with the same logical value does not exceed a maximum number. In In this case, the first delay time must be chosen longer than the duration the maximum number of consecutive identical data with the lowest Transmission frequency. If one of the latter two errors occurs immediately after a signal transition or a level transition on the two lines done, the subsequent transmitted data is for the duration of the first Delay time practically lost. However, this can be done in most cases compensate for the fact that a data block, when it is transmitted, causes the interference occurred, is transmitted repeatedly, for example because the recipient of the correct receipt of the data block has not been confirmed.

It is desirable that a bug be fixed during a data transfer if possible does not lead to a malfunction. The error can disappear occur, for example, in that a connection within one of the lines has poor contact or that there is a short to ground or connection between both lines due to mechanical shocks disappears. With the first three errors mentioned, the error disappears as well as its occurrence practically without influence on the data transmission itself, only the interference immunity is restored after the error has disappeared cheaper. With the latter two errors, the disappearance of the Error that the memory is switched back again. However, to prevent the memory from being erroneously caused by short interference signals on the lines switches back, it is expedient that the first memory further via a second  Delay element with a second delay time with the first Comparator output is coupled such that the first memory is the changeover switch switches so that the data output from the second comparator output to the first comparator output is switched back if during a period of time corresponding to the second delay time, the output signal on the first Comparator output does not have the first value.

In this way, the first memory is reliably prevented from being erroneously transmitted the interference signals are already switched back to normal.

In many cases, not all stations or are in the system mentioned at the beginning none of the stations equipped with its own power supply, but it is parallel to the two lines for data transmission at least one led further line that carries a supply voltage, of which in each Station a lower operating voltage for operating an electrical circuit in the station for driving the first and second lines is derived. In this If it is possible, the first or the second line may be connected due to an error the third line comes into contact and the level on the corresponding line becomes equal to the supply voltage. To even in such cases To be able to carry out data transmission over the still undisturbed line is one Another embodiment of the invention, characterized in that a third, a fourth and fifth comparators are provided, of which the third Comparator coupled to the second line to provide an output signal to the generate first value at a third comparator output when the level is up the second line is above a third threshold, the fourth Comparator with the first line and the fifth comparator with the second Line is coupled and each of these two comparators with an output signal generates a first value at a fourth or fifth comparator output if the level on the line coupled to the comparator in question fourth threshold exceeds that between the operating voltage and the  Supply voltage is that a second and a third memory is provided are, each of which has a first and a second input and an output has, wherein the first input of the second memory with the first Comparator output, the second input of the second memory with the fourth Comparator output, the first input of the third memory with the fifth Comparator output and the second input of the third memory via a third Delay element with a third delay time with the fifth Comparator output are coupled and that the output of the second memory with the switch is coupled to the third comparator output with the Data output to couple, and the output of the third memory with the Switch is coupled to the second comparator output with the To couple data output.

The fourth or fifth comparator can immediately determine if one of the two lines short-circuits with the higher operating voltage Has. With the first line, such a short circuit acts as if this line constantly at least one level corresponding to the second logical value of a binary data signal would have, so that the first comparator constantly an output signal with the first value. In this case, therefore, the data output is included coupled to the third comparator output, which carries the signal on the second line evaluates which is assumed to be functional. If, on the other hand, the second Line is short-circuited with the supply voltage, however, is the difference between this level and the level on the undamaged first line like this negative that the threshold value of the first comparator is never exceeded and the signal at the first comparator output never takes the first value. Therefore in this case the data output with the second comparator output coupled, the level on the first line assumed not to be damaged evaluates. Here, too, it is advisable to use the inputs of the memory To couple delay elements to the corresponding comparator outputs Prevent malfunctions with short interference signals.  

It is generally not sufficient if, despite a mistake on either one Lines of the differential bus, data transmission is still possible, but such a mistake should also go beyond one Error display output are reported so that the error can be remedied. Except for the first three errors, the remaining errors become memory unswitched, whose output signals are used for an error display can. For the first three errors, however, there is an additional error detection necessary. This is a further embodiment of the invention characterized in that a first and a second counter are provided, of which each has a counter input, a reset input and a counter output, where the count input of both counters with the first comparator output, the Reset input of the first counter with the second comparator output, the Reset input of the second counter with the third comparator output and the Counter output of both counters and the output of the memory elements with the Fault indicator output are coupled. So the counters each count a number Signal transitions of the first comparator output, and in the case of errors belongs to each such signal transition also a corresponding signal transition on the second and at the third comparator output, so that the counters do not have their Can count out the starting position. However, if one of the two lines is disturbed, the corresponding second or third comparator output is missing Signal transitions, and thus the counter concerned may have a fault status achieve, in which an error signal is generated.

Embodiments of the invention are explained in more detail with reference to the drawing. Show it:

Fig. 1 shows schematically a system with multiple stations and their Leitungsverbindugen,

Fig. 2 is a block diagram of the important parts of a station,

Fig. 3 is a block diagram of one of two error detection circuits,

Fig. 4 is a block diagram of another error detection circuit,

Fig. 5, the control of the data output and the terminating resistors,

Fig. 6 shows the circuit of a station for a standby state,

Fig. 7 shows a further error detection circuit for the standby state.

In Fig. 1, three stations 1 , 2 and 3 are shown schematically, which are connected to one another via three lines 10 , 11 and 12 . The line 10 is connected to a higher supply voltage, from which the individual stations derive the operating voltage for the electronic circuit contained therein. Lines 11 and 12 form the differential bus over which the data are transmitted.

At station 2 further details are shown, which are omitted for the sake of clarity at stations 1 and 3 . The line 11 is connected to ground via a resistor 14 and a switch. Correspondingly, line 12 is connected via a resistor 15 and a further switch to the operating voltage Vc, which is derived in the station from the supply voltage on line 13 . The function of the two switches will be explained later. Furthermore, a control arrangement 5 is provided in station 2 , which controls two switches 6 and 7 together, switch 6 connecting line 11 to the operating voltage Vc and switch 7 connecting line 12 to ground. When switches 6 and 7 are open, line 11 is at a low level via resistor 14 and line 12 is at operating voltage Vc via resistor 15 . This corresponds to the one logical value of the binary data signals to be transmitted. If the other logic value is to be transmitted, both switches 6 and 7 are closed by control unit 5 , so that line 11 is now at a high level and line 12 is at a low level. In this way, data can be transmitted via lines 11 and 12 from each of stations 1 to 3 . The state or level on the lines 11 and 12 with open switches 6 and 7 is therefore referred to below as recessive and the state with closed switches 6 and 7 is referred to as dominant.

The circuit for evaluating the data transmitted via lines 11 and 12 in a station is shown in FIG. 2. The two lines 11 and 12 lead to a first comparator 21 , which forms the difference between the levels on lines 11 and 12 , more precisely, subtracts the level on line 12 from line 11 , and which compares the correct sign with a first Compares threshold. This threshold value is chosen such that a low output signal is generated on line 31 only in the recessive state of both lines 11 and 12 . The line 31 is connected to a multiplexer 29 which connects the line 31 to the data output 40 in the event of an error and in the event of certain errors. Furthermore, the line 31 leads to two error detection circuits 26 and 27 , which will be explained later.

The line 11 also leads to a comparator 22 which compares the level on this line with a threshold value which lies between the dominant and the recessive level on the line 11 , taking tolerances into account. Comparator 22 produces a high signal on line 32 when the level on line 11 is above the threshold. This line 32 leads to the error detection circuit 26 and to the circuit 29 which connects this line to the data output 40 in the event of certain errors.

Line 11 also leads to a further comparator 24 , which compares the level on this line with a voltage between the operating voltage of the circuit and the higher supply voltage on line 13 in FIG. 1 and generates a signal on line 34 when the level is up the line 11 is higher than the operating voltage. This line 34 leads to the lower error detection circuit 27 .

Correspondingly, line 12 also leads to a comparator 23 , which compares the level on this line with a threshold value, which is also between the dominant and recessive level. Comparator 23 produces a high signal on line 33 when the level on line 12 is below the threshold. The line 33 is connected to the upper error detection circuit 26 and to the circuit 29 which, in the event of a specific error, as explained later, connects this line to the data output.

Furthermore, line 12 leads to a comparator 25 , which compares the level on this line with a threshold value between the operating voltage and the higher supply voltage, in the same way as is done with comparator 24 with the level on line 11 . The output line of the comparator 25 is also connected to the lower error detection circuit 27 .

The upper error detection circuit 26 generates an error signal on an output line 36 a when the line 11 is interrupted or has a short circuit to ground. B on line 36, an error signal is generated when the line is interrupted 12th

The lower fault detection circuit 27 generates a signal on an output line 37 if the two lines 11 and 12 have a short circuit with one another or if the line 12 has a short circuit to ground. An error signal is generated on line 38 when line 11 is shorted to the supply voltage and an error signal is generated on line 39 when line 12 is shorted to the supply voltage.

All error signals on lines 36 a, 36 b and 37 to 39 are combined via a logic element 30 and output at an error display output 41 .

The lines 37 to 39 also lead to a priority circuit 28 , since in the event of certain faults more than one line carries a high signal, but clear control signals are required for the circuit 29 . Line 38 has the highest priority, line 39 the second highest and line 37 the lowest priority. The structure of such a priority circuit 28 is generally known. The signals on lines 37 to 39 are specified according to their priority on lines 37 a to 39 a.

In circuit 29 there are also switches, as indicated in FIG. 1 in station 2 , which connect the resistor 14 connected to line 11 to ground and the resistor 15 connected to line 12 to the operating voltage Vc.

In Fig. 3, the structure of the error detection circuit 26 in Fig. 2 is shown in more detail. There are two counters 51 and 54 , two differentiating circuits 52 and 55 and two counter memories 53 and 56 . The counter inputs of counters 51 and 54 are connected together to line 31 . The input of differentiator 52 is connected to line 32 , and differentiator 52 outputs a short output signal when there is a signal edge on line 32 due to the transition of the signal on line 11 , and the signal of differentiator 52 sets counter 51 to an initial position and also sets the counter memory 53 to its rest position. The differentiating circuit 55 receives the signal from line 33 and also generates a short output signal from the signal transition on line 33 at the transition of line 12 , which sets the counter 54 to an initial position and the counter memory 56 to the rest position.

If line 11 or 12 is interrupted, signal transitions occur on line 31 , which are counted by both counters 51 and 54 , but depending on the interrupted line, no corresponding signal transition occurs on line 32 or 33 , so that the associated one Counter 51 or 54 is not reset, but reaches a counting position in which the counter memory 53 or 56 is set. An error signal is thus generated on the corresponding line 36 a or 36 b. Instead of using the counter memories 53 and 56 , the further counting of the counters can also be blocked when they have reached the corresponding counter position. If the error disappears or is eliminated, a set counter memory or a blocked counter is automatically reset because signal edges then occur again on both lines 32 and 33 .

The structure of the error detection circuit 27 in FIG. 2 is shown in more detail in FIG. 4. This contains three memories 61 , 62 and 63 , each of which is constructed from two cross-coupled NOR gates, the further inputs of the NOR gates forming the inputs of the memory. For clarity, this structure is only shown for the memory 61 . Other so-called R-S flip-flops can also be used.

The upper input of the memory 61 is connected to the line 31 via a first delay element 64 and an inverter 65 . As soon as line 31 carries a high signal for a continuous period of time which is greater than the delay time of the first delay element, the output of delay element 64 goes high and a high signal is generated on output line 37 . This continuous high signal on line 31 occurs when one of the two lines has a dominant state due to an error. The delay time of the delay element 64 must therefore be greater than the period of time that a maximum number of transmitted data with the same value can have.

If such an error is eliminated and the signal on line 31 occurs in a recessive state on both lines 11 and 12 , an inverter 65 and a further delay element 66 , which is connected to the lower input of the memory 61 , reset it and brought the signal on line 37 low. The delay element 66 is intended to prevent the memory 61 from being erroneously reset by short-term interference signals in the event of an error.

One input of the memory 62 is connected to the line 34 via a delay element 67 and the other input is connected to the delay element 66 . Both delay elements preferably have approximately the same delay time. As soon as line 11 has a short circuit to the supply voltage, a high signal appears on line 34 , and if this signal is present longer than the delay time of delay element 67 , memory 62 is set and a high signal is generated on line 38 . This state is, moreover, the dominant state for line 11 , and while this exists, no signal transitions are generated on line 31 , so that memory 62 remains set. Only when the error has been eliminated and signals appear again on line 31 is the memory 62 reset, so that the signal on line 38 then becomes low again. Instead, the memory 62 can also be reset from the signal on line 34 via an inverter (not shown).

One input of the memory 63 is connected via a delay element 68 to the line 35 , which carries a high signal when the line 12 has a short circuit with the supply voltage. If this short circuit lasts longer than the delay time of the delay element 68 , which is expediently chosen to be approximately equal to the delay time of the delay elements 67 and 66 , the memory 3 is set and a high signal appears on line 39 .

The other input of the memory 63 is connected to the line 35 via a further delay element 69 and an inverter 60 . The delay time of delay element 69 is considerably longer and depends on conditions during a standby state of the entire system, which will be explained later. In this standby state, a level above the operating voltage on line 12 also occurs without a fault, so that the memory 63 is always set in the standby state. In this state, however, no data transmission takes place and an error signal is not evaluated either.

The structure of the circuit 29 in FIG. 2 is shown in more detail in FIG. 5. The line 37 a, which carries a signal when the line 12 has a short circuit to ground or to the line 11 , as described earlier, leads to an input of an OR gate 71 and an OR gate 72 . The output signal of the OR gate 72 on line 79 opens switch 73 and thus interrupts the connection from line 31 to data output 40 , so that the signal at data output 40 is no longer derived from comparator 21 in FIG. 2. The OR gate 71 generates a signal on the line 78 which closes the switch 74 , so that the line 32 is now connected to the data output 40 and the signal at the data output is thus derived from the comparator 22 in FIG. 2. In addition, the signal on line 78 opens a switch 77 , which connects line 12 via resistor 15 to the operating voltage Vc. This prevents that if the line 12 has a short circuit to ground, a current from the operating voltage flows continuously through the resistor 15 , or if the line 12 has a short circuit with the line 11 , the recessive level on both lines is raised too much becomes. All that remains is a connection from line 12 via resistor 15 and a very high-resistance resistor 17 to operating voltage Vc, in order to ensure that line 12 does not assume an undefined level after the error has ended.

The line 38 a, which carries a signal when the line 11 has a short circuit with the higher supply voltage, also leads to an input of the OR gate 72 , so that the connection between the line 31 and the data output 40 is also interrupted in this case becomes. In addition, the signal on line 38 a controls a switch 75 , which now connects line 33 to data output 40 , and furthermore a switch 76 is opened so that line 11 is no longer connected to ground via resistor 14 and thus an unnecessary current through the resistor 14 is avoided. Line 11 is only connected to ground via the series connection of resistor 14 and a very high-resistance resistor 16 , for the same reasons as described for line 12 and the series connection of resistors 15 and 17 .

The line 39 a, which carries a signal when the line 12 has a short circuit with the higher supply voltage, is connected to an input of the OR gates 71 and 72 , in the same way as the line 37 a, ie the switches 73 and 77 are opened and the switch 74 is closed and thus the line 32 is connected to the data output 40 .

It should be noted that the states on lines 11 and 12 are determined not only by the resistors 14 and 15 of this station, but by the corresponding resistances of the other stations.

Sometimes a system of the type described is used in an environment where the source that supplies the higher supply voltage is only a limited one Contains energy. This is particularly the case if the system described is in one Motor vehicle is used. Therefore, in addition to the normal transmission mode also a standby state is provided in which a correct receipt of data and sending of data is not possible, but the data transmitted by other stations if certain criteria are met understood as a request to switch to normal transmission mode can be. This change is also known as waking up. A station can, for example, if no data during a predetermined period of time have been transferred to an operating state with very low Power consumption, namely the standby state, but over the  Transmission lines controlled back to normal at any time Transmission status can be reset. The current consumption in The state of readiness should be as low as possible since the total energy consumption increases proportionally with the number of stations in a system.

However, the requirement for the lowest possible current consumption in the standby state conflicts with the fact that in each station the operating voltage for the electronic circuit is derived from the higher supply voltage, in the case of a motor vehicle, from the battery, because a voltage stabilization circuit required for this and the further circuit in FIG Each station has a minimum current that is greater than the desired current in the standby state. Therefore, in the standby state, the voltage stabilization circuit is switched off completely, so that there is no longer any operating voltage. Thus, the line 12 is no longer brought to the recessive high level via the resistor 15 in each station in the standby state. Although this would not lead to disturbances in the other switched-off stations, it would then no longer be possible for a station which has been brought into the normal transmission state, for example by a local condition, such as a switch, to control all lines of the bus by all other stations. The condition that both lines have to be activated to wake up the other stations is based on the fact that in the event of a fault in one line, all other stations should still be woken up.

A circuit which enables proper functioning even under these conditions is shown in FIG. 6. This shows a station that receives a supply voltage via line 13 . A control unit 81 is provided in the station, which not only carries out the transmission and reception of data via lines 11 and 12 , but also the setting to the ready state or the transmission state. The line 13 leads to a voltage regulating circuit 82 , which derives from it a stabilized operating voltage Vc, which is fed to the control unit 81 . The voltage regulating circuit 82 can also be switched off via the line 85 in order to put the station into the ready state, in which case the operating voltage Vc practically disappears. Since the processing of a data transmission via lines 11 and 12 must be effective in the standby state, line 13 is also fed directly to control unit 81 for this part of the circuit which requires very little current.

So that the start of data transmission for a woken-up station can begin in the ready state of all stations, care must be taken to ensure that a recessive high level is present on line 12 even in the ready state. This is no longer possible via the resistor 15 , since the voltage Vc is absent in the standby state. For this purpose, the line 13 with the higher supply voltage is led via a resistor 84 to a switch 83 , which switches the two resistors 84 and 15 in series from the control unit 81 in the ready state and thus on line 12 a level with approximately the supply voltage on the line 13 generated. Although this voltage is higher than in the normal transmission state, data transmission is not provided in the standby state. The memory 3 in FIG. 4 is not set in the standby state because the operating voltage is missing.

A station, which is woken up by a local condition and now starts a transmission, first switches the switch 83 over again, so that the line 12 in this station is connected via the resistor 15 to the operating voltage Vc which is then also switched on. However, since in the other stations the line 12 is still connected to the higher supply voltage via the resistor 84 , a higher level is initially set on the line 12 than in the normal transmission state, as a result of which the memory 3 in FIG. 4 is set. However, as soon as line 1 has been at the level corresponding to the normal transmission state for a sufficient length of time, this time corresponding to the delay time of delay elements 69 in the individual stations, all memories 3 are finally switched back again. Since normal data transmission is possible even when the memory 3 is set, there are no disturbances.

However, errors can occur or are present on lines 11 and 12 during the standby state of all stations, but these must not lead to increased current consumption. To prevent this, an error detection circuit that is effective during the standby state is provided, which is shown in FIG. 7. In this line 11 leads to two comparators 91 and 92 which compare the level on line 11 with different threshold values. The comparator 91 checks whether the level on line 11 rises above a value which is slightly below the supply voltage on line 13 . This is the case if the line 11 has a short circuit with the supply voltage. The signal generated in this case on line 101 is fed via a delay element 95 to an input of an AND gate 96 . Its output leads to the switch 76 in FIG. 5 and separates the resistor 14 from ground, so that in this fault case no current can flow from the supply voltage via the resistor 14 or the resistors 14 in all stations, since all stations have the same fault determine and separate the resistor 14 from ground.

In the recessive state, line 12 has high potential, as previously described. However, if this line has a short to ground, a current from the supply voltage would flow through resistor 15 to ground in each station via resistor 15 . The comparator 93 now compares the level on the line 12 with a threshold value between the dominant and the recessive level and emits a signal if the level falls below this level. This signal leads via the OR gate 97 and a delay element 98 to the switch 77 in FIG. 5, so that the resistor 15 is no longer connected to the resistor 84 in FIG. 6 and therefore no current flows from the supply voltage to ground can.

If the two lines 11 and 12 have a short circuit with one another, they have a common level which, depending on how many stations have already reacted to this error, can lie between ground and a voltage below the supply voltage. To determine this, the comparator 92 is provided, which compares the level on the line 11 with a threshold value which is also between the dominant and the recessive level, but is smaller than the threshold value of the comparator 93 . It is thereby achieved that in the event of a short circuit between the two lines 11 and 12, at least one of the two comparators 92 or 93 emits a signal. The signal from comparator 92 is supplied to an AND gate 94 , from which a lock input is connected to the output of comparator 91 , since comparator 92 also provides an output signal when line 11 is shorted to the supply voltage, then the output signal of the comparator 92 should not be effective. If only the lines 11 and 12 are shorted to one another, the AND gate 94 is enabled and the output signals of both comparators 92 and 93 are combined in the OR gate and lead via the delay element 98 to the switch 77 in FIG the output of delay 98 also to a lock input of AND gate 96 to prevent both resistors 14 and 15 from being turned off. However, this case can only occur in the case of a multiple error, so that this connection to the AND gate 96 and this itself can also be omitted.

The function of the circuits described so far is explained below. Mean in it

CAN-H: line 11
CAN-L: line 12
Comparator D: Comparator 21
Comparator H: Comparator 22
Comparator L: Comparator 23
Comparator BH: Comparator 24
Comparator BL: Comparator 25
Comparator WS: Comparator 91
Comparator WH: Comparator 92
0 Comparator WL: Comparator 93
RxD: data output 40
Vcc: regulated operating voltage Vc
Vbat; Supply voltage on line 13 .

Requirement

In a CAN communication system with the differential transmission lines CAN_L and CAN_H, the error states
1 interrupted CAN_H line
2 interrupted CAN_L line
3 Short circuit CAN_H after Vbat
4 Short circuit CAN_L to ground
5 Short circuit CAN_H to ground
6 Short circuit CAN_L after Vbat and
7 Short circuit CAN_H after CAN_L
recognized and tolerated or recognized and circumvented. Errors 1 and 2 must not lead to an error in the received data stream when they are received or canceled (tolerance). With errors 3 to 7 , data errors are allowed while the line error is received. Increased currents and the associated higher temperatures should be avoided.

The system has a standby mode in which communication is not possible, but the current consumption of transmission units is very reduced and the errors must not lead to increased quiescent currents. In this mode the CAN_L line is at Vbat potential. This may result in other error situations. The errors that can lead to increased currents and must therefore be recognized and avoided are errors 3 , 4 and 7 for this mode.

Physical layer

The CAN physical layer knows two states:

Recessive, no driver stage is activated
→ CAN_L potential = Vcc leakage (4.5 ... 5.25 V), in normal mode
→ CAN_L potential = Vbat leakage (6... 27 V), in standby mode
→ CAN_H potential = mass + leakage (0 ... 0.25 V)
Dominant, the driver level of at least one transmission unit in the system is activated
→ CAN_L potential = ground + transmitter drop voltage (max.1.4 V; typ. 1 V)
→ CAN_H potential = Vcc - transmitter drop voltage (min. 3.35 V; typ. 4 V).

The transmission rate is a maximum of 125 kbit / s (minimum bit duration = 8 us). The Terminie The bus lines are distributed across all transmission units in the system. The replacement resistance of all terminations gives approximately the line impedance. A maximum mass offset of 1.5 V should be tolerated.

Problems with error detection

Line levels in the fault state cannot be distinguished from levels in normal communication. For example, in the case of error 5 , CAN-H is equally at ground as in the normal recessive state; with error 4 , CAN_L is pulled to ground as well as in the dominant state. The large mass offset that can be tolerated exacerbates the problem of the lack of differentiation. Only errors 3 and 6 lead to line levels that are distinguishable from those during normal communication.

The errors generally lead to the data stream at the receiver being falsified becomes. This also affects the transmitting station during its transmission process and breaks this one. No further level changes are available for an analysis of the error situation added, only when a station is sent again do level changes occur, the one Analysis can serve. Each new, unsuccessful attempt to send results in the sending Depending on the protocol, transmission units become "penalty points" that sooner or later become passive Behavior of the station. Some errors result in no further attempts to send collecting penalty points. The static error of the bus line must therefore be as possible be circumvented quickly.

Some errors cannot be distinguished from one another, but require different actions with regard to their tolerance. For example, the beginning of a frame is transmitted with existing error 1 , both lines are initially recessive and the CAN_L line is then dominant; it can then only be transmitted on the intact CAN_L line. If, on the other hand, error 4 occurs while both lines are recessive, the CAN_L line also changes to the dominant state here, however, further communication must take place on CAN_H. The two errors must therefore be distinguishable, but are not easily distinguishable.

The error analysis is to be implemented on the transceiver chip. There is no information mation over the duration of a bit.

Description of the error analysis

Three comparators are used for reception. The differential threshold voltage of the Comparator D is set (recessive <-2.8 V (dominant) so that both the dominant State of one of the two lines alone and both lines together into one dominant level at the output leads. Comparator H evaluates the state of the CAN_H line off (absolute threshold voltage, recessive <1.8 V <dominant), comparator L the state of the CAN_L line (recessive <3.0 V <dominant).

In the error-free state, comparator D is received. The differential reception favors the conditions of mass offset and EMC currents (the design is a big one Common-mode range taken into account).

Detection of errors 1 , 2 and 5

Errors 1 , 2 , and 5 are tolerated by the appropriate selection of the threshold voltage at comparator D without further measures. This is important because even with static errors, the error may appear as a repetitive error. This results from the different position of a transmitter compared to the fault location.

In order to be able to report the error via the status flag, it must nevertheless be recognized. This is done by comparing the signals received by comparators H and L. the differentially received. For this, edges on comparators H and L are counted, one Edge on comparator D always resets the counter immediately. So meet at H or L seven If there are edges in a row and no edge on D in the same time, an error is detected. Of the The error is only deemed to have been eliminated when a flank arrives at D again.  

Detection error 3

In the event of error 3 , the CAN_H line has the potential of the battery voltage (min. 8 V; typ. 12... 14 V). This level can be clearly distinguished from levels in normal communication by means of a comparator BH (7.3 V to ground). The error state is kept in a memory element. Since the threshold voltage can also be reached under certain circumstances through the basically tolerated EMC interference, incorrect diagnosis of errors by an additional filter (T2 = 10 ... 60 us) in front of the memory element is excluded.

The elimination of the error is determined by reaching the recessive level at comparator D. posed. This event must also last at least T2 for a reset of the memory. Alternatively, the suspension of the Errors are recognized. However, the implemented solution results in a better system ver hold for errors that lead to voltages between Vcc and the threshold voltage.

Detection error 6

In the event of error 6 , the CAN_L line has the potential of the battery voltage. This is recognized by the comparator BL (7.3 V against ground). If the threshold for at least T2 is exceeded, a further memory element is set, if the threshold is undershot for at least T3 = 150. . . 1000 us reset (T3 is therefore chosen larger than T2 to avoid frequent switching of the memory element by transmission during a switchover of the CAN_L line from standby to normal operation).

Detection errors 4 and 7

Errors 4 and 7 lead to a permanent dominant state at D. This is delimited by the time condition T1 from dominant states during normal transmission and is stored in a further memory element. T1 is defined from the number of dominant bits that can be sent in succession with the CAN protocol and from the expected bit rates (725 ... 4000 us).

The cancellation is recognized by a recessive level at D at least T2 long and that Memory element reset.

Description of the workaround

In the event of a fault, the remaining intact line is used for further communication. as far as possible. To do this, the signals D, H and L are correspondingly applied to the RxD Output of the circuit switched. In addition, to avoid increased current the corresponding bias resistors are switched off as long as there is an error remains.

The faults are recognized independently of one another by the circuit described. Everything However, some errors mean that when the error arrives or after all Time conditions in the steady state diagnosed several errors at the same time will. The corresponding correct actions son dated. The priority order is: P3 <P6 <P47. The priority circuit makes exactly one of the possible error or no error diagnosed.  

Workaround for error 3

If error 3 is detected, the receive channel RxD is switched to comparator L and the bias series resistor of CAN_H is switched off to ground. However, a high-resistance resistor remains connected to ground. If the error is removed, the line returns to ground potential. Comparator output D is recessive and the removal of the error is recognized and the original state is restored.

Workaround for error 6

If error 6 is detected, RxD is switched to comparator H and the bias series resistor from CAN_L to Vcc is switched off. If the error is removed, the line floats but is brought back to a potential below Vcc by the input networks. The removal of the error is recognized and the original state is restored.

Workaround for Error 7

If error 7 occurs , the transmission lines are short-circuited. Further communication is continued on CAN_H. For this purpose, RxD is switched to comparator H, the bias resistance from CAN_L to Vcc is switched off and the transmission stage for the CAN_L line is deactivated. The CAN_L line remains connected to Vcc via a high-resistance resistor, but is forced to its potential via the short circuit with the CAN_H line. When the error is raised, the CAN_L line assumes Vcc potential, the recessive state at comparator D is reached again and the removal of the error is recognized. The original state is restored.

Workaround for error 4

Error 4 is treated the same as error 7 . A distinction would require further analytical means.

When error 4 occurs , RxD is switched to H, the bias series resistor from CAN_L to Vcc is switched off and the transmission stage for the CAN_L line is deactivated. The CAN_L line remains connected via a high resistance to Vcc. If the error is removed, the CAN_L line returns to the recessive level via the high-resistance resistor. The cancellation is recognized by the recessive level at D and the original state is restored.

Description of the fault analysis in the standby state

Communication is not possible in standby mode. The system is in one State of low power consumption, but in that of other transmission units Data sent in normal mode as a request to switch to normal Communication mode can be understood.

Errors 1 , 2 , 5 and 6 do not result in increased current consumption in this mode. Errors 3 , 4 and 7 must be recognized and increased current consumption avoided.

When detecting error 7, it must be taken into account that the area of Vbat voltage 8. . . Can be 27 V. The range of the equivalent resistance of all terminating resistors distributed in the system ranges from approx. 100 depending on the number of transmission units in the system. . . 200 ohms for CAN_H to ground and from 150. . . 5000 Ohm for CAN_L according to Vbat. As a result, in the event of a short circuit between the transmission lines, voltages of approx. 0.3. . . 8 V can be reached.

Description of the analysis

Three further comparators are used for the analysis. Comparator WS is on CAN_H connected and has a threshold value of approx. Vbat - 2 V. Comparator WH provides with a Threshold of approx. 2 V the dominant state at CAN_H fixed; Comparator WL with one Threshold of approx. 3 V the dominant state at CAN_L.

Error 3 is recognized directly when the threshold at WS is exceeded. This fact is additionally qualified by a timer. The resistance from CAN_H to ground is switched off.

Error 4 leads to the WL falling below the threshold. This fact is also qualified by a timer and leads to the switching off of the resistance from CAN_L to Vbat.

Error 7 leads to voltages between 0.3 V and 8 V on both lines CAN_H and CAN_L. In any case, at least one of the comparators WH and WL becomes dominant. The two comparator outputs are logically ORed and, in the case of a dominant state, error 7 is accepted. This fact is qualified by a timer and the resistance from CAN_L to Vbat is switched off. As a result of the switching off of all resistors from CAN_L to Vbat distributed in the system, the lines CAN_H and CAN_L short-circuited by error 7 increasingly assume mass potential1. The "overlapping" threshold voltages at WL and WH ensure that at least one of the comparators remains dominant when passing through the voltage range. With static error 7 , comparator WL remains dominant.

If error 7 is removed, the CAN_H line remains at ground, the CAN_L line floats and, if necessary, will reach a potential above the threshold voltage at WL, whereby the resistor is switched on again after Vbat. As a result, CAN_L is back on Vbat and the removal of the error is also reliably recognized in other transmission units.

Two additional locks

Error 7 may only make comparator WH dominant, but not WL. The same situation applies to error 3 . In order to differentiate errors 3 and 7 from each other - they require different error treatments - a detection of error 7 is locked by means of comparator WH with the signal from comparator WS. Optionally, the qualified signal from comparator WS can also be used.

To rule out that both terminations are switched off at the same time, a Locking of the shutdown signal for the resistor CAN_H to ground by the shutdown signal for the resistor CAN_L according to Vbat (optional).  

Note

The comparators WH and WL are in standby mode for data reception (Requirement to transition to normal communication mode) needed them anyway recognize the dominant state separately on the two transmission lines. For the Error handling in standby mode only requires another comparator.

Claims (5)

1. System for the transmission of binary data between a number of stations which are connected to one another via a common first and a common second line, wherein the logical line of the binary data, the first line a low level and the second line a high level and other logic value of the binary data, the first line is at a high level and the second line is at a low level and the logic value of the binary data for output at a data output is derived from the level of at least one line, characterized in that at least one in each station a first comparator is provided, which is coupled to both lines in order to subtract the level on the first line from the level on the second line and to output an output signal with a first value at a first comparator output if the difference formed by the subtraction has a first threshold value exceeds, this first threshold n value is chosen so that the output signal at the first comparator also changes its value if a level change occurs only on one of the two lines and the other line has a level corresponding to the one logical value of the binary data. 2. System according to claim 1, characterized in that a second comparator is provided, which with the is coupled to an output signal having the first value at a first line Generate comparator output when the level on the first line below a second threshold value and that a first memory is provided which via a first delay element with a first delay time with the  Comparator output is coupled and one of which has an output with a changeover switch is coupled to the data output from the first comparator output to the second Switch comparator output if during a period of time corresponding to the first delay time the output signal at the first comparator output constantly has the first value. 3. System according to claim 2, characterized in that the first memory further via a second Delay element with a second delay time with the first Comparator output is coupled such that the first memory is the changeover switch switches so that the data output from the second comparator output to the first comparator output is switched back if during a period of time corresponding to the second delay time, the output signal on the first Comparator output does not have the first value. 4. System according to claim I, 2 or 3, with a supply voltage, of which a lower one in each station Operating voltage for operating an electrical circuit in the station for Driving the first and the second line is derived, at least one Part of the stations via a third line carrying the supply voltage are connected, characterized in that a third, a fourth and a fifth comparator are provided, of which the third comparator with the second line is coupled to an output signal with the first value at a third Generate comparator output when the level on the second line is above a third threshold, of which the fourth comparator with the first Line and the fifth comparator coupled to the second line, and each an output signal with a first value at one of these two comparators fourth or fifth comparator output generated when the level at the with relevant comparator coupled line a fourth threshold  which lies between the operating voltage and the supply voltage, that a second and a third memory are provided, each one has first and a second input and an output, the first Input of the second memory with the first comparator output, the second Input of the second memory with the fourth comparator output, the first Input are coupled to the fifth comparator output and that the output of the second memory is coupled to the changeover switch to the third Comparator output to couple with the data output, and the output of the third Memory is coupled to the changeover switch to the second comparator output to couple with the data output. 5. System according to one of claims 1, 2, 3 or 4 with an error display output, characterized in that a first and a second counter are provided by which each have a counter input, a reset input and a counter output has, the count input of both counters with the first comparator output, the reset input of the first counter with the second comparator output, the Reset input of the second counter with the third comparator output and the Counter output of both counters and the output of the memory elements with the Fault indicator output are coupled.