DE1949755A1 - Discrete integrated circuit wiring and methods of making them - Google Patents

Description

DR.-INO. DIPL. -ING. M. SC 11 Ρ · ..- FHYS. D R. DIPL.-PHYS.

HÖGER-STELLRECHT-GRIESSBACH - HAECKER

PATENT LAWYERS IN STUTTGART I "s3 H J / 0 0

A 37 534 b

Sept. 13 1969

Texas Instruments Incorporated I35OO North Central Expressway Dallas / Texas, U.S.A.

Discrete integrated circuit wiring and methods of making them

The invention relates to an integrated circuit arrangement with several in a semiconductor substrate at a distance from one another formed integrated circuits which have metallic connections and are arranged in several levels by means of a Connection system can be connected to one another. The invention also relates to a method of manufacture such an arrangement in which the integrated circuits in the semiconductor substrate and above that in several Connection system arranged on levels are formed.

The intention behind the manufacture of larger monolithic structures from integrated circuits is to increase the number of integrated circuits Reduce circuit units per device. With the current state of the art it is now quite possible to accommodate a complete circuit system on a single semiconductor wafer by adding a large number of individual

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integrated circuits on this from a single single crystal cut out silicon wafer with a diameter of about 40 mm. Anyone can individual integrated circuits to represent a logical or other puncture about 20 or more active and contain passive components. As the component density on the semiconductor wafer increases, the complexity of the interconnections increases as well, so that ultimately a multilevel metallization is required, which means that the eink Individual interconnections can be arranged in several connection levels separated from one another by insulation.

In order to achieve such high density integrated circuit layouts, a number of different have been used Techniques developed. In one a 100% circuit utilization In order to accomplish this, the components are integrated on a single semiconductor wafer Circuits connected to one another within a first metallization level in such a way that they integrate a large number of individual ones Form circuits that can perform logical or other punctures, but not yet mutually are connected. An insulation layer is then placed over the first metallization level, then this is used accordingly A fixed, preselected pattern of through-holes is introduced and, finally, another layer of metallization is applied applied to this insulation layer, with which the mutual connection of the individual integrated circuits is performed with each other so that a complete circuit system results. When the production is finished, one now examines the Öcha'ltkreissystem, especially with regard to it on its mode of action. Is now only a single component or one of the multilayer interconnections or a Circuit so defective that it cannot be repaired, like this

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the entire arrangement is unusable for the intended purpose and to be evaluated as a committee.

Given that a $ 100 exploitation is more integrated Circuits on a single semiconductor die is highly unlikely in the current state of the art, "discrete wiring methods" have been developed to in which on the relevant semiconductor plates a single number Integrated circuits have been formed larger than that required to puncture the circuit system. Before making a multilevel interconnect, the individual integrated circuits were punctured Checked efficiency, according to which only the circuits found to be good are connected by a special interconnection pattern became. Such discrete wiring prevents an entire arrangement from being integrated as a result of some faulty Circuit becomes scrap, which increases the yield tremendously. Such a discrete wiring method is shown in Electronics (February 20, 1967, pp. 143-154) and in one older registration (official file number .....).

Although now the discrete integrated circuit wiring techniques developed up to now have a high packing density However, difficulties arose from the fact that the discrete wiring directly above each integrated circuits were arranged in a tiered manner, which required a large number of line crossings and providing through connections through the individual insulating layers. The "through connections" turned out at times as interruptions, in that the electrical contact to be established between two levels is insufficient or insufficient accomplished. Such interruptions can be caused by inadequate etching of the feed-through holes through the insulation

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li layer or by insufficient metallization of the Implementation arise. On the other hand, crossovers are the possibility of short circuits occurring between the subject to metallic, crossing lines of the various levels if the insulating layers are deficient have insulating oxides.

In order to reduce the rejects caused by faulty leadthroughs and crossovers, further techniques W have been developed. In such a method, redundant through connections are provided in a multilevel arrangement with a storey-like structure, in which only the through connections found to be in order are used. For such a technology, however, a further manufacturing step is required to generate test fields at the through connections, so that this technology is limited to systems that have a relatively high level of space redundancy, as is the case with shift registers or the like. may be the case. Moreover, such techniques do not provide a means of repairing defective integrated circuits or connections, since the multi-level stacked arrangement does not allow this.

The object of the invention is now to avoid the aforementioned disadvantages by developing a discrete wiring technique which is a subsequent repair as well as a clear and easy test without the use of special test connections or the like. in the case of multilevel interconnections for the connection of integrated circuits on a semiconductor wafer better made possible.

This object is achieved for an arrangement of the type mentioned according to the present invention in that the Connection system has several conductor strips that are not

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are led to the connections of the integrated circuits, and that a separately determined for each circuit arrangement Pattern of connecting lines is provided, the selected, functional conductor strips with selected, functional Connect integrated circuits in an electrically conductive manner. When making such an arrangement, starting from a method of the type mentioned, according to the invention also proposed that after the formation of the integrated circuits initially only the conductor strips are generated, whereupon the integrated circuits and these Conductor strips are subjected to a test of their electrical properties, and then the .Connecting lines be generated.

A large number of integrated circuits, which are arranged in groups, are expediently provided on a semiconductor carrier and are spatially considerably separated from one another and in which the connections are extensions in the form of over have an insulating layer extending lines. A multilevel network is established in a first area of the insulating layer formed from conductor strips between the integrated circuits. The integrated circuits and the conductor strips are electrically tested and registered accordingly, after which based on the test results in a second area Discrete connections are made through the insulating layer. The discrete connections lead to selected parts of the multilevel network and the extended connections of the integrated circuits »whereby the integrated circuit assembly is completed.

The invention thus particularly relates to complex semiconductor arrangements in microminiaturized training by creating a predetermined network of conductor strips with a majority

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of crossings and feed-through connections on a semiconductor carrier is formed in an area between spatially separated integrated circuits or groups of circuits, The Integrated circuits and the network of conductor strips are then based on certain preselected electrical properties checked what to look for a special pattern of discrete lines between the networks and the integrated ones Circuits for performing the desired system function 'forms.

The network of conductor strips is in particular through a special multi-level network of conductor strips with a Variety of crossovers shown. Feedthrough connections are created in the multilevel network by connecting ends of the Conductor strips are routed overlapping over the edges of the insulation that separates the individual conductor levels. Additionally If a part of the conductors of one network level is not formed in a straight line, which leads to connections of conductors of a Level with those in another level, which extend in another direction, become possible.

The semiconductor carrier is expediently provided with an insulation layer which is not attacked by etching agents which etch away the oxides and metals that are otherwise used. This insulating layer preferably consists of silicon nitride. This passivates the carrier immediately below to prevent electrical degradation of the surrounding integrated circuits. In addition, the silicon nitride layer enables formation of _v planes between the integrated circuits on which a reasonable line network of predetermined fixed configuration as well as the discrete wiring. can be brought.

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Further details and features of the invention can be found in the attached claims and / or the following description, which is used to explain one shown in the drawing Embodiment of the invention serves. Show it:

Pig. 1 is a plan view of a portion of a complex integrated circuit arrangement after the manufacturing stage , in which a first metallization layer has been applied;

Pig. Figure 2 is a top plan view of the circuitry of the Pig. 1 after the application of two further metallization layers ;

Pig. 3 shows a section along line 3-3 of Pig. 2J "Fig. 4 is a section along the line 4-4 of Fig. 2 \ Fig. 5 is a section along the line 5-5 of Pig. 2J

Pig. 6 is a view of an overpass according to the present invention Invention and

. FIG. 7 shows a view of a lead-through connection according to FIG present invention.

In Fig. 1 is a greatly enlarged section of a silicon wafer 10, in which a number of integrated circuits 12, 14, 16, 18, 20, 22 have been formed. Each of the Integrated circuits contain a large number of active and passive components to represent one logical or another Function. Of course, the part 10 represents only a piece of an overall arrangement located on the single crystal wafer The integrated circuits can be produced in a conventional construction, such as by the epitaxial production or the multiple diffusion process; however, any other manufacturing technique can also be used. For a more detailed description of the manufacturing

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integrated circuits is referred to Baum et al, Integrated Circuits, McGraw-Hill Book Company, 1965, particularly pages 127-1651.

The integrated circuits can use pn junctions or, on the other hand, dielectric barrier layers. In addition to the conventional transistors, junction field effect transistors, metal oxide field effect transistors, thin-film arrangements and the like can also be used to construct the integrated circuits. Although silicon of the invention is used as Halbleitermateriel in Ausführungsbei-8piel, other semiconductors such as germanium or ψ ■ can find well-known III-V group for many examples in the same way application. The disc section 10 can be polycrystalline and intrinsically conductive or semiconducting; It does not therefore need to be monocrystalline and intrinsically conductive, as in the present exemplary embodiment.

The integrated circuits 12 to 22 are spaced from one another arranged; this results in areas lying in between, of which a first area 24 is used to create a conductor matrix is used as described below internal interconnections within the integrated circuits 12 to 22 are a simplification in the illustration

. in some places due to have been omitted and not drawn.

'Outside of the first region 24 are additional areas 26, 28, 30, 32, which are intended to receive a discrete wiring according to the present invention in the course of a Pabrikationsprozesses. As will be described in detail later, the regions 24 to 32 and the upwardly facing surfaces of the integrated circuits 12 to 22 are covered by a suitable insulating material, which is preferably silicon nitride. A metallic covering 34 extends around the

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integrated circuits 12, 14, 16. In the same way, a metallic coating 36 extends around the integrated Circuits 18, 20 and 22. The metallic coverings 34, 36 later serve as a shielding and zero volt lead Links.

A plurality of parallel metallic strips 40, 42, 44 are located on the first area 24. The area 26 lies between the strips 40 and 42, the area 28 between the Stripes 40 and 44, while the area 30 lies below the stripes 44. The metallic coverings 34, 36 as well as the metallic ones Strips 40, 42, 44 are applied to the insulating layer made of silicon nitride.

Each of the integrated circuits 12 to 22 has Connections 46 which protrude from the semiconductor wafer section 10 and the connection to the integrated circuits Establish via holes in the insulating layer. The connections 46 are in the course of production with ground and voltage supply lines tied together. The integrated circuits 12 to 22 have further connections 48, which inputs and outputs represent for logic and other circuits; they also rise from the disc section 10 through holes in the insulating layer. Certain connections 48 must now with other other integrated circuits · in order to achieve the desired system function.

In Pig. 2 shows the final assembly of the integrated circuit arrangement shown in FIG. 1. An insulating layer 50 designed according to a specific pattern let over the first metallization layer shown in FIG laid out of the metallic coverings 34, 36 and the metallic strips 40 to 44; the end sections of the metallic strips 40, 42, 44, however, are not affected by the insulating layer 50

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covers. It still does not cover the integrated circuits. 12 to 22 as well as areas 26, 28, 30, 32.

Now a second metallization layer is applied, which consists of several groups of metallic strips; a first group of metallic strips 52 lead from the terminals 48 of the integrated circuits 12 and 14 via the insulating layer 50 into the regions 30, 28 and 32. The strips 52 allow Connections to any ports 48 of the integrated circuits or between multiple circuits by means of the later discrete wiring to be discussed. In the same way, metallic strips 54 lead from Integrated circuit 16 over the insulating layer 50 in the areas 32 and 26. Metallic strips 56 are also used for Connection between the terminals 48 of the integrated circuits 20 and 22 with the areas 28 and 30 used. In the end uniform metallic strips 58 connect the terminals 48 of the integrated circuit 18 over the insulating layer 50 with the region 26. A pair of wider metal strips 59 lie likewise on the insulating layer 50 for later use as a voltage supply line.

Pig. 2 also contains further conductor strip groups in this second level; Strips 60 are arranged above the metallic strips 40 at right angles to them and are separated from them by the insulating layer 50 lying in between. T-shaped strips 64 adjoin the strips 60 in that they run parallel to them and are also attached to the insulating layer 50 above the metallic strips 40. I-shaped metallic strips 62 adjoin the strips 64, but have a right angle, which is why they run perpendicular to the latter and in the same direction as the metallic strips 40. From Fig. 2 is easy to.

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see how in the first area 24 between the integrated circuits 12 to 22 a complex multi-level network the way described came about. So many crossovers are formed because the overlying metallic strips 60, 62, 64 run essentially at right angles to the metallic strips 40 below. Bushing connections between the first and second metallization level of this network are simply achieved by the fact that the ends the metal strips 62 and 64 extend beyond the insulating layer 50 and are thus in ohmic contact with corresponding ones metallic strips 40 come. By doing so Overlap technique is avoided according to the present invention that actual through holes through the insulating layer must be performed in which there is a much higher probability of mistake; "Implementations" will be thus accomplished by continuing the conductor strips beyond the edges of the insulating layer 50. The areas 26 to 32 thus form extremely large openings for bushing connections, in which there is no large geometric opening Pursuit loyalty is required.

After this multilevel network has been created according to a fixed and predetermined pattern, a series of tests is carried out away; by means of them, the integrated circuits and the network according to the invention are adjusted to predetermined electrical characteristics As described later, the test results are checked processed by a computer that has a special Calculates the pattern for the discrete wiring to be applied to the areas 26, 28, 30, 32.

Discrete connections 70 to 76 are now directly on the Insulation layer applied, at the same time and in the same way on areas 26, 28, 30 and 32.

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bind selected terminals 48 of the integrated circuits over the multilevel network with one another. "Discrete connections 78 lead from selected connections 46 to the metallic ones Coverings 59, which preferably carry supply voltages. These discrete connections create the discrete wiring carried out, by means of which the entire integrated circuit of the semiconductor wafer part 10 is fully wired and becomes functional.

FIG. 3 shows a section along the line 3-3 in FIG. 2. An insulating layer 80, for example made of silicon oxide, extends over the surface of the semiconductor wafer 10. A further insulating layer 82 is made over the layer 80 Silicon nitride applied. The metallic connections 46 extend through the oxide layer 80 and the nitride layer 82 and thus form the connection of the integrated circuits 12 and 14 to the outside. As will be described later, the silicon nitride layer 82 by etchants, which are commonly used for etching silicon oxide or metal layers are not attacked, so that processing continued after the silicon nitride insulation layer 82 has been applied of the disc part 10 is possible with such etchants to achieve the multilevel structure. The metallic covering 34 lies on the silicon nitride layer 82 and is in turn covered by part of the insulating layer 50. · .The.metallische Lining 59 lies over the insulating layer and has electrical contact with the discrete connection 78. The latter connects the connection 46 of the integrated circuit 14 with. the metallic covering 59.

Fig. 4 shows a section along the line 4 - 4 in Fig. 2. The disc part 10 is covered by the silicon oxide layer 80 ', which in turn is covered by the silicon nitride layer 82.

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The metallic strips 40 and the metallic covering 34 of the first metallization level lie on the silicon nitride layer 82. The insulating layer 50 covers the metallic Strip 40 and the metallic covering 34. It ends at the point marked with 50a, at which the second region 32 begins (Pig. 1 and 2). The metallic strip 60 of the second metallization level runs on the insulation layer 50 and overlaps the location 50a, being in contact with the discrete Connection 76 is coming. In Pig. 4, a number of crossovers of metallic interconnect strips are shown.

In Pig. 5 is a cut along line 5-5 of the Pig. 2 shown. The silicon oxide layer 80 extends over the surface of the semiconductor wafer part 10 and above it there is again the silicon nitride layer 82. A metallic one Strip 40 of the first metallization level overlies the silicon nitride layer 82. The insulating layer 50 extends extending over most of the length of the metallic strip 40, with only the end portions of the metallic strip 40 are not covered by them. Several metallic strips 60 of the second metallization level are evenly spaced over the insulating layer 50. The T-section of the metallic Strip 64 extends over the edge of insulating layer 50 and forms at its end at location 64a make contact with the metallic strip 40. This provides a feed-through connection between an upper metallic strip Strips of the second metallization level and a lower metallic Strips of the first level of metallization of the multilevel network. In addition, the discrete connection 70 has also at the point 64a direct electrical contact with the metallic strip 64 and thus contact with the strip 40. Regardless, other discrete connections 70 in FIG. 2 only contact metallic strips 40.

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Pig. Figure 6 shows a view of a typical line crossing between two lines of the multilevel network running in adjacent levels. The insulating layer 50 separates the metallic one Strip 40 of the first metallization level from the metallic strip 60 of the second metallization level. The ends of the metallic strips extend beyond the insulating layer 50, making them easy for example brought into ohmic contact with discrete connections and, moreover, can be easily reworked.

k Pig. 7 shows a view of a typical through connection according to FIG of the present invention. An L-shaped metallic strip 62 of the second level of metallization laps over the end of the Insulating layer 50 out and thus comes into direct ohmic contact with the metallic strip 40 of the first metallization level. By such a device, which in an open, relatively large area such easily accessible ohmic connection of two of two different Metalization planes originating conductor strips enables the scrap rate of production is significantly reduced as well as post-processing of faulty connections is greatly facilitated.

\ As mentioned initially, any conventional technique for the production of various insulating or conductive layers, the arrangement inicrominiaturisierten be used. It goes without saying that the circuits shown in FIGS. 1 through 7 are merely exemplary; Within the scope of the invention, modifications to the exemplary embodiment shown here are also possible.

In an example method for producing the embodiment, the integrated circuits 12 to 22 are on

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the semiconductor wafer 10 generated by epitaxial growth or multiple diffusion. An insulating layer, for example a silicon oxide insulating layer 80, is formed on the wafer 10 by, for example, a silicon hydrogen using method generated. A photoresist layer (photoresist layer) is then according to a usual Method placed over the insulating layer 80 and through a suitable photomask with a corresponding, fixedly predetermined Pattern designed by suitable exposure. This will make the over the connections of the integrated circuits exposed areas. The photoresist layer gets its pattern by an exposure with an intermediary Photomask; it is then developed by spraying the disc 10 with a suitable developing solution. That Disc 10 is now immersed in an etching solution, for example in a buffered hydrofluoric acid solution, whereby 'the Regions located above the connections of the integrated circuits 12 to 22 are etched free of the insulating layer 80. The remaining photoresist material is now removed from the wafer 10.

A uniform metal layer, for example aluminum, is then made by means of a suitable technique, for example by steaming, dejected. Photoresist material is applied, exposed and developed; then it is etched, whereby it is achieved that the connections 46 and 48 are now as an aluminum layer above the oxide insulating layer 80.

A thin layer of silicon nitride is placed as an insulating layer 82 over the oxydis ^ olierschicht 80, but this is done that the metallic terminals 46 and 48 remain exposed. Silicon nitride is usually used for integrated circuits for etching insulation or metal

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All reagents used are not attacked.

A uniform metal layer, for example made of aluminum, is now placed over the silicon nitride insulating layer 82. A photoresist layer is then placed over the metal layer and exposed over a suitable solid pattern Photomask and continue treating it as previously described. Through the development of the photoresist material and the subsequent etching, the metallic coatings 34, 36 and the metallic strips 40 to 44 are produced, whereby the state shown in Fig. 1 is reached.

The insulating layer 50, made of silicon oxide, for example, is over the surface of that shown in FIG Arrangement laid. Photoresistive material is in turn applied and over a corresponding, with a fixed pattern provided mask exposed. Subsequent etching removes the areas 26, 28, 30, 32 apart from the silicon nitride insulating layer 82 etched away. The latter does not react to the etching liquid and represents the later insulation layer which the discrete wiring can be done.

After applying the first metallization layer 34, 36, 40, 42, 44 and partial subsequent insulating cover the same through the insulating layer 50 is another metal layer, for example made of aluminum, placed over the device. Using another mask with a fixed pattern and the usual etching technique this metal layer is etched so that the metallic strips 52 to 64 of the second metallization layer of the multilevel network. With this production stage, a line matrix is therefore over a lower and an upper metallization level have been created, the lines of the lower level being with those the upper cross (Fig. 6) and partly by means of the invention

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appropriate bushings (Pig. 7) are connected, but the extended connections of the integrated circuits are still not connected are.

Now all lines of the matrix as well as the supply lines to the connections of the integrated circuits and the latter itself tested for predetermined mechanical and electrical properties. This happens after one through one older patent application (official file number) described type. The check is carried out using the Lines with multiple probe tips, each of which has certain probe tips with electrical input signals and others again emit or receive electrical output signals. The recorded electrical output signals form a measure for the electrical properties of the electronic components, such as the transistors and also an indication of whether certain lines short circuits or interruptions on-r point. Of course, the test steps are not limited to simple mechanical and electrical tests; you can by other devices, such as thermal or field scanning devices, to be continued.

To test the wafer 10, it is brought into a precise position and optically aligned in the same way as for the test with multiple probes is required. It is now automatically shifted step by step and so in several test runs scanned by the probes until all of interest Data are recorded. This data is about correct working or failure of the integrated circuits and conductor tracks cached on tape storage. From there they are displayed in a work program of a digital computer, the is programmed to generate a "map" of the disk on which the integrated circuits and lines are marked by "good" and "bad".

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Using this map, the digital computer generates a digital route pattern of the interconnections, whereby only the Integrated circuits found to be good by means of lines, feedthroughs and crossings found to be good in one desired type to achieve the overall function. The resulting digital path pattern is generated via a Digital to analog converter converted into analog signals. The latter control the deflection and intensity of a cathode ray tube. Their beam is bundled via a lens system and onto a light-sensitive plate or onto a light-sensitive one fe film directed.

On such. A mask image is created on the film by means of small light spots by means of step-by-step exposure. One such computer-controlled mask generation is described in Electronics, February 20, 1967, under the heading "Multilevel interconnection generator".

After the film has been exposed according to the desired discrete wiring, it is developed. The washer-10 receives a thin metal film, such as a molybdenum-gold layer, and over it a layer of photoresist material. The film developed above now serves as a photomask for the appropriate design of the photoresist material Exposure so that the discrete wiring is created. After exposure and development of the photoresist material as well as after removing the excess metal film by a suitable etching liquid, which is molybdenum-gold, however does not attack aluminum of the first and second metallization levels, the discrete wiring pattern results from the discrete compounds 70 to 78. Suitable caustic liquids do not form highly concentrated nitric acid and cyanides. the The arrangement wired in this way is shown in FIG. 2; with her

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the desired system function is achieved.

The present invention provides a multilevel microminiaturized one Integrated circuit arrangement produced, which manufactured with high economic efficiency and high yield can be achieved by creating a greater number of pre-fabricated crossovers and penetrations. By a Reduction of the reject rate is the apparently dealt with it lower packing density as a result of in part with Significant distances between integrated circuits arranged more than just canceled. Moreover, leave it Today's manufacturing techniques for integrated circuits have significant port steps with regard to the geometrical Recognize dimensions for individual circuits, which would make it possible to identify such circuits and their external wiring much smaller than what is currently happening. As a result of the storey-like arrangement of the multilayer connections for the integrated circuits of previous arrangements it appeared impractical to use the integrated To make circuits as small as the state of the art allows. With the present invention, the integrated However, circuits are designed to be as small as the respective technologies allow.

According to the invention, the number of crossings compared to the number of bushings is kept significantly higher, whereby a balance is created between the number of crossings found to be good and that of bushings found to be good, which is a prerequisite for a satisfactory pattern of discrete wiring. A relatively complex computer program is used to create the discrete wiring, although the effort required for this is outweighed by the high yield guaranteed by the present invention. _20th

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The large number of lines and connections required for maintenance and revision has also proven to be advantageous exposed and easily accessible. Especially thanks to the fact that the lines are not built above the Circuits, rather than being attached to the side of them, can be revised without the risk of damaging the integrated circuits are made.

The use of silicon nitride as an insulation layer in the Embodiment according to the invention leads to a passivation of the semiconductor surface, whereby an ■ electrical "Deterioration of the arrangement due to ion migration in the silicon oxide is avoided. In addition, the subsequent process steps of etching oxides and metals are made possible in this way, because the silicon nitride is not attacked by the usual etchants. Prove to be particularly useful also the relatively large-scale "bushings", which avoid that, as before, one has to work with very tight tolerances.

The use of L-shaped metal strips in the prefabricated multi-level network enables the direction of conductor strips to be changed. The moreover used T-shaped metallic strips increase the flexibility of the arrangement in the same Sense, so that connections of three conductor strips in three different directions are possible. Of course you can Configurations other than the aforementioned L- and T-shaped strip shapes have been used for the present invention will. Modifications to the exemplary embodiment shown are possible within the scope of the inventive concept.

The idea according to the invention, on a semiconductor substrate with integrated circuitry arranged at a distance from one another

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lines between them to arrange an insulating layer that cannot be attacked by oxide and metal etchants, in particular Containing silicon nitride is also advantageous regardless of the other features of the present invention.

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Claims (12)

A 37 534 b - 22 - k - 71 September 13, 1969 Patent claims: Μ.] Integrated circuit arrangement with several in one Integrated circuits formed at a distance from one another and having metallic connections and can be connected to one another by means of a connection system arranged in several levels, thereby characterized in that the connection system has a plurality of conductor strips (34, 36, 40 to 44, 60 to 64) which do not to the connections (46, 48) of the integrated circuits (12 to 22), and that one for each circuit arrangement Separately specific pattern of connecting lines (70 to 78) is provided, the selected, functional Connect conductor strips with selected, functional integrated circuits in an electrically conductive manner. 2. Arrangement according to claim 1, characterized in that of the connections (46, 48) of the integrated circuits Connection conductor strips (52 to 58) are led away. 3. Arrangement according to claim 1 or 2, characterized in that that the conductor strips and the connecting lines are arranged over different areas of the semiconductor substrate with the area for the conductor strips between the integrated circuits. 4. Arrangement according to one or more of the preceding claims, characterized in that at least two groups of conductor strips (40 to 44; 60 to 64) are provided, . the conductor strips within a group approximately are parallel to each other, conductor strips are different -23- ootiti / titt A 37 534 b - 23 - k - 71 ' September 13, 1969 Groups, however, preferably have a right angle to each other form, and that over the lowermost group of conductor strips is an intermediate insulating layer (50). 5. Arrangement according to claim 4, characterized in that at least some of the conductor strips protrude beyond the intermediate insulating layer (50) and conductor strips on the contact the other side of this intermediate insulating layer. 6. Arrangement according to one or more of the preceding claims, characterized in that conductor strips (62, 64) are provided in one plane of the connection system, which form angles or are curved. 7. Arrangement according to claim 6, characterized in that the non-straight conductor strips L-shaped (62) or T-shaped (64) are formed. 8. Arrangement according to claims 4 to 6, characterized in that the angled or ' curved conductor strips (62, 64) protrude beyond the intermediate insulating layer (50) and at least partially conductor strips (40 to 44) on the other side of the intermediate insulating layer. 9. Arrangement according to one or more of the preceding claims, characterized in that between the integrated Circuits on the semiconductor substrate a lower, metal and oxide-resistant insulating layer (80, 82) is provided. 10. The arrangement according to claim 9 »characterized in that the lower insulating layer contains silicon nitride (82). -24- 009818/1211 A 37 534 b - 24 - k - 71 September 13, 1969 11. Arrangement according to claim 9 or 10, characterized in that the connecting lines on the lower insulating layer lie. 12. The method for producing an arrangement according to one or more of the preceding claims, in which in the semiconductor substrate the integrated circuits and above it the interconnection system arranged in several levels are, characterized in that after the formation of the integrated circuits initially only the conductor strips are generated, whereupon the integrated circuits W and these conductor strips are subjected to a test of their electrical properties, and that the connecting lines are then produced. 009818/1211