GB1271243A - Integrated circuit arrays utilizing discretionary wiring and method of fabricating same - Google Patents

Abstract

1,271,243. Integrated circuits. TEXAS INSTRUMENTS Inc. 8 July, 1969 [8 Oct., 1968], No. 34323/69. Heading H1K. A method of providing multilevel interconnections between the satisfactory integrated circuits 12-22 of a system spaced on a surface of a substrate 10 comprises forming a first group of spaced elongated conductors 4-44 on the substrate surface adjacent to but spaced from the integrated circuits, each of said first conductors having its ends terminating in connection areas 26-30 with the remaining portions of the conductor defining a first conductor area, then selectively applying a layer 50 of insulation over these first conductor areas and substrate surface, then forming a second group of spaced elongated conductors 60-64 extending transversely to the first conductors over this layer of insulation, each of said second conductors having its ends terminating in connection areas 32 and selectively overlying and connected to respective ends of the first conductors, and finally forming a third group of spaced elongated conductors 70-78 according to an individually calculated pattern for the circuit system in the connection areas to interconnect satisfactory circuits as required via satisfactory first and second conductors. Unsatisfactory circuits and conductors are not connected in the system. To calculate the pattern of the third group of conductors, the integrated circuits and conductors of the first and second groups are tested and those which are satisfactory are selected for interconnection, the testing and interconnection pattern calculations being performed by computer. Layers 34, 36 of conductive material to form earth buses for the circuit system may be applied prior to the application of the layer 50 of insulation. The provision of power supply conductors 59 may also be carried out as a separate step of the method. The layer 50 of insulation, which is generally silicon oxide, may be provided with a surface layer of silicon nitride to provide protection against the etchants used during subsequent processing steps.