DE1946653B2 - Combining cct. for binary variables - uses magnetic cores with rectangular hysteresis loop - Google Patents

Abstract

Each of the magnetic cores has separate winding for obtaining the binary variables and interrogation pulses in one magnetisation direction and for obtaining recording pulses, the duration of which is shorter than that of the shortest binary variable, in the opposite magnetisation direction. During a first time period an interrogation pulse is obtained in one part of the core, while a recording pulse is obtained in a second part of the core, and during a second time period a recording pulse is obtained in the first part of the core, while an interrogation pulse is obtained in the second part of the core. The read signal is supplied to the read winding via a NOR coupling logic, interrogated during each alternate period.

Description

Magnetic cores with a rectangular hysteresis loop are used extensively to build gates for linking binary variables. The advantages of such cores include m

their almost unlimited service life their high reliability, as well as their ability to generate the link result to be able to save.

In the case of a large number of logic circuits with magnetic cores, the Vana-

have common or separate input windings supplied, whereby they influence the respective magnetic core in the same direction of magnetization When the resultant, count through the initial var generated field strength the saturation field strength of the

Magnetic core exceeds, the core is magnetized The signal generated by induction in such a magnetic reversal or that of e.ner Query i.e. when influencing the core in the opposite direction Direction of magnetization on - '-

^66. ° r. ι- c: ™ "ol ciollt Harm Ha:

Input variables (e 1, e 2) is supplied, and that Gegengcbc ^. '""f;"-:;;.; ,,. - _d

^{the S.gnalst "™ n das} occurring from the reading windings (n 2A 1. η 2A 2) of this 35 sewing winding

Basic gate emitted impulses both as an oversight link. ^en "P;« ^h = "^ Ä,

Link variable to the respective other Grundgat- (See e.g. Taschenbuch der Nachnchtem

ter passed on as an output variable edition 1967 by K. S te ι η bu c: h p.4Λ <

(a 1, a 2) , which creates a bistable. With such a co.nzid! nzlog ^ e ^ e

in each case two inverse output variable delivered 4 ° considerable difficulties de Kmnzdenz of the K ^ _he

Trigger circuit is formed to ensure the input signals supplied by the inputs

variables (e 1 e 2) each in one or the other - at least one part of this ^Em ^^^ ^]

ren stable state is set (Fig. 7). gnals of other cores s.nd. with what you ze. Jeher Verlau

3. Circuit arrangement according to claim 1 or 2. strongly of the tolerances of the useile_ cores

characterized in that the writing pulses 45 temperature and the length of the guarantee ao-

characterized in that the input for all basic gates from a central input pulse source to be delivered.

4 circuit arrangement according to one of the preceding claims, characterized in that the reading winding of the magnetic core of that basic gate (Aa) which emits output variable, with def reading winding (n 2k) one only by interrogation (K)

are pending. _D "u ^

With a solution that avoids these * = problem denzlogik that the Ke.nen input variables contained herein does not de core "^ j so _youre n but to the ^ magnetisierungdirch, En write pulses to prevent De Einschre.b.mpulse

with def reading winding (n 2k) of a compensation core (K) that is controlled only by interrogation, in this case basically shorter than the input pulses. In addition to avoiding the difficulties inherent in the coincidentally soft magnetic material in series, one thing that is switched is that the NOR logic of this type that arises when interrogating still has the advantage that even with voltages in the two cores, one another contradicts one another - the summation of the interference pulses caused by magnetic

^ ese tensions of the two nuclei counteract each other (Fig. 8).

5. Circuit arrangement according to one of the preceding claims, which consists of a number of There is basic gate groups that do not process input variables at the same time, characterized in that that the interrogation pulses are supplied by switchable interrogation pulse generators that only provide query pulses as long as the variable to be linked to the relevant basic gate group are fed.

6. Circuit arrangement according to one of the preceding Claims, characterized in that the summation of the glitches caused by magnetization of cores from the remanence state to the saturation state associated with the same logical state arise, cannot result in an incorrect result, as they are not able to the magnetization reversal due to the generally longer write-in pulse and thus the delivery of a to prevent the signal corresponding to the non-fulfilled NOR condition.

It is also already known to combine several such NOR gates to form circuit arrangements, with the help of which more complex logical links can be carried out. Both

the query windings as well as the read windings of the cores of the individual NOR gates connected in series. In this way, the interrogation of the individual cores takes place at the same time and the read signals the individual cores are linked according to an OR function (see Steinbuch, »Taschenbuch der Message Processing ", 1967, p. 428). With such an interconnection, only such Build logic circuits whose output signal is the result of an OR operation. which means that the number of links that can be implemented using this technology is limited.

The circuit arrangement according to the invention is not subject to this restriction. The invention relates to namely also a circuit arrangement for linking binary variables that consist of similar There are logic elements, each using a magnetic core with a rectangular hysteresis loop are constructed, each of which has separate windings from the variables to be linked and of interrogation pulses in one direction of magnetization and of write-in pulses, their pulse duration is shorter than that of the shortest variable to be linked, in the other direction of magnetization is excited, so that on its reading winding a NOR operation of the variables supplied to it corresponding Read signals occur. According to the invention, this circuit arrangement is characterized in that that to a first clock phase one part of the magnetic cores interrogation pulses and the other part of the Magnetic cores write-in pulses and, in a second clock phase, the queried magnetic cores write-in pulses and interrogation pulses are supplied to the magnetic cores to which the write-in pulses have previously been applied and that the read signals of all magnetic cores of logic elements as further processed, Variables that act against a writer's excitation are only passed on to magnetic cores of such logic elements which are queried during the other clock phase.

In the circuit arrangement according to the invention, the NOR principle with its initially mentioned Advantages are retained even if the type of links to be implemented am The output of the circuit arrangement is other than an OR operation of the result variables of the rest Part of the circuit arrangement requires links, as will be explained in detail will.

The structure and mode of operation of the circuit arrangement according to the invention are illustrated below with reference to 9 figures and their variants are explained in more detail.

Fig. 1 shows the hysteresis loop of magnetic cores, how they are used in the circuit according to the invention;

F i g. 2 shows a known basic NOR gate;

F i g. 3 shows a construction diagram of the circuit arrangement according to the invention;

Fig. 4 shows the known NOR gate according to FIG. 2 in a different representation, which is also used for the other embodiments of the circuit arrangement according to the invention is used;

F i g. 5 shows an embodiment of the circuit arrangement according to the invention for realizing the Or link;

F i g. 6 shows an exemplary embodiment of the circuit arrangement according to the invention for realizing the U N D linkage;

F i g. 7 shows the circuit arrangement according to the invention configured into a bistable multivibrator;

F i g. 8 shows a circuit arrangement for compensating for in the circuit arrangement according to the invention occurring interfering signals;

F i g. 9 shows a circuit arrangement for amplifying the cores of the basic gates of the invention Circuit arrangement supplied or the pulses emitted by these cores.

The F i g. 1 shows a rectangular hysteresis loop of magnetic cores such as are used to set up the circuit arrangement according to the invention. The positive remanence state + Br of such nuclei is assigned the binary value 1 and the negative remanence state - Br is assigned the binary value O.

In FIG. 2 shows a basic gate which is known per se and is constructed using such a magnetic core and which is used to link the variables supplied to it in accordance with a NOR function. The magnetic core of such a NOR gate is symbolically represented here by a vertical, strongly drawn line and denoted by M. This magnetic core carries a query winding π 1, a reading winding η 2, which is connected in series with a diode D , a writing winding π 3, and a number of logic windings η 4 indicated that these windings sometimes have different winding directions. The interrogation winding η 1 and the logic windings π 4 have the same sense of winding, so that the pulses supplied to them influence the magnetic core in one and the same direction. The polarity of the pulses supplied to these windings is directed in such a way that they influence the magnetic core in the direction of the negative remanence state - Br assigned to the binary value O. The write winding η 3, on the other hand, has opposite winding directions, so that with the same polarity of the write pulses, magnetization takes place in the opposite direction, namely towards the remanence state + Br . The write pulses fed to the write winding π 3 are shorter in time than the shortest pulses occurring on the logic windings.

An interrogation pulse continuously interrogates the core via the interrogation winding, so that it is then always in the remanence state - ßr. In the pauses between the interrogation pulses, the core is excited by a write pulse that is also continuously applied via the write winding η 3 in the opposite direction after the positive remanence state + BrWm . The logical linkage of the variables supplied to the logic windings π 4 comes about because the write pulses and the pulses to be linked at the same time influence the magnetic core in opposite directions of magnetization. The logic signals to be linked influence the magnetic core in such a way that they prevent unimagnetization from the remanence state - Br, in which the core is after the query. If, on the other hand, no logic signals occur, the core becomes in

⁶ S magnetizes the positive remanence state + Br . With this reversal of magnetization, no current can flow through the read winding due to the blocking effect of the diode D , which means that the magnetization reversal with re-

relatively little writer excitement can go on. The diode also has the advantage that interference currents can be suppressed, which can be caused by tensions that may occur in the reading winding to connect logic windings of further cores are induced.

The following the interrogation pulse has Einschreibimpuls in the latter case, a magnetic reversal of remanent -for in the negative remanent - Br result, one to a binary 1 corresponding pulse is delivered to the sense winding. Such a pulse only occurs if a signal corresponding to the binary value 1 is not applied to any of the logic windings, which corresponds to the result of a NOR operation. Since the logic signals influencing the core always only magnetize it from the negative remanence state - Br to the negative saturation state - Bs , interference pulses supplied by other cores, even if they add up to a total interference pulse of large amplitude, cannot lead to a false signal, since the in each If the write pulse lasts longer than interference pulses, it still brings about a magnetization reversal into the remanence state + Br. In addition, as already mentioned at the outset, the difficulties that arise in the event of a magnetization reversal as a result of the coincidence of supplied pulses are avoided here.

On the basis of FIG. 3 it will now be explained in more detail how the individual basic gates are to be connected to one another in the circuit arrangement according to the invention and how they are to be operated. In the case of the FIG. 3, which contains the three NOR gates Gl to G 3, is an example that was not designed with a view to realizing a specific logical link, but is primarily intended to serve as a clear illustration. The cores of the three NOR gates CI to G 3 are provided with the same type of windings as the NOR gate according to FIG. 1. Interrogation pulses supplied by a central interrogation pulse source are supplied via two interrogation lines A I and A 2 , and write pulses supplied by a central write-in pulse source are supplied via two write lines 51 and 52. The interrogation winding π 12 of the gate G 2 is inserted into the interrogation line A 1. The interrogation windings nil and η 13 of the gates G 1 and G3 are inserted into the interrogation line A 2. In a corresponding manner, the write line 51 contains the write-in winding η 32 of the gate G 2 and the write line 52 contains the write-in windings π 31 and π 33 of the gates Gl and G3. The reading windings π 21 of the gate G 1 is connected to the logic winding η 42 of the gate G 2 via the diode D 1. The reading winding λ 22 of the gate G 2 is connected to the logic winding η 43 of the gate G 3 via the diode D 2. The reading winding π 23 of the gate G 3 can either be used to emit output signals or be connected in a corresponding manner to the logic windings of a further core. The logic winding π 41 of the gate G1 is connected either to a signal input or to the read winding of a further core, not shown here.

The interrogation pulses fed to the interrogation lines A 1 and A 2 or the write pulses fed to the write lines 51 and ⁶ S 52 each occur at different clock phases. Due to the connection of these lines with interrogation or write-in windings described above, the core of the gate G 2 is always queried at a first clock phase, whereas the interrogation of the cores of the gates G and G 2 takes place at the second interrogation clock phase. The same applies to registered mail; the core de: gate G 2 is written in for the first write clock phase and the cores of gates G 1 and G3 are written in for the second write clock phase. In connection with the connection of read windings with logic windings other cores described above, one recognizes that read signals as logic signals are always passed on to those cores which are queried for the other query clock phase or written to the other write clock phase. This, however, results in the freedom of movement in the construction of circuit arrangements for the implementation of any logical connections.

Before now to the explanation of some exemplary embodiments of the circuit arrangement according to the invention which are used to implement an OR link and an AND link or show the behavior of a bistable multivibrator, a representation of the The basic gates used here are explained, which ensures greater clarity than the representation the basic gate in Figs. 2 and 3.

The magnetic core of a NOR basic gate is also shown in FIG. 4 symbolized by a vertical, strongly drawn line. The upper end of this line becomes the remanent state + Br, or the binary value 1 and the lower end becomes the remanent state -Br. or the binary value O is assigned. The interrogation and the write-in windings are represented by an arrow running in the direction of this line, the direction of which indicates the magnetization state towards which the pulses supplied to the corresponding winding magnetize the magnetic core. The arrow symbolizing the query winding thus points in the downward direction, while the arrow symbolizing the writing winding points upwards. In contrast to the other arrows, the arrow for the interrogation winding is also filled in to indicate that the interrogation pulses cause a considerably stronger excitation than the other pulses. The logic windings λ 4 are also shown by arrows running in the direction of the core bar, which point downwards and in which the lines belonging to the windings are indicated. The reading winding is symbolized by an arrow pointing to the right from the core bar, the associated lines also being indicated. In order to identify the cycle phase of the pulses that are fed to these windings or emitted by these windings, the core bar is divided into two halves by a horizontal line. In the upper half, which is assigned to the one clock phase, are the arrows for the query winding η 1 and the read winding π 2 and in the lower half, which is assigned to the second clock phase, the arrows for the write winding are π 3 and the arrows for the logic windings π 4 are drawn.

In FIG. 5, using the symbols explained above, a circuit arrangement is shown which is used to implement an OR link between two variables. This circuit arrangement contains the two cores E and A. The two input variables e 1 and e 2 to be linked are fed to the logic windings / i4 £ of the core £ The read signal of the core E that via the read winding π 2Ε

is released, the logic winding η 4A is fed to the core A as the only logic signal. As the arrangement of the arrows for the query windings η i Fund π M or for the write winding /) 3 £ and η 3,4 in each different halves of the cores shows, the cores are queried or written to different clock phases.

If one or both of the input signals c 1 and e2 assume the binary value 1, they prevent a unimagnetization of the magnetic core E from the magnetization state - Br. In which it was moved by the previous interrogation pulse to the magnetization state + Br of this core E no read signal is emitted to the logic winding η AA of the core A. However, this has the consequence that when it is inscribed in the second inscription phase, a reversal of magnetization from the magnetization state - Br to the magnetization state + Br takes place. During the subsequent interrogation for the second interrogation cycle phase, a pulse corresponding to the binary value 1 is therefore emitted via its read winding nlA, which indicates that the OR condition was met. If, on the other hand, the OR condition is not met, i.e. if both input signals e 1 and e 2 have the binary value O, then core E emits a read signal, writing to core A is prevented and no read pulse is generated from core A when interrogated. which corresponds to the output of the binary value O.

In FIG. 6 shows an exemplary embodiment of the circuit arrangement according to the invention, which is used to implement an AND link. The circuit arrangement contains the two magnetic cores EX and Ll, whose logic windings η4Ei and n4 £ 2 are each fed to one of the input variables el and e2 to be linked, and the magnetic core A. to whose reading winding n2A the output signal is emitted. The read windings η 2Ei and /? 2 £ 2 of the cores Fl and El are connected in parallel and connected to the logic winding η AA of the core A with their non-grounded connection. The two cores £ 1 and El be interrogated at the same first Abfragelaklphase and enrolled at the same first Einschreibtaktphase. The core A is written in or queried for the second writing or query clock phase. If the AND condition is met, i.e. if both input variables el and e2 assume the binary value 1, none of the cores el and e2 are remagnetized and accordingly the core A does not receive a logic signal, which in turn means that it has its write-in pulse in magnetization state + Br and then magnetized back into magnetization state -Br for the second interrogation cycle phase, so that a pulse corresponding to the binary value 1 is emitted via the read winding π IA of core .4. For all other value combinations of the input signals el and e2, a logic signal is fed to core A from core £ 1 or from core £ 2 or from both cores, which logic signal prevents writing and thus the emission of an output signal.

In the case of the FIG. 7, the basic gates are connected to one another in such a way that a circuit arrangement with bistable behavior is produced, which is switched from one input signal to one stable state and from the other input signal to the other stable state. The circuit arrangement contains the two magnetic cores A i and A 2, whose logic windings η 4A i and η 4A 2 are each fed to one of the input variables el and e2. The logic windings of these cores are also connected to the read winding n2A i or η IA 2 of the respective other core. If, for example, the core A 1 is written in, it emits a read signal during the first clock phase of the interrogation pulse, which prevents the core A 2 from being written. This

ίο When it is interrogated, the core cannot emit either a blocking signal to the core A 1 or an output signal at the output a 2, so that the core A 1 is re-written when the next write-in pulse occurs. In this way, the core A 1 is permanently magnetized back and forth and thus continuously emits pulses at its output a 1, which corresponds to a stable state of the circuit arrangement. This permanent magnetization reversal of core A is only prevented when an input variable with the binary value 1 is fed to its logic input n4A 1. The core A 1 is then blocked and accordingly does not emit a read signal, so that the core A 2 is now remagnetized and continues to block with its read signal core A 1, even if its input signal e2 has meanwhile assumed the binary value O. Other write-in and read pulses have thus a continuous remagnetization of the core A 2 and hence the delivery of read pulses on the output of the consequence, which corresponds to the second stable state al. In a corresponding manner, the arrangement is switched back to the first stable state again by a logic signal e2 with the binary value 1 at the logic winding η 4Al of the core A 2.
As explained above, noise can not enrolled example, the magnetization magnetic cores from the remanence Br into saturation - Bs arise _# NOR basic gates do not affect in a disturbing manner, since they are the seeds of such gates also only the remanence in the corresponding saturation state magnetize and as a result of their short period of time they cannot prevent the magnet core from being magnetized reversed due to the write-in pulse that lasts for a long time. Only in the case of the basic gate emitting the output signal could such interference pulses have a disruptive effect, e.g. B. when the basic gate delivering the output signal controls a trigger stage. A further embodiment of the circuit arrangement according to the invention makes it possible to avoid such an occurrence of interference pulses, as shown in FIG. 8 shows, for this purpose the reading winding η la de: Magnetic core Aa of that basic gate which emits output variables and which is the only one shown in this figure, with the reading winding η 2k one!

Compensation core K connected in series. The winding sense of the two read windings is selected here so that when the compensation core K and the output core Aa are queried. which takes place for the same interrogation cycle phase, the reading tensions that arise in this way counteract each other and compensate for each other. Since the compensation core K is only influenced before interrogation pulses, that is, it is always magnetized only by the remanence state - Br into the saturation state - fi, only such pulses are compensated

siert, which arise with the corresponding magnetization of the output core Aa , but not the useful impulses, which stood by remagnetization from the remanence state - Br of the output core Aa into the saturation state

509584/34

7 59ft

stand -Bs arise.

In the above-described exemplary embodiments of the circuit arrangement according to the invention, it may be necessary to amplify individual currents supplied to the cores of this circuit arrangement or output by them. An amplifier that can be used universally is particularly suitable for this purpose, as shown in FIG. 9 and is described below. The pulses to be amplified are fed to the control windings η 1 of a magnetic core Kv . The output winding ns of this magnetic core is connected between the base and the emitter of a transistor Tr , which operates without a DC power supply and whose emitter is grounded. In the collector circuit of this transistor, the control windings of the magnetic cores to be influenced by the amplified pulses and a collector resistor are arranged, the resistance value of which depends on the use of the amplifier, i.e. on whether it is to be used as an interrogation pulse amplifier, a write pulse amplifier or a cable driver. These alternative configurations of the collector circuit are indicated by dashed lines. The following correspond here: use as query pulse amplifier and collector circuit A, use as write pulse amplifier and collector circuit B, and use as cable driver and collector circuit C. If the amplifier is only used for adaptation, e.g. B. used on the DTL technology, the collector circuit is designed according to variant D. In the case of use as a write pulse amplifier , a coil with inductance is inserted in the collector circuit of the transistor Tr , which flattens the rising edge of the write pulses and thus contributes to the fact that the write pulses are outlasted by the read signals of the magnetic cores, which serve as blocking signals .

If the circuit arrangement according to the invention consists of a number of basic gate groups that do not have to process binary variables at the same time, the interrogation pulses can instead be sent through a central one Interrogation pulse generator by interrogation pulse generators assigned to the individual groups which are made switchable and only deliver interrogation pulses as long as the relevant one Basic tag group to be linked variable are supplied. In this way the total Reduce the energy to be used for querying.

For this purpose 2 sheets of drawings

Claims (2)

Patent claims: 1. Circuit arrangement for processing binary variables consisting of logic elements of the same type consists, each using a magnetic core with a rectangular hysteresis loop are constructed, each of which has separate windings of variables to be processed and of interrogation pulses in one direction of magnetization and of write-in pulses whose Pulse duration is shorter than that of the shortest variable to be processed, in the other direction of magnetization is excited, so that on its reading winding a NOR operation of the Read signals corresponding to variables occur, characterized in that in a first clock phase one part of the magnetic cores (Eq, G 3) interrogation pulses and the other part of the magnetic cores (G 2) write-in pulses and to a second clock phase the queried magnetic cores (Gl, G 3) write-in pulses and the Magnetic cores (G 2) previously loaded with write-in pulses are supplied with interrogation pulses, and that the read signals of all magnetic cores of logic elements as to be processed further, Variable acting against a writer excitation only on magnetic cores of such logic elements are passed on, the query of which takes place during the other clock phase (e.g. FIG. 3). 2. Circuit arrangement according to claim 1, characterized in that it consists of two basic gates (A 1, A 2) , each of which is one of two IO the query and write pulses of the basic gates as well as the read signals of output signals emitting basic gates are passed on via the collector circuit e.nes DC potential-free controlled trans, -lr amplifier (Tr) , for which purpose they are passed on to the control circuit e.nes of the respective transistor amplifier associated magnetic core (Kv) with a rectangular hysteresis loop, the output winding (ns) of which is inserted into the base-emitter circuit of the trans.stor (Fig. 9).