DE1948377A1 - Circuit arrangement for processing binary variables - Google Patents

Description

Circuit arrangement for processing binary variables The logic elements, from which circuit arrangements for processing binary variables are composed, are often made using a magnetic core with a rectangular hysteresis loop built, as they have a number of advantages, such as unlimited lifespan, high reliability, storage capacity and integrating properties that are have a beneficial effect in the event of malfunctions. In known links of this type during the writing process either through the coincidence of the variables to be linked with a write-in pulse the magnetic core in one of its two remanence states magnetized or due to the opposing action of the coincident pulses such a reversal of magnetization is prevented. A subsequent interrogation pulse magnetizes the core, if it was previously remagnetized, back to the original one Retentive state back, with a read signal then being emitted.

If the read signals of such operated linking elements as Variables to be processed further are to be fed to downstream cores, special measures must be taken to ensure a temporal coincidence of such Read signals with the other signals that also determine the writing process to ensure.

In the event that all cores are written in from a central pulse source can be delivered according to a known solution (Steinbuch, Taschenbuch der Nachrichtenverarbeitung, 1967 edition, page 428) this difficulty avoid the write pulses basically shorter than that shortest of the expected read pulses can be made.

It has also already been proposed (PA 9/420/4710) for a circuit arrangement for processing binary variables, in which the logic elements of the same type NOR elements are not to deliver the write-in pulses from a central point, but by means of blocks controlled by the read signals of these logic elements the same conception, whose signal signals represent the writing impulses and the through corresponding reduction in the number of turns of the read and drive windings have desired short duration. In the case of links inscribed in this way thus the write-in impulses for the logical connection with, whereby a Simplification of the wiring results, since with such logic elements the write winding is identical to a control winding. In addition, this type of control has the advantage that not always all cores, which do not influence them in the blocking direction variables to be processed are supplied, are written, so that a total of less energy is required for the central delivery of query pulses is, which leads to a saving of interrogation pulse amplifiers.

The invention now provides a circuit arrangement in on the one hand also the temporal coincidence of when the individual is registered Linking elements involved impulses is ensured, and the other hand the advantages of using building blocks in the proposed solution mentioned for the decentralized generation of writing impulses, also has, However, such additional modules are not required for this purpose.

The invention accordingly relates to a formwork arrangement for processing binary variable, which consists of similar logic elements, which each constructed using a magnetic core with a rectangular hysteresis loop are the one when the link condition is filled during a write-in process in one of its two retentive states and during the subsequent query process through an interrogation pulse back to the original other remanence state is magnetized, emitting a read signal. This circuit arrangement is according to the invention characterized in that interrogation pulses are shorter in time Duration are supplied that the then magnetization in the saturation range corresponding remanence state is initially not achieved, but by itself auxiliary pulse of such a small amplitude directly following the interrogation pulse it is set that the read pulses linked to this for magnetization reversal downstream cores are not sufficient.

As will be explained further below, according to the invention made shortening of the interrogation pulses compared to known circuit arrangements, in which the interrogation pulses remagnetize the magnetic cores to saturation, the advantage that the length of the read pulse used for further processing is independent of tolerances of the components, of the temperature, of the wiring length and on the number of downstream devices controlled by the read signal of a core Kernels is. As a result, however, read signals can also be sent to the Inscription of downstream cores and thus as a contributing variable to the link use without the coincidence with read signals of other cores which may be have to influence the core in the opposite direction of magnetization, in Question is asked.

An exclusive-OR element, a bistable multivibrator, a frequency divider and a binary counter are specified as exemplary embodiments of the circuit arrangement according to the invention.

The structure and mode of operation of exemplary embodiments are described below the circuit arrangement according to the invention explained in more detail with reference to 10 figures.

Fig. 1 shows an example of one of the logic elements from which the circuit arrangement according to the invention is composed.

Fig. 2 shows the symbolic representation for such a link, which is also used to illustrate the individual exemplary embodiments.

Fig. 3 shows the hysteresis loop used for the gates Cores.

FIGS. 4 to 7 show exemplary embodiments of the circuit arrangements for processing binary variables according to the invention, namely FIG. 4 is an exclusive OR gate, FIG. 5 a bistable multivibrator, FIG. 6 a frequency divider and FIG. 7 shows a binary counter.

The logic element shown in FIG. 1 is a NOR element. It contains a magnetic core M, which has a rectangular hysteresis loop should have, and that by a vertical, strongly drawn line is symbolized. This magnetic core carries a series of windings, which are created by short, the line symbolizing the magnetic core indicated under 450 intersecting lines are. By inclining these lines to the right or left, the different one becomes Twist sense Windings indicated. The lines intersecting the core horizontally indicate the supply lines of the individual windings.

The magnetic core M carries an interrogation winding n1, one wound in opposite directions Reading winding n2, to which the diode D is connected, also one for the query winding write winding n3 wound in opposite directions and a number of Xogi windings n4, the direction of which is in turn opposite to that of the write winding n3. the The number of turns of the reading winding is selected so that the read pulses emitted are at least have the same amplitude as the write pulses. This creates the NOR link comes about that a writing of the core and thus the delivery of a read signal in the subsequent query is only possible if none of the logic windings a variable with the binary value t'1 is supplied. The diode blocks the circuit the reading winding n2 when writing and suppresses interference currents up to the size of theirs Threshold that is induced when variables are fed to the logic windings will.

In FIG. 2, the logic element according to FIG. 1 is simplified Symbolism shown. The magnetic core M is here again by a vertical strongly drawn line illustrated. The top of this line is that positive remanence state of the magnetic core + Br or the binary value ttlN and the lower one The end is the negative remanence state of the nucleus -Br or

the binary value "O" is assigned, the core windings are in the form here represented by arrows. The query winding nl, the write winding n3 and the windings n4 to which variables to be processed are fed, i.e. all windings are supplied via the pulses that contribute to the magnetization of the core, run at this representation in the direction of the magnetic core symbolizing line. Depending on whether they influence the magnetic core Pulses a magnetization in the direction of the remanence state + Br or the remanence state -ßr cause the arrowhead is pointing up or down. The arrow, which should represent the reading winding, via which only impulses are emitted, points away from the core bar since the interrogation pulses are delivered from a central point and are constantly present are next to the arrow symbolizing the query winding no leads drawn, and this arrow is filled in, which means that it is special large pulse amplitude of the interrogation pulses is indicated. From the location of the arrows with regard to the center of the core, marked by a small horizontal line the temporal position of the windings supplied or given off Recognize impulses. So you can see that the interrogation pulses and those linked to them Reading pulses on the one hand and the writing pulses and the variables to be linked on the other hand occur during different time periods.

With reference to Fig. 3, which shows a bysteresis loop, how the magnetic cores the logic elements used to build the circuit arrangement according to the invention according to FIG. 1 and FIG. 2, that of the circuit arrangement according to the invention underlying operating mode explained in more detail. When the magnetic core of a linking link the circuit arrangement according to the invention has been written in, is located this in the positive remanence state + Br. An interrogation pulse that is then supplied magnetizes the magnetic core again in the direction of the negative saturation state -Bs out. In contrast to known arrangements, however, according to the invention Regulation the duration of the interrogation pulse so short that that of a magnetization Corresponding remanence state -Br in the saturation range is initially not reached will. This means that the interrogation pulse has already ended before the steep one left part of the hysteresis loop has been run through. It then arises, for example the remanence state Bx shown in FIG. 5, although the interrogation pulse has such a large amplitude that the magnetic core is severely overdriven. The magnetic core then acts in a first approximation like a transformer, so that with The interrogation impulses linked to impulses from the core properties and the output load of the core are independent and have substantially the same duration as the interrogation pulses exhibit. Reading pulses that are delivered by different cores can therefore can be easily linked by influencing another core, without special measures taken to ensure their temporal coincidence Need to become.

As FIG. 3 shows, there is a magnetic core after the query with shortened query pulses in an undefined remanence state Bx. The next Interrogation pulse would therefore tn the second read signal, albeit of a lower amplitude deliver. So that the cores are again in a unique Rem + --- are state, is therefore according to a further feature of the invention Magnetic core is supplied with an auxiliary pulse immediately after r'e'1t'e'n the interrogation pulse, which moves the magnetic core beyond the steep part of the hysteresis loop drives. After the auxiliary impulse has subsided, the will definitely arise negative remanence state -Br a. However, the amplitude of this auxiliary pulse is on the other hand kept so small, that those with this auxiliary pulse linked read pulses for remagnetization of downstream magnetic cores are not suffice, so also not in an erroneous way the presence of a useful pulse can pretend.

As an embodiment of the circuit arrangement according to the invention an exclusive OR circuit is first described with reference to FIG. The circuit arrangement 4 contains two logic elements with the magnetic cores E1 and E2, which can be queried at the same time. The reading windings ni4 and n24 of these magnetic cores are connected in parallel and thus both contribute to the delivery of result variables at. The input variable el influences the magnetic core El via a write-in winding n13 in the writing direction and the magnetic core E2 via a blocking winding n24, the is connected in series with the winding n13 of the core Ei, opposite to the writing direction.

In contrast, the input variable e2 influences the magnetic core Ei via the Blocking winding n14 against the writing direction and the magnetic core E2 via the Write-in winding n23 in write-in direction-. Each of the two magnetic cores El and E2 is therefore from one input variable in the writing direction and from the other Input variables influenced in the blocking direction. If these, input variables such as explained above by querying other magnetic cores not shown here no further measures need to be provided for their temporal coincidence when acting on the two magnetic cores.

The circuit arrangement according to FIG. 4 only then provides an output signal if only one and only one of the input variables takes the binary value 4. Namely, only in these two cases does the inscription become one of the two cores El and E2 through one of the two input variables el and e2 due to the blocking Effect of the other input variables is not prevented. One of both Pips then there a read signal to the common output a. if on the other hand, both input variables assume the binary value "1", as a result of the blocking Effect of an input variable prevents writing or if both input variables assume the binary value "O", there will be none due to the lack of a write-in excitation of the two cores.

In both of the last-mentioned cases, there is no query Magnetization of the cores and thus no read pulse is emitted.

5 shows an embodiment of the circuit arrangement according to the invention in the form of a bistable flip-flop with a dynamic input, that is, such a flip-flop described, the-on each input signal at one and the same input in each case is switched from one stable state to the other stable state. the The circuit arrangement according to FIG. 5 contains an exclusive OR circuit with the magnetic cores E and A, as shown in Fig. 4, and another link with the magnetic core R is connected downstream. The magnetic cores E and A of the circuit arrangement become a first interrogation clock phase, the magnetic core R, however, becomes a second query clock phase queried what by the different location of the Query windings symbolizing arrows for the magnetic cores E and A on the one hand and in the case of the magnetic core R, on the other hand, is indicated. The from the magnetic cores E and A read signals supplied via the read windings nt2 and n22 influence the magnetic core R via its write-in windings nR3 in the write-in direction. That about the reading winding nR2 output read signal of the core R represents the one input variable of the by the Cores E and A formed exclusive-OR gate, so it influences the magnetic core A2 over the write-in winding n23 in the write-in direction and the magnetic core E over the winding n14 in reverse direction. The switching of this circuit arrangement The effecting input variable el acts on the magnetic core E. in writing direction and on the magnetic core A in the reverse direction. Both the ~ read signals of the cores E and A as well as the read signal of the core R3 can be used.

In one of the two stable states of the circuit arrangement if none of the Xernes is registered, the interrogation pulses are also alsci no read signals issued. The input variable el now becomes the magnetic core E, this core gives a write-in pulse when it is queried on the core R, which on the other hand inscribes the magnetic core A when it is queried. at Magnetic cores A and R alternately write and enter further inquiries accordingly alternately read signals. This second stable state of Circuit arrangement is maintained until an input signal el again occurs. However, the core E can now not be inscribed because it is from the core R is blocked. On the other hand, the core A is blocked and accordingly also gives no more writing pulse to the core R from. However, all 3 cores remain in the non-registered state, until the next occurrence of an input pulse the cycle repeats.

A tilting stage of the aforementioned type could also be used per se can be constructed from only two magnetic cores queried at different clock phases, one of which supplies the writing excitement for the other.

However, due to such feedback, it could already occur of minor, for example temperature-related disturbances lead to the fact that the flip-flop is switched to the stable state in which both magnetic cores are alternately written in and read out.

6 shows an exemplary embodiment of the circuit arrangement according to the invention in the form of a four-stage Frequency divider. His second through fourth Step S2 to S4 are formed by bistable multivibrators, as shown in FIG. 5 have been described. The interrogation of the cores of these levels is done as follows, that cores of the same order of successive stages to the other clock phase be queried. If, for example, the cores E2 and A2 are queried for the first clock phase and the core R2 for the second clock phase in the following stage S3, the cores E3 and A3 for the second clock phase and the Interrogated core R3 for the first clock phase. The cores of the following level 54 become then again.jewells at the same clock phase as the co-ordinated cores of the stage S2 queried. The reading windings of those cores of the stages that are necessary for inscription The input winding serving for the purpose of writing is always matched with the one serving for the registered mail Input winding of the corresponding core of the next following.

Level, as well as with the interrogated to lock the at the same clock phase Core serving input winding connected. So this is the reading winding of the core E2 of stage S2 with the input winding of the core E3 which is used for writing and connected to the locking ring winding of the core A3 of the stage S3. The same applies to the connection of the reading winding of the core E3 of the stage S3 with the input windings of stages E4 or A4 of stage S4. At the steps S2 and S3 supply the read signals of the cores E2 and E4 and the output signal at the same time the stage. For stage S3, whose core ED, as explained, to a different clock phase how the cores E2 and E4 is queried is for the clock conversion of the output signal An auxiliary core H3 is also provided, which is written by the read signal from the core E3 and is queried at the same time with the cores E2 and E4.

The three bistable flip-flops S2 to S4 have a pulse reducer upstream, to which the input pulses are fed and which every second input pulse suppressed. This pulse reducer stage contains three magnetic cores El, Al and lii. The input pulses are fed to the core E1 in the writing direction. This core is queried for the first cycle phase. Its read signal excites the core Al of this reduction stage, which is queried for the second clock phase is also in the writing direction Das This signal of this core Al writes the third core L1 of the reduction stage as well the core E2 of the first bistable multivibrator of the frequency divider. The read signal of the core L1 of the reduction stage blocking core Al and at the same time represents the The output signal of this frequency divider stage.

If initially none of the cores El, Al and L1 of the reduction stage S1 is written, a first input pulse at input F initially the core El is registered, which is also the registered letter in subsequent query cycles of the cores A1 and L1 and the output of a broom signal at output F / 2. By interrogating the core L1, however, the core A1 is blocked, so that the occurrence of a second pulse at the input F only the core El is written and accordingly no output signal is emitted via output F / 2. Since now the core Al is no longer blocked, a third pulse at input F has again the writing of all three cores and the delivery of an output signal result.

The read signal of the nucleus Al, which also only applies to every second Input pulse is emitted, but occurs in the second interrogation cycle phase, is fed to core E2 of stage 52 as a write-in signal. This works in the manner described with reference to FIG. 5, thus leads to a further pulse reduction in a ratio of 1 to 2, so that at output P / 4 supplied by it only every fourth Pulse towards an output signal is emitted. The same applies to the further reduction through the stages S3 and S4, at their outputs F / 8 and? / 16 on every eighth input pulse or output signals are emitted on every 16th input pulse.

In Fig. 6, the two cores Mi and M2 are shown, the be queried at different clock phases and apart from the query windings only carry one reading winding at a time. The reading winding of the core M1 is with a blocking winding of the core R3 of stage S3 and the read winding of the core M2 is each with a blocking winding of the cores R4 and R2 of the stages S4 and S2 connected, Since the cores M1 and M2 do not receive any write excitation, they only give Signals of low amplitude from those of the respective magnetization from the negative remanence state these nuclei correspond to the negative saturation state. By the aforementioned Feeding as blocking signals to the cores of the bistable multivibrators labeled R it is ensured that the respective feedback of the cores A2 and R2, A3 and R3 as well as A4 and R4 do not become an unwanted one in the event of temperature-related malfunctions Switching these flip-flops leads.

In Fig. 7 is another embodiment of the invention Posture arrangement shown in the form of a three-stage binary counter. The steps of this counter are the same and contain three magnetic cores of which the first two, e.g. cores Gi and A1 at level S1, to a first clock phase and the third e.g. N1 can be queried at a second clock phase.

The read signals of these first two cores G1 and Al are effective as blocking signals for the third core N1.

The read signal of the third core N1 magnetizes the first core G1 in the writing direction and the second core Al in the blocking direction. The second core Al and the third core N1 are each supplied by a central write pulse source inscribed what by drawn in the relevant halves of the core bar Arrows without feed lines is symbolized.

The read signal of the third core N1 becomes the first cores G2 and G3 of the stages S2 and S3 as well as a but magnetic core Ü each as a blocking signal fed.

Transfer magnet core Ü, which is also from a central write-in pulse source written to a first clock phase is queried, magnetized with his Read signal of all third cores N1 to N3 of the stages S1 to S3 in the writing direction.

A second clock phase is used to record the counting pulses queried magnetic core Z, which is counter to the writing direction by the counting pulses is magnetized and its read signal all first cores G1 to G3 of the stages of the counter and the transfer core 2 magnetized against the Einohreibrichtung.

As long as the described counter is 0, give all cores of the stages marked with N a read signal for the second interrogation clock phase that blocks the A-labeled cores of the same level. These cores Al bis A3, the reading windings of which form the outputs al to a3 of the stages, so give in the successor does not receive a read signal. The same applies to the cores G1 to (3,3, since they - are blocked by impulses from the nucleus.

The occurrence of a count has the locking of the core Z to As a result, when it is queried, there is no blocking pulse to the cores G1 and the transfer core 2 releases. It is therefore the core G1 by the read signal of the Core N1 is written in, cores G2 and G), however, are still blocked namely by the read signal of the core N1 or N2. In the following query of the core G1, the core N1 is blocked so that it does not have a read signal when it is queried can give more.

The consequence of this is that when it is queried, there is no longer a blocking signal the core Äl is released and this is written in by the central write-in pulse and emits an output signal when it is queried via the output al, with which the second counter status is set.

When a second counting pulse occurs, the one from the core drops again Z supplied blocking excitation for the cores G1 to G3 gone. However, it just becomes the core G2 is written by the core N2, since the core N1 also has no blocking excitation supplies to the register winding of core G2. The cores G1 and (33, however, are not inscribed, the reason why the core G1 is not, because the nucleus N1 does not have any inscribing excitation supplies, the core G3 does not, because the write-in excitation supplied by the core N3 is compensated by the blocking excitation supplied by the core N2.

When it is queried bs the core G2 from a read signal that together with the central write-in pulse counteracts the nucleus N1 of the previous stage the blocking excitation supplied by the core Al inscribes, so that the stage S1 at subsequent interrogation cycle again in the state corresponding to the binary value "O" is moved.

The read pulse of the core G2 blocks the other hand core N2, whereupon according to the processes geschilder.ten in connection with level S1 the core A2 is written and when it is queried via the output a2 Emits output signal. This sets the third counter status.

The occurrence of a third counting pulse and thus the elimination of the Blocking excitation supplied by core Z for cores G1 to G3 has the registered letter of the core G1. The core G2 cannot be enrolled because it is dated Core N1 is only supplied with a blocking excitation and the core G3 cannot be registered because the writing excitation supplied by the core N3 comes from the read signal of the core N1 is compensated. The one released by the core G1 in the subsequent query Read signal blocks the core N1 of this stage, so that this in turn at his Query no longer emits read signal and thus the writing of the core Al Level S1 no longer prevented. So now both via the output al as output a2 output signals, with which the fourth counter state is set is.

From the steps explained above, it follows that the with G can only be enrolled if the cores before the level to which they belong, the set state, i.e. that of the binary State appropriate and that they then. on the one hand, setting your own Stage and, on the other hand, the deletion of the previous stage, i.e. its switchover in the state corresponding to the binary "O".

According to this principle, the counts when further counting pulses occur described binary counter up to an eighth count position, -from which he through the read signal of the Kernes Ü, which occurs after the occurrence of the eighth The counting pulse was initially entered during the entire counting process, is reset to the counter state 0 again in the cases described above Embodiments of the circuit arrangement according to the invention were the individual Linking elements of at least one of the variables to be processed in the blocking direction influenced.

The advantages that are caused by the query according to the invention, naturally occur even if the variables to be processed are also in Direction of writing influence the cores of the logic elements and when they meet with a write-in pulse or

with another variable acting in the writing direction, the magnetization reversal of the core during the enrollment phase.

1 fl 't, n <8 ç ilehe 7 figures

Claims (7)

Patent claims 1. Circuit arrangement for processing binary Variable, which consists of similar logic elements, which are each under Use a magnetic core with a rectangular hysteresis loop, when the link condition is met during. of a writing process in the one of its two retentive states and during the subsequent query process by an interrogation pulse back to the original other remanence state is magnetized, whereby it emits a read signal, d u r c h g e -k e n n z e i c h n e t that interrogation pulses are supplied with such a short duration, that thereupon the remanence state corresponding to a magnetization in the saturation range initially not achieved but by a directly following the interrogation pulse Auxiliary pulse is set so small amplitude that the associated with this These impulses are not sufficient to remagnetize downstream cores (Fig. 4 to 7). 2. Circuit arrangement according to claim 1 for linking two binary More variable in the form of an exclusive OR function, which means that it is not possible to use it c h n e t that it consists of two logic elements, whose magnetic cores (El, E2) are queried at the same time and their read windings (nu2, n22) both for Delivery of the result variable (a), and that both input variables (ei, e2) the one magnetic core via separate windings (n13, n14, n23, n24) magnetize in the direction of insertion and the other magnetic core in the opposite direction, for which purpose they are supplied in such a way that their effects on one and the same core are directed in the opposite direction (Fig. 4). 3. Circuit arrangement according to claim 2, d> -a d u r c h g e k e It is not indicated that its output (a) stimulates a third person to write in Magnetic core (R) supplies, which is queried for another clock phase and its read winding (nR2) supplies the input variables for one of its inputs (e2), so that it works as a bistable multivibrator, which is switched by the other Input (ei) supplied switching variable is effected (Fig. 5). 4. Circuit arrangement according to claim 3, d a d u r c h g e k e n n notices that they are part of a chain of the same type forming a frequency divider Stages (S2 to S4) is where sibling cores of successive stages are queried for the other clock phase and for each of the reading winding of the core (E2, E3, E4) carrying the input winding of a stage with the input winding of the following stage is connected and in those of these cores (E2, E4), the are queried for the first clock phase, including the output signal (F / 4, F / 16) of the stage outputs, with those of these cores (E3), however, those queried for the second query cycle phase the write excitation for an auxiliary core assigned to the same stage (S3) (H3) which is queried for the first clock phase and its read winding the output signal of the stage in question is emitted, and the first frequency divider stage (S2) a pulse scaler stage (S1) for suppressing every second input pulse is connected upstream (Fig. 6). 5. Circuit arrangement according to claim 4, d a d u r c h g e k e n n shows that the pulse reducer stage (S1) has three magnetic cores (El, Al, L1) contains, of which the first (egg), which the to be squat Pulses (F) are fed, and the second (Al), which is the input signal for the first stage (S2) of the chain releases the subsequent core (Al, L1) in the writing direction magnetize, and the third (L1), whose read signal is also the output signal (F / 2) represents the stage, the previous second core (Al) in opposite Direction magnetized and that the first (El) and the third core (L1) to the first Clock phase are queried, the second core (A1), however, queried for the second clock phase will. 6. Circuit arrangement according to claim 4 or 5, d a -d u r c h g e It is not indicated that two additional compensation cores (M1, M2) are provided are, to which only interrogation pulses are fed to different clock phases, and the compensation pulses via their reading windings with each query deliver to such third cores (R2, R3, R4) of frequency divider stages (S2 to S4), which are queried for the other clock phase that these cores are contrary to the Writing direction are excited (Fig. 6). 7. Circuit arrangement according to claim 4 and 5, in the form of an n-stage Binary counter, d a d u r c h e -k e n n n z e i c h n e t - that they are the same among themselves Levels each consist of three magnetic cores (G, A, N), the first two of which ((3, A) to a first clock phase and the third (N) to a second clock phase are queried, of which the first two (G, A) with their read signals the magnetize the third in the opposite direction to the writing direction and the third (A) with his read signal the first (G) in the direction of writing magnetized, and of which the second (A) and. third (N) each from a separate central write-in pulse source that 4from the read signal of the third kernel (N) of the stages the first kernels (G) of all subsequent stages as well a transfer magnet core (Ü) interrogated for the first clock phase against the writing direction magnetizes that the read signal of the first cores (G) of the stages the first cores (G) all the preceding stages magnetized in the writing direction that the read signal of the transfer magnet core (Ü) all third cores (N) of the stages in the writing direction magnetized, and that to receive the counting pulses a phase queried for the second clock Magnetic core (Z) is used, which is magnetized by the counting pulses against the writing direction is and its read signal all first cores (G) of the stages of the counter as well as the The transfer magnet core (Ü) is magnetized against the direction of writing. (Fig. 7).