DE1938789A1 - Electronic delay line with adjustable delay - Google Patents

Description

Presearoli Incorporated ....- "..- Silver Spring, Md., V.St.A * 3 0, JULY 19SS

Electronic delay line with adjustable ■ considerable delay

The invention relates to an electronic delay ·! · line with adjustable delay.

In many electronic systems it is desirable to a device for introducing a delay in the Provide propagation of signals through the circuits, these delays often being adjustable have to. Numerous arrangements have already been created to produce adjustable delays, of which the delay line with over its length

taps provided may be the best '· "■■■ is known / arrangement. With such an arrangement, however, a manual switch from tap to tap is usually necessary and will only be a gradual change in delay rather than a continuous change evenly changing delay achieved.

Attempts have also been made to etie Delay of a line of the above described Type to continuously 'change electronically' These attempts consisted in changing one or both resistance elements (L and G) of the line, Jm the first case called the change of one cons *

1938783

elements based on mismatch in the line Difficulties emerged, which also made a "change in the power sources" and load resistances necessary. If, on the other hand, both resistance elements are adjusted, difficulties arise with regard to the phase shift. Tracking problems on ^ As a result, the electronically adjustable delay lines with taps provided over their length practical application inevitably fundamental advice dernis.se against »

The invention overcomes the disadvantages of the known arrangements by enabling continuously variable delays with constant amplitude and linear phase properties over a large bandwidth such a range variably constructed _s that the entire circuit to the signal issued a SSiasenverschiebung that _{t has} a value of about 12 ° does not exceed being possible within this Bereiohs eina small ₉ continuously variable delay · Wen "However, all a greater signal delay at a certain Anwendiangsf erforder * is lent, a number of these circuits will be so that their individual delays add in cascade ·· circuit sngeordnet _f and share the desired Sesamt-

In the following, the invention is in a preferred aspect management example explained in more detail using the drawing » Ss seigern. '^, ._. - ■■ ■ -. -:

1938799

Fig. 1 is a schematic diagram of a conventional one Delay line with along its length « provided taps,,

Fig. 2 is a schematic circuit diagram of a fundamental cnen delay line circuit with the mark « basking the invention and

Fig. 3 is a schematic diagram of a preferred one Embodiment of the invention with delay circuits arranged in a cascade circuit *

Before explaining the details of the invention is in the following the most common conventional one with reference to FIG Arrangement in more detail, described. To with such a Delay line to achieve different delays are at the junction points between the Inductors taps provided »Bas toggle from one tap to the other, however, is a mechanical one Process through which only gradual delay, changes are achieved

Bs siBd already been attempts to modify the S © hai "tung gesiäS Figure _e 1 to form a delay line with continuously adjustable delay by trying to make the inductors and / or the capacity electronically adjustable * These changes throw However, the following Schwierigkeitext on.

In the circuit of Figure 1 _e is the time delay of the number of sections of the delay line and

909836/1151

proportional to the square root of the product of L and C, while the characteristic impedance of the overall network is proportional to the square root of the ratio of L and G. To achieve useful time delays with constant "amplitude and linear phase properties over a desired frequency band, it must Network ■ must be precisely matched so that the change in one of the resistance elements (L or C) is both an adjustment of the current source and the load resistance Rg or Β-, makes necessary · the proper implementation of this Adjustment is a difficult undertaking · If ü both resistance elements (L and C) are varied, the result is a serious problem with the phase shift due to the square root ratio lake, which determines the time delay of the circuit

Having described the disadvantages of conventional arrangements, the invention will now be explained in more detail. Fig. 2 illustrates a basic circuit for achieving a time delay. This circuit consists of a phase-reversing transformer T with a number of turns ratio of secondary to primary winding of 2iT and with a secondary winding center tap.In this context, it is assumed that the impedance of the transformer secondary winding is essentially smaller than the impedance of an ohmic resistance R and a capacitive resistor C connected in series across the secondary winding of the phase-reversing transformer. As a result of this circuit, each half of the secondary oscillation can be regarded as a voltage source, and with an input of sin φ, one half of the secondary delivers'!

909886711S1

1936789

winding the signal sin «# and the other half the signal -sin <yto The resulting output signal is the vector sum of the two secondary signals j-

Assuming that e _{Q1 represents} the vector sin #t and the vector -sin u? T, then is

01

sin ujt,

with S = j ω (where j = output frequency is).

ω the one

The separation of the vector components gives

'01

sina; t.

Likewise is

02

02

Ic S. 1
MyniMmjiui » sin njt or * R. R = SG 12 "5 ™ · R ² ■■■ ■. ι S ² ^ G ²

sin (0t

- • ■ »■ 6 *»

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1933799

The output e ~ results from the Yectox sum

E ² -

2H SC

, Z "2 - ~

sin

It is the size of the resultant

¹ O

a in

R ² T ^

G ² "^

1/2

sin at

1 ⁺ , "XT"

R ² +

U ² G ² J

a

However, a very useful property of the size of the output is that it is equal to the size of the input and is not a function of R, C or U3 .

The phase angle of the output is

Jl - tg

-1

2R

T.

3-5-

-2

-T

-7-

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1939789

Sa the tangent function is very linear at small angles and calibrate below J ^ degrees by less than 1 # changes, this circuit provides a very precise time delay «! for all values of Oi j which phase angles of or smaller than 2 χ «or ^ (about 12 °).

For the above calculations to be valid, the impedance the output load can be significantly greater than the impedances of R or C.

The circuit arrangement of FIG. 3 provides a practical one Example of an electronic delay line based on the principles of the invention with adjustable Delay, with details of the circuit supplying the bias voltage for the sake of illustration are omitted. In this preferred embodiment, the phase inverters consist of transistors TS-1, TR-2 bia TR-η. across each transistor are an ohmic Resistor R and a capacitor C connected in series. The output of each stage is from the branch between R and C removed and applied to the base of the phase inverter associated with the next stage. To this In this way, a cascade arrangement is formed in which the time delays of the individual stages change add. The total time delay (t ^) of the circuit isti

tg ejRC,

■■■: · α w

where η is the total number of stages. The delayed one. The output at stage η is connected to the output terminals of the circuit via a conventional emitter follower circuit guided.

909886/1151

The time delay within the circuit arrangement can be changed electronically by changing the value of E or C to adjust. In the preferred embodiment H adjustable as it has been shown that the use of photosensitive resistors such as eadmium sulphite photocells or other photosensitive devices, one practically independent of the signal to be delayed Adjustment of the delay practically allows. The resistances of the photocells can be adjusted by means of lamps whose light intensity can be regulated by a separate voltage and current source, which in turn depending on the state to be monitored einstellbajr_ist. For example, if a sensor detects ^, that one from the delay line to an associated The signal applied to the controlled system is to be delayed to a greater or lesser extent, a corresponding * corresponding control voltage to change the intensity of the lamp is generated, which in turn adjusts the resistance of the photocells while changing the delay characteristic the circuit causes.

Although the embodiment according to Figure 3 in connection with resistances varied electronically by light is described, of course, voltage-dependent resistors or capacitors can also be influenced and can be any other parameter such as Heat, light, pressure, etc., to produce the positioning. function to change the value of the resistances or con-

ι CL * L 6

capacitors are used. In addition, need in the Delay line applied reactance elements to not be capacitors, but instead can be inductors be. In such a pail it goes without saying

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the above formulas modified in the same way that they make the contribution of the inductors to the impedance of the circuit part of the contribution of Capacitors reproduced "

The above description relates to a preferred embodiment of an electronic ¹ IV delay circuit which enables a uniform automatic adjustment of the delay characteristic over a wider frequency range. However, it will be apparent to those skilled in the art that certain modifications can be made within the scope of the invention. For example, both the real and the complex resistance element can be varied and, instead of the switching elements shown in FIGS. 2 and 3, other phase reversing elements, such as vacuum tubes and field effect transistors, can be used. The variable electronic elements can be set either manually or automatically. All these changes and modifications should of course be included in the extended scope of protection.

In summary, the invention therefore creates a delay line with continuously changeable delay, which is caused by a real and a complex cons « Stand element is formed, which via a phase reversal «· member, like a transistor, are connected. At least one of these resistance elements is in an area variable, at which the phase shift impressed on the signal generated by the circuit has a value

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of about 12 does not exceed · To enlarge the Delays beyond the range that can be achieved with a single delay line element can be several these circuits can be cascaded.

-11-

909 * 86/1111

Claims (8)

Claims Electronic delay line with adjustable delay) characterized by a basic circuit with a real and a complex resistance element, which are connected in series via a phase reversal element are and of which at least one resistance element for the purpose of changing the delay characteristic the delay line is adjustable, it being the phase shift of the delay line passing signals are limited to less than about 12 °. 2. Delay line according to claim 1, characterized in that that the phase reversing element is a transformer with a secondary winding provided with a center tap is and that the real and the complex resistance element across the secondary winding in series are switched. 3. delay line according to claim 1 »characterized in that that the phase inverter is a transistor and that the real and the complex. Resistance element are connected in series across the emitter and collector of the transistor. 4. delay line according to claim 1, 2 or 3t thereby characterized in that the resistive element is a photosensitive device. 909886/1 1B1 5. Delay line according to one of claims 1 to 4, characterized in that the complex resistance element is an inductance. 6. Delay line according to one of claims 1 to 4t characterized in that the complex resistance element is a capacitor. 7. Delay line according to one of the preceding claims, characterized in that for the purpose of enlargement the total delay of the delay line several basic circuits in cascade connection are arranged, with each of a basic circuit at the junction between the real and output signals taken from the complex resistance element as input signals to the phase inverter the next basic circuit of the cascade can be created » 8. delay line according to claim 2 and 7, characterized characterized in that the one basic circuit at the junction between the real and the complex resistance element and at the center tap output signals taken from the secondary winding as input signals to the primary winding winding of the transformer of the next basic circuit. 9β delay line according to claim 3 and 7, characterized characterized in that the one basic circuit at the junction between the real and the complex resistance element taken from the output • -13- 9 0 9 8 8 6/1161 signals are each applied as input signals <to the base of the transistor of the next basic circuit. The delay line of claim 7, 8 or 9, characterized in that the real resistance element of each basic circuit iat a photosensitive device _e 909886/1151 Blank page