DE1935356C - Circuit arrangement in ECL technology for forming the transmission signal in a full adder - Google Patents

Description

to indicate the carrying signal in a full adder, which is a! Supplement to the arrangement already proposed for the formation of the sum and otherwise fulfills the same conditions. When using the series coupling, this should be limited to two-stage arrangements for reasons of tolerance ^ The circuit arrangement according to the invention is characterized by a first logical subcircuit, built in series coupling from two emitter-coupled current switches χα, for ANDing the signal α and corresponding to the first summand of the (incoming) carry signal c _b formed by the addition of the next lowest binary digits by a second, essentially identically constructed sub-circuit consisting of two emitter-coupled busbars, one of which is controlled by the signal b corresponding to the second summand and the other by the parallel connection of an additional tran - ao sistors to the directly driven transistor to form an OR link between the signal α and the incoming carry signal r, is expanded, through the connections of the outputs of the subcircuits each with the base of an emitterfo lger, 5 switched transistor and through the connections of the emitters of these transistors with a common emitter resistor and the output terminal for the over-

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Execution shown in the drawing. Example of the invention "consists of two almost identical parts. One circuit part contains one Lten emitter-coupled current switch with the transistors T1 and 72, whose emitters are common

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ssiii. ϊϊΞο ^ £ rpotential-t / v2. The base of the transistor Tl is directly controlled for the first summand appropriate, the same signal is connected via a resistor α-transistor network for shifting the potential of the control signal by about 1.2 V to the input terminal ". In the exemplary embodiment, this network consists of a series connection of three resistors R 2, R 3, R 4 between the input terminal α and the negative supply potential - Ub and of the transistor 74, the collector of which is connected to the input terminal a and the base of which is connected to the connection point of the resistors R. 2 and R 3 and its emitter at the connection point of the resistors R 3 and R 4 and also at the base of the downstream Trans, - ^St ^ K ² oi ⁿ eSkreis of the directly controlled transistor 72 of the first current switch is a second current switch with the transistors 75 and 76 inserted, which is controlled by the carry signal c formed from the addition of the next lowest binary digits. The collectors of the indirectly driven transistors 71, 75 of the two current switches are with the base of one as an emitter follower

terminal realized. Cphaltunos arrangement too

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1 sheet of drawings

Claims (1)

controlled transistors be connected in parallel. Claim: As it relates to the operation of the differential amplifier in the present case, a pure switch operation Circuit arrangement in ECL technology for BiI- acts in which the constant current source tion of the carry signal in a full adder 5 is supplied by one of the two tranmit short running time, characterized by sistors, should be taken over by a a first, in a manner known per se, can be spoken of two emitter-coupled current switches, emitter-coupled current switches (Tl to Γ6) in The second possibility to reduce the Si Logical subcircuit built up in series coupling gnallaufzeit over a complex logic network for ANDing the first summanio is the saving of the corresponding signal α connected in series and the OR elements formed by the logic elements such as AND elements and addition of the next lower binary digits. This also includes the replacement of the (incoming) carry signal c "with real logic elements through wired associations of second, essentially identically structured logic element functions, which themselves do not contribute anything to the running subcircuit of two emitter-coupled current times. This is understood to mean the direct switches (Γ8 to Γ13) whose one (TS to TU) bare galvanic connection is suitably designed by the logic element outputs corresponding to the second summand is controlled to the further corresponding signal b and the other AND or OR operation of the Output by connecting an additional signal in parallel (cf. "Der Elektronikiker", March 1967, p. 87). Transistor (Γ15) for directly driven transit ao It is also under the name "Serienkoppsistor to form an OR of the lung" is known in the collector circuits of the Transisto signal α and of the incoming carry-ren an emitter-coupled current switch further signal c, is extended to insert emitter-coupled current switches through the connections ("The outputs of the subcircuits each with the Electronic Engineer", November 1967, pp. 56 to 60), the basis of a transit as an emitter follower, whereby the link value of the link ;, store < T7 or T 14) and through the connections member without substantial extension of the signal of the emitter of these transistors is increased with a running time. Additional logical linkage common emitter resistance and the output connections can be achieved if transistors belonging to the terminal (C ₀ ) for the different current _{switches in the circuit arrangement respond to a formed carry signal C 0} . 30 common collector resistance work. Use For example, a circuit arrangement is found in which only the collector circuit of the directly controlled th transistor of one power switch another Power switch is inserted, and connects the KoI- 35 readers of the indirectly controlled transistors of both Power switches with each other and with a common The invention relates to a circuit common collector resistor, as follows from the arrangement In ECL technology, an output signal, which is the AND carry signal, is used to form the connection point in a full adder with a short run linkage of the input signals (data time. 40 sheets MC 1019, 1219 from Motorola Semiconductor The Desire for an Increase in Labor Products Inc., November 1967 edition). speed in data processing and ahn- To equalize the potentials of the control signal Borrowed systems leads, among other things, to the conveyance for the "lower" power switch to the potentials After a short signal delay in the other input and output signals, it is see circuits. Known as the yardstick for the signal run 45, the basis of the directly controlled transit time Via a complex logical network, the stors is a resistor-transistor network for Po runtime via a simple OR-NOR gate. To be connected upstream for potential displacement. The potential reduction the total run time is generally slightly greater than that according to two options. The first option> voltage drop across a conductive base-emitter exists in the application of a circuit technology 50 diode and is, for example, about 1.2 V. with the lowest possible logic element running time. Digital circuits are currently becoming more and more For this purpose, the ECL circuit technology (emitter-coupled - more than integrated components. In addition to the pelte logic), in which the control of the requirement for a short signal run time result Transistors in the saturation area is avoided. from this the demands for easier integrating that The basic element of ECL technology is an emitter capability, as few terminals and as possible coupled differential amplifier with two transi- low power consumption of the components. The Fordestoren, whose emitter together at a source tion after a few terminals means that (approximately) constant current. The basis of the signals to be linked only in one form of the two transistors, in the following the indirect. - normal or inverted - should be required, called controlled transistor, is connected to a fixed auxiliary 60 There has already been a circuit arrangement in potential placed, which is chosen so that it proposed the arith ECL technique (P 1 929 144.2), which the Metic mean from the two signal potentials of the function of the sum output of a full adder bi- met at the base of the other transistor and the aforementioned requirements are satisfied, forms nary control signal. The second transistor is The signal delay is only slightly longer than the Laufim The following is shown as a directly controlled transistor via a standard OR-NOR element of the ECL. To create an OR link technique. can the collector-emitter path of this transi- The invention is now based on the object interferes with the collector-emitter paths further direct a circuit arrangement for the formation of the over-