DE1806443C3 - Central command generator for time-dependent program-controlled functions in switching systems, especially in telephone systems - Google Patents

Description

Clock controlled counter elements are used.

In the course of development one has often passed over to the individual chronological elements centralized place, where they are then requested by the decentralized switching elements if necessary and, after the specified period of time has elapsed, the decentralized switching element is requested to execute the Control process to trigger now.

This principle of the central arrangement of timing elements is used in particular modern rental systems with memory-programmed Central control units, which now handle the entire functional sequence within a switching system control and monitor from a central point. For the timely introduction of the individual control programs these central control units and for monitoring time-dependent functional processes within the Switching systems are the central control units of such modern mulling systems with command givers equipped, the control clocks for the initiation of the individual programs and the time-dependent switching functions deliver. The heart of such a central command generator is a clock in the form of an off individual storage elements, e.g. B. magnetic cores, built-up time table, which is equal to a matrix in rows and Columns is divided, with the individual lines of this time table cyclically one after the other and periodically recurring are controlled depending on a basic cycle, while the individual columns of this time table are each assigned to a program. The individual storage elements within each program column indicate in each case whether the associated program should be started when the associated line is activated is or not. Depending on the number of markings per program column, the result is the periodic reading of the time table with control pulse sequences for starting the individual control programs different pulse frequency, which now, depending on the choice of programs, either control the ablaut of switching processes or as basic clocks for others Timing tables or other timing elements in the form of counter elements to measure larger times for Time-dependent, program-controlled functional processes that are not easily incorporated into the rigid cycle schedule the chronological tables are available.

To generate the control commands for such time-dependent program-controlled function sequences a separate memory section is permanently assigned to each of the time cycles generated by the time table, the Additional memory sections can be freely assigned via link addresses. This In addition to the locations for the link addresses, further memory sections also have an address location to identify the switching element that is after Is to be controlled expiry of the prescribed time period, or one associated with this switching element Memory section and a counting section, which in multiples of the controlling time cycle designated time span. So there are a total of so many memory sections with counting sections, so-called counting registers are to be provided as switching elements are to be monitored at the same time.

On the other hand, it is generally known in the case of devices which operate according to the time division multiplex principle, individual Storage locations or other facilities depending on a cyclically advanced sampling selector or sampling counter with a downstream decoder to be controlled or called up periodically.

The triggering of control functions after any times that can be specified is not provided here.

The present invention also relates to a central command generator for time-dependent program-controlled Functional processes in Vermiulanlagen, in particular telephone systems, with a Clock generator and with a memory to be queried by means of at least one counting register. Task of The invention is the effort for the generation of control pulses to trigger time-dependent functional sequences further reduce. This is achieved in that each stage of the counting register at least a section of the memory to be identified by the counting register is individually assigned, in the identification addresses of control commands that occur at any time and through the switching or Control functions should only be triggered after a specified period of time or the dimensions predetermined time segments should be initiated at the point in time at which the relevant control command accrues, are each written into a memory section of the memory that corresponds to that stage of the Counting register is assigned, which was activated at the time at which the relevant control command occurs Level of the counting register by one of the quotient of the specified time and the time of the Basic clock, with which the counting register is incremented, is followed by a corresponding number of stages.

According to the new solution, only a single counting register is required per time cycle, which is cyclical and is incremented periodically depending on the controlling time cycle. In order to nevertheless ensure that the, based on the counting register cycle, occurring at different times are time-dependent Control commands can also be processed in a timely manner, each level of the counting register is a separate one Permanently assigned memory section, which is analogous to the address sections of the individual counting registers in the known arrangement of the inclusion of the identification address of the switching element to be controlled or of this Switching element assigned memory section is used. By classifying the applicable tax address into a memory section of the counting register which is the desired time later in the frame of the normal counting register cycle is activated, it is also ensured that the Time span is adhered to almost exactly. On the other hand, this results in a very simple workflow for the command generator, since each activation of a The level of the counting register is synonymous with the timing of the one marked in this level Control commands. It does not matter how many simultaneously occurring control commands within one Level of the counting register are to be processed, as each memory section of the individual counting register levels Any number of additional memory sections can be assigned freely using link addresses can without each having their own counting section, which is synonymous with a own counting register. The spectrum of possible time spans is the same as in the known arrangement depending on the number of stages in the counting register; the same applies to the Accuracy of the time spans that can be generated.

The range of time spans that can be generated and their accuracy can, however, according to a further development of the invention can be significantly expanded if several counting registers are combined to form a sequential circuit.

in which each subsequent counting register corresponds to the cycle rate of the preceding one Counting register is advanced; if the assigned to the individual levels of the individual counting registers Memory sections in addition to a subsection for the identification addresses of the individual control commands Have subsections, the number of which corresponds to the total number of the respective upstream counting registers; if further to measure a predetermined period of time to this by setting all Counting register adds certain phase time of the command register, the time value thus obtained, based on the largest basic clock, broken down into integer multiples of the individual counting register clocks; if the The identification address of the associated control command is initially stored in a memory section of the one with the largest required Basic clock incremented counting register is written to the level of the counting register is assigned, which is characterized by the multiple of the associated basic clock, and if in the free Sections of the memory section determined in this way are the multiples of the remaining basic clocks as addresses for the one after the other the identification address of the control command together with the remaining multiples taking over levels of the associated counting register.

By connecting several counting registers in sequence, there is initially much less effort, as if one were to provide a single counting register of the appropriate size instead. True will by constantly transferring an identification address from one counting register to the other, the control effort in the Funds increased. However, this is less important than the savings in register levels. By taking into account the phase time of the command generator when a Identification address, the end of the time span is synchronized with the incremental clocks of the individual counting registers, so that with much less effort than with the known arrangement time spans with very Realize your tolerance limits.

According to another embodiment of the solution principle on which the invention is based, the Significantly simplify control processes within the command generator if they are triggered frequently time-dependent functional processes, such as B. Dial pulse integration, forwarding of digits, display of Intermediate selection times, counting according to zones, separate counting registers are provided, the number of stages in each case equal to the quotient of the respectively provided period of time and the respectively chosen most favorable Basic cycle time is. In this case the Identification addresses of new control commands in each case in the level of the counting register that has just been activated as the cycle time of the counting register corresponds to the desired time span. On the other hand, this results in significant simplifications when linking several commands to be processed at the same time.

Furthermore, the last-mentioned variant of the solution offers in a simple manner the possibility of a and to adapt the same counting register to different time conditions, for example as part of the Billing when changing from day to night tariff and vice versa must be met by the Counting register is assigned a control device through which the number of stages of the counting register cycle is changeable, and by shortening the counting register cycle z. B. as a result of switching the count from the night to the day tariff, which are assigned to the levels of the counting register that are no longer required Memory sections are allocated step by step to the memory sections of the remaining stages.

According to another development, there is also the

Invention the possibility that the memory sections assigned to the individual stages of a counting register for the identification addresses or the memory sections identified by these each have a sub-section used as a counter, so that times corresponding to the multiple of the counting register cycle can be monitored.
A further expedient development is that the memory sections assigned to the individual stages of a counting register for the identification addresses or the memory sections identified by them each have a subsection used for special identification so that one and the same memory section for different control functions, e.g. B. Forwarding of digits and fading in of intermediate dialing times, can be used several times.

Further details of the invention are shown below with reference to in the drawings Embodiments explained in more detail. In detail shows

F i g. 1 is a block diagram of the central control unit of a program-controlled switching system,
F i g. 2 shows an embodiment according to the general solution principle of the invention,

3 shows an overview of the memory sections coupled to the counting register to explain the general solution principle,

Fig. 4 is an overview of the multiple, one Sequential circuit forming counting registers coupled memory sections,

F i g. 5 shows an exemplary embodiment for counting registers, the cycle time of which is equal to the period of time to be monitored, 6 shows an overview of the memory sections for receiving the identification addresses of several at the same time control commands to be triggered,

7 shows an overview of the memory sections when using counting registers with switchable Number of stages per cycle and

F i g. 8 an embodiment of the with the command generator according to FIG. 5 collaborative data store.

F i g. 1 shows the basic structure of the central control creation of a modern telephone exchange "

so with a programmed function sequence. This: central control part is divided into a control unit I / O for the input and output of data, the data memory! SP, the command generator BF and the program control units linking all units

Prog-St. The data exchange between the central control unit is carried out via the control section I / O! and the peripheral system parts of the switching system under consideration, primarily the individual connection lines, the connection sets, the coupling network for the switching through of connections and their control devices. The memory part S contains both the individual control programs as well as all of the data important for the individual switching processes and the commands

h5 supplies the central control part with the various most control clocks to ensure the timely execution of the individual function programs and the individual To ensure mediation processes.

F i g. 2 shows part of the in FIG. 1 contained command generator BF and the part of the program control Prog.-St that is of interest in this context in a detailed representation. The core of the command generator part shown is the counting register Z1, which can be incremented cyclically by the basic clock T, in conjunction with the storage units SP 1 and SP 2.

Before the mode of operation of this exemplary embodiment is explained in more detail, let us first refer to FIG. 3 shows the solution principle on which the arrangement shown is based. Each of the π counting stages of the counting register Zi in FIG. 2 is permanently assigned a memory section in the memory SP1. This memory section could serve to directly record the identification address K-AD of a command to be carried out as soon as it can be ensured that during the duration of each time interval, that is the time between two successive control pulses of the clock generator T incrementing the counting register Zl, only one Time request would arise. Since, however, it is generally to be expected that several time requests have to be dealt with during each time interval, these memory sections are used to receive linkage addresses via which the code addresses K-AD stored in the memory unit SP 2 of FIG. 2 for the commands to be dealt with can be determined.

In the present case, an area of several memory sections is permanently assigned to each stage of the counting register Z1 in the memory unit SP 2 , the respective beginning of which in the memory unit SP1 is identified by a start address An-AD . The second part of the memory section in the memory unit SP 1 permanently assigned to each stage of the counting register Zl designates the address for the memory unit SP 2, in whose associated memory section the last time request of this time stage is written. By including this respective last address L-AD in the memory section of the memory unit SP1 that is permanently assigned to each counting stage of the counting register Zl, the functional sequence of the command generator shown can be significantly simplified, as will be shown later.

With reference to FIG. 3 it is now assumed that the counting register Zl is set to its second level. A memory area with the start address 20 is assigned to this level. From the associated last address L-AD, which corresponds to the start address, it can be seen that there is only a single control command for this time interval. On the basis of this state, it is now assumed that a control command which is subject to a time request of three interval times is to be processed by the central command generator. This means that, based on the current position of the counting register Z1, the present control command is to be incorporated into the counting stage 5 downstream of the activated counting stage by three interval times - corresponding to three stages. When reading the memory section assigned to this counting stage 5, to which a memory area with the start address 50 is allocated in the memory SP 2, the result is that no control command has yet been stored for this counting stage, since the last address LAD is equal to zero. The control command to be newly incorporated is therefore to be written into the memory section with the start address 50 of the memory SP 2 and the previous last address in the memory SP1 to be changed accordingly. The counting register Zl is then returned to its original state, that is to say it is set to the previous counting stage 2.

Since the counting register Z1 with the basic clock Tcyclic is incremented, counting stage 5 is reached after three time intervals have elapsed. The ones at this time stage integrated control commands are read one after the other and released for processing. Everyone in The control command integrated into the cycle of the counting register is therefore always the desired Period of time taken up again and thus processed in a timely manner. The range of this way measurable time spans and their tolerance limits is determined solely by the number of counting levels the relevant counting register and the length of the individual time intervals, which is determined by the Pulse repetition time of the basic clock cycle which increments the counting register.

Based on the basic principle explained above, the mode of operation of the arrangement according to FIG. 2 now the following:

With each control pulse of the basic clock Γ, the bistable multivibrator B 5 is set, the control pulse of which can take effect immediately via the locking gate S1 and on the one hand advances the counting register Z1 and on the other hand starts the clock stage rl when the bistable multivibrator J36 is in the rest position only tilted into the working position when the request to write a new control command is communicated via the control line san from the data and command memory, and at the end of the writing process for a new control command with the marking, the readiness for recording is reset again via the control line ab . In this way it is ensured that when a control pulse of the basic clock T arrives, a write process which is currently running can be ended without being disturbed.

As soon as the clock stage f 1 is started, the line controlled in the memory unit SP 1 by the counting register Zl is read via the reading device L and its information is transferred to the reading register L-Reg 1. When the following clock stage f 2 takes effect, the last address L-AD contained in the activated memory section is checked by means of the comparator VG 1.

If the checked last address is equal to zero, because there is no control command to be executed for this time interval, the control signal occurring at signal output 0 of comparator VG 1 is sent via coincidence gate K 2, which is already linked to bistable multivibrator B 1 set by clock stage f 1 has been released, immediately brought the clock stage it. The activation of this clock stage is a sign that there are no further control commands stored and consequently it is possible to switch over to accepting new control commands from the data memory SP of the central control unit zi and writing them into the memory SP 2.

If, on the other hand, a control signal occurs at the signal output χ of the comparator VG 1, the clock stage chain f 3 to i5 is started via the coincidence gate K 1. E there are control commands to be carried out for the controlled time interval, which now have to be read from the spoke SP 2. For this purpose the selection register Z 2 for the memory SP 2 with the start address An-Ai read at the memory SP1 is first activated with the clock f3 via the switch Ti

709 645 /

set. The activated memory section of the memory SP2 is read with clock i4 and its information content is transferred to the read register L-Reg2. Then checks with clock r5 by the comparator VG 2 whether a characteristic address K-AD is included in the read memory section depending on the result of this test is placed the clock circuit / 8 either via the signal output 0 of the comparator VG 2 and thus, as already mentioned, switched to the writing of new commands or, if a command is present via the signal output χ, the trigger stage B 3 is set and the clock stage f6 is switched on. The characteristic address K-AD is then forwarded the command to be done via the switch T2 for further processing with the work cycle 1 6

As soon as the control line be the feedback signal is available, that the output via the switch 72 control command is done, is switched via the now released by the trigger circuit A3 coincidence gate K 5 directly the clock circuit 1 7 effectively. In this way, the counter reading of the selection register Z2, which is also designed as a cyclically operating chain circuit, is first increased by one unit and the next memory section of the associated section area in the memory SP 2 is controlled and then, when the clock stage 1 4 is switched on, the read and output cycle for the memory SP 2 initiated again This game is repeated until finally the clock stage 1 8 is activated by the output 0 of the comparator VG 2.

Based on the setting of the counting register Zl by a control pulse of the basic clock 7, all control commands assigned to this time interval and stored in the memory SP2 are read and thus released for their execution. Only when this storage process has ended is the command generator shown available for receiving new control commands. The clock stage f8 initiates this second working section by setting the bistable multivibrator B Λ , in that readiness for writing is reported to the data memory SP via the control line from.

If there is a new control command to be recorded, then the chain circuit comprising the clock stages ί 9 to / 12 is started via the control line san and at the same time the register Reg is loaded with the identification address K-AD of the new command and its time request ZA. Clock i9 initially resets the flip-flop BA , which could also be done directly by the control pulse on the line san. Furthermore, the status of the counting register Z1 is temporarily stored in the memory Puf via the switch 74. With clock 1 10 the counting stage to which the new command is to be assigned is then determined from the old status of the counting register ZI and the time request ZA of the new control command by means of the adder A Di, and the counting register Zl is set accordingly. The memory section selected in this way is read with the following cycle ill and checked by the comparator VG 1 with cycle 1 12 whether or not a control command has already been stored for the selected time interval.

If there is still no control command, the new control command is to be written into the memory section of the memory SP 2 identified by the read start address An-AD . If, on the other hand, a control command has already been stored, the next following memory section in the memory SP 2 is to be determined by adding a one and the new control command is to be written there on the basis of the last address found.

Corresponding to these two basic tasks, when a control signal occurs at output 0 of the comparator VG 1 via the coincidence gate K 3, which has already been released by the trigger stage B 2, the chain circuit comprising the clock stages ί 13 to ί 15 is started. When the clock stage f 13 takes effect, the selection register Z 2 of the memory SP 2 with the read start address An-AD is set from the memory SP 1 via the switch Tl on the one hand and the write register S-Regi of the memory SPl is loaded with the new last address on the other hand. Furthermore, the identification address K-AD of the new control command is transferred to the write register S-Reg2 via the switch 73. With the following work cycle f 14, the information provided in this way in the write registers is written into the selected memory sections of the memories SP1 and SP2. Once this write operation is completed, the count register Z1 transmitted back via the switch 75 the initial state of the memory Puf again with the subsequent working cycle 1 15 and set the count register to the originally driven counter stage.

The writing of the new control command is now complete, and as a result, the clock circuit is in turn controlled 1 8 and reported to the data storage SF the pickup standby. As soon as another control command is present, the clock stage chain f9 to fl2 is again sar via the control line. started and thus carried out the work sequence determined by these cycle levels again.

If, when checking the last address L-AD read in the memory SPl by the comparator VG 1 at the end of this work sequence, it is found that control commands have already been stored for the time interval in question, the control signal occurring at the signal output Ar of the comparator VG 1 The clock chain comprising the clock stages f K to 1 18 is started via the coincidence gate K 4. On your first work cycle 1 16 of this new work sequence, the read last address L- AD is first passed over the 1-adder AD and the corresponding!

Storage location of the write register S-Reg 1 as well as the selection register Z 2 loaded with the new address.

At the same time, the identification address K-AD of the control command that has not occurred is transferred from the input memory Reg into the write register S-Reg 2 by opening the switch 73. Thus, all necessary for dei subsequently through the working clock 1 17 ausgelöstei write information provides bereitge. Again, the last bar 1 18 this work result bewirk over switch 75 setting de count register Zl to the original controlled) storage section, so that so that the Ausgangszustam is restored and can handle re Anlassung de-pull stage 1 8.

To derive the next Speicherplat2 address for the memory SP 2, the selection register Z 2, which can also be cyclically incremented, could be switched one step further with clock 1 16 and the new counter reading could be transferred as the last address L-AD in the write register S-Reg ί . The 1-encoder AD can then be omitted.
This game can repeat itself for so long now, bi

with the next control pulse of the basic clock T, the bistable multivibrator B 4 is tilted back into the rest position for the duration of the reading process that then follows.

The arrangement according to FIG. 2 underlying control principle can also be used in the same way perform if several counting registers are linked to one another in the form of a sequential circuit.

F i g. In this case, FIG. 4 shows the systematic division of the individual memory sections into the individual counting registers. A total of three counting registers E. Z and H are provided, which are linked to one another in the form of a sequential circuit. The counting register £ is analogous to the counting register Z1 of the arrangement according to FIG. 2 is immediately advanced by a basic clock whose control pulses follow one another, for example, with an interval of 1 millisecond (ms). A control pulse is applied to the remaining counting registers Z and H each time the upstream counting register has completed a full cycle. If, for example, ten counting levels are selected for each counting register, the selected basic cycle of 1 millisecond results in an incremental rate of 10 milliseconds for counting register Z and an incremental rate of 100 milliseconds for counting register H , corresponding to a counting cycle of 10 ms for counting register E of 100 ms for counting register Z and 1 second for counting register H. In total, time spans of up to 1.00 seconds can be monitored directly with the three counting registers shown. This range can be extended by further counting registers as required. The complexity of such a sequential circuit remains overall substantially below that for a single linear counting register with comparable time accuracy, since this would have to have a total of at least a thousand counting stages compared with the exemplary embodiment according to FIG.

Analogous to the arrangement according to FIG. 2, each counting stage of the individual counting registers is in turn permanently assigned a memory section in memory SP 1, which is divided into a subsection for the start address An-ASD of the associated section area in memory SP 2 and a subsection for the last address L-AD is subdivided to identify the memory section of the section area defined by the start address An-AD in the memory SP 2 which was last occupied with the identification address K-AD of a control command.

For the sake of simplicity, it is assumed that each memory section in the memory SP1 is assigned ten cyclically contiguous memory sections in the memory SP 2, each of which can be controlled consecutively one after the other.

The counting stage 8 of the counting register E is assigned in the memory SP 2, for example, the section area which begins with the start address 180. In this section area, only the memory sections 180 and 181 are assigned the identification address D and E, respectively, of control commands to be processed.

In addition to the subsections and the identification addresses K-AD of the individual control commands, the memory sections assigned to the counting registers Z and H in the memory SP 2 also have additional subsections a or a and b , in each of which the counting stage is marked into which a control command is sent upon transfer from one counting register to the next upstream counting register. The subsections a denote the counting stages of the counting register Hund, the subsections b the counting stages of the counting register Z.

The operating principle on which such an arrangement is based is now as follows: As soon as a control command to be written is present, the phase time of the command generator is first determined. This phase time results from the respective position of the individual counting registers, taking into account the clock cycles that advance the individual counting registers. In the present case, counting register E is in position 8, counting register Z is in position 2 and counting register H is in position 6, which corresponds to a phase time of 628 ms. The duration of the time span to be monitored, for example 856 ms, is first added to this phase time and the sum obtained in this way is broken down into multiples of the interval times specific to the individual counting registers. A related example is shown in the lower left part of FIG. 4 specified. The following control sequence results for the selected values: The control command is first written into a free memory section of the memory SP 2 which is assigned to the counting stage 4 of the counting register H. As with the arrangement according to FIG. 2, the required free memory space in the memory SP 2 is derived directly from the last address L-AD contained in the controlled memory space of the memory SP1. These features, in this case the memory location 343 in the memory SP 2, so that it results in as the next free space of the storage section 344 in this memory section then be the characteristic address and in the partial areas A and B are previously determined multiple of 4 and 8 added. Furthermore, the last address assigned to the counting stage 4 of the counting register H is modified accordingly in the memory SP 1. The counting register H is then set back to the previous counting level 6.

As soon as eight incremental pulses are fed to the counting register H and thus the counting stage 4 is reached within the normal counting cycle, starting with the start address 340, all memory sections occupied by a control command of equal priority are read in memory SP 2, including the last one in memory section 344 registered control command X.

At the same time it is checked whether the subsections a and b contain markings, the absence of which is a sign that the time span with which the read control command was affected has already passed and therefore a transfer to possibly upstream counting registers is no longer necessary.

In the present case, however, both the subsection a and the subsection b each contain a marking, the marking of the subsection b indicating that the associated control command is first passed on to the counting register Z and is to be incorporated in the counting stage 8 there.

The associated memory section is again controlled, based on the last address 282 de next free memory space 283 in memory SP: determined, there the command X is written , the last address in memory SP1 is scanned accordingly and the counting register Z returns to the old position; switched back. The same game is repeated when the command X is taken over by the counting register E, where it is now incorporated in the counting stage 4 analogously to the information in the subsection a of the memory SP 2

This results in the following transit times in the individual counting registers for the Stenerbefel X in question: 772 ms in counting register H, namely eight interval steps corresponding to 800 ms, minus the phase time d <counting registers E and Z with 8 ms and 2 ms, 80 ms i

■ ΊΙΤ.

Counting register Z and 4 ms in counting register E, which together results in the desired time span of a total of 856 ms. It should be noted that the running time in the upstream counting registers, in the present case the counting registers £ and Z, corresponds to the running time from the start of the cycle to the activation of the counting stage in which the command is integrated, as the phase time is taken into account of the command generator at the beginning and, as a result of the sequential control of the individual counting registers, a transfer from one counting register to the next upstream one takes place at the beginning of the cycle. This also reveals the great advantage of this solution, because as a result of the synchronization of the respective command acceptance with the incremental cycle of the individual counting registers, the deviation from the desired time span is never greater than the smallest claimed time interval, i.e. lsms when counting register E is used.

That on the basis of FIG. 4 explained solution principle for a central command generator can be realized in an analogous manner by an arrangement, as the solution principle explained with reference to FIG. 3 by the arrangement according to FIG. 2, which would only have to be duplicated according to the number of counting registers used. The individual counting registers with their sequencing controls would then expediently be interconnected in such a way that when the first counting stage of the lowest-ranking counting register is activated, with reference to FIG. 4 of the counting register E, all control commands linked to this counting stage are initially output, so that all control commands incorporated in the activated counting stage of the next following counting register are checked and all control commands to be transferred to the previous counting register in an interplay with this counting register analogous to the transfer of control commands in the Arrangement according to Fig.2 are transmitted. After all control commands have been rewritten or issued, the control commands incorporated in the next higher counting register are checked in the same way and, if necessary, transferred to the other counting registers that have already been checked. Only when all of the control commands incorporated in the respectively activated counting stages of the individual counting registers of the command generator have been checked, analogous to the arrangement according to FIG. 2 started to take over control commands from the data memory SP, which have now arisen.

Fig.5 shows a further embodiment, the refers to counting registers for special cases. The main difference between that in the arrangement according to FIG. 5 provided counting register Z1 and according to FIG. 2 is that not a multitude are monitored by time spans, but only a single time span per counting register and that consequently the number of stages is equal to the quotient of the time period to be monitored and the the most favorable basic cycle time selected in each case, with which the counting register is incremented, is selected.

Otherwise, however, shows the command generator part according to FIG. 5 has approximately the same structure as that of FIG. 2. Each stage of the counting register Z1 is also permanently assigned a memory segment in the memory SPi , to which a segment area in the memory SP2 corresponds in each case. The arrangement according to FIG. 5 is compared to that according to FIG. 2 has also been expanded to the extent that when the information contained in the memory SP 2 is read and released for further processing, the control commands read are not simply deleted in the memory SP 2 , but remain stored until a corresponding delete command is sent on the control line belö is present, so that one and the same control command can be called several times in succession at the same time intervals. It does not have to be, as in the case of an arrangement according to FIG. 2, to be re-entered as a new control command after each reading process.

In order to still be able to maintain the linkage of control commands of the same rank via linkage addresses in a simple manner, the principle of linking control commands of the same rank to one another has been changed compared to the arrangement according to FIG. 2 also changed. Since commands can also be deleted, a rigid sequence for the occupancy of the individual memory sections within the section areas E in memory Sp 2 permanently assigned to a counting stage cannot be maintained. For linking, therefore, an additional sub-area is required in each memory section for receiving the following address F-AD , which indicates the next memory section occupied by a control command.

On the other hand, it was possible to dispense with the subsections for the last addresses L-ΛΟ in the individual memory sections of the memory SP 1. Instead, only a single control identifier is provided in the form of a marker bit MB , which indicates whether or not a control command is actually stored in the associated counting stage. This flag bit can also be dispensed with if the check is carried out analogously to the arrangement according to FIG. 2 with the comparator VG 3. However, the amount of work required increases because the memory SP2 always has to be activated first in order to be able to carry out this test.

Furthermore, an additional storage register Reg 3 is provided for the new last address L-AD to be worked out in each case.

Before the mode of operation of this arrangement is explained in more detail, the principle of linking control commands of equal priority on which the arrangement shown is based should first be explained in connection with FIG. 6 shows a section area of the memory SP 2 with the memory sections 400 to 409, which is permanently assigned to a memory section of the memory 5Pt and can be controlled from there via the address of the memory section 400 in the memory SP 2 as the start address An-AD Read register L · Reg of the memory SP 2 and the storage register Reg 3 for the respective last address L · AD.

Notwithstanding that of the arrangement according to FIG. 2, the memory space for each new control command to be written is not gained by increasing the respective last address L-AD by one unit, but starting with the start address An-AD present in the memory SP 1, in the present case the start address 400, the memory sections of the so-called section area are checked step-by-step one after the other to determine whether they are already occupied and the control command to be written is each written into the memory section which is found first to be unoccupied.

All that remains is the problem of writing the address of the newly allocated memory section as a new follow-up address F-AD in the memory location in which the previous, last control command was included

has been written to an identification address K-AD . This address is taken from register Reg 3. This is easily possible since there are new control commands as in the exemplary embodiment according to FIG. 2 can only be accepted if at the beginning of the time interval, ie immediately after the control of its counting stage of the register Z 1 in FIG. 5, all control commands incorporated into this time interval have been read and the register Reg 3 takes over the address of the memory section that was last read but not deleted.

Given the specified occupancy of the memory sections 400 to 409 shown, the last control command E is written to the memory section 407 and has not been deleted. This means that register Reg 3 is automatically set to address 407 at the end of the read process. In the last memory section identified in this way, the address of the memory section 403 receiving the new memory command would have to be entered as the subsequent address F-AD and the status of the register Reg 3 set to the new last address 403. The memory sections of the section area shown can therefore now be optionally linked to one another without a predetermined sequence.

The reading process of each section area immediately after the activation of the associated counting stage of the counting register Zl in FIG. 5 initially runs in such a way that, beginning with the start address An-AD of the selected memory section in memory SP1, the so-called memory section in memory SP 2, in the present case the memory section 400, is read in a known manner and that in this Memory section contained control command A is released for further processing. If, after processing this command, there is a response that the command cannot be deleted, then the address of the memory section last accessed, that is section 400, is transferred to register Reg 3. With the following address 40t in the memory section 400, the so-called memory section 401 is then driven next and the command B stored therein is read. If this command cannot be deleted either, the address of this memory location is now transferred to register Reg 3 and so on.

If, on the other hand, it turns out that, for example, the control command B contained in the memory section 401 is to be deleted, the memory section 400 is controlled again using the last address L-AD contained in the register Reg 3 and the section for the subsequent address F-AD is entered in the read register L -Reg included subsequent address 402 is written. On the basis of this subsequent address, the memory section 402 designated by it is then activated and the read cycle is continued.

A special solution is necessary, however, if a command contained in a memory section identified by a start address An-AD is to be deleted, since when the command is deleted, the start address contained in the memory SP 1 makes sense as the beginning of a read cycle without additional measures would lose the identifying tax address. As a result, when there is a delete command for a command contained in the first memory section of a section area, the next following control command, which can be determined via the subsequent address, is transferred to this start section and the read cycle is continued with this new command.

In application to the example chosen according to FIG. 6th the following follows:

After reading the memory section 400 as the starting section of the section area indicated in the memory SP2, both the following address F-ADaIs and the identification address K-AD of the control command are in the read register L-Reg. If the command to erase now comes, the next address contained in the read register L-Reg is used to drive the memory section 401 for the next control command B and this section is also read. The information contained in this way in the read register L-Reg is now written via the write register of the memory SP2 into the starting section 400 designated by the register Reg3 , so that this memory section now contains the following address 402 and the control command B as information. This memory section is then read again and the control command B contained therein is released for processing. If this command had to be deleted as well, the control cycle just described is repeated anew, so that finally the information found via the next address 402 in the memory section 402 would now be contained in the memory section 400.

The status of register Reg3 is not changed during this entire time. A change is only made if a read command does not need to be deleted. In this case, the status contained in register Reg 3 is replaced by the address of the associated memory section, so that register Reg 3 identifies the memory section whose content was last has been read but not deleted.

Starting from the above-explained principle for linkage of equal commands the operation of the arrangement will now be explained contiguous to Fig.5: With each setting of the count register ZX via the inhibit gate Sl having the same function as in F i g. 2 exercises, by a control pulse of the basic clock T , the clock stage 1 1 is activated at the same time and thus read the memory section controlled in the memory SP 1 via the reading device L and the start address An-AD is transferred to the read register L-Reg 1. At the same time, the identifier contained in the activated memory element MB is sent via the sense amplifier LV to the coincidence gates Ki and the blocking gate S 2 and thus checks whether a control command is actually stored in the memory SP 2 for the time interval marked by the setting of the counting register Zl. If this time interval before not to be done Direction control command, it is immediately reacted with the barrier at the output of gate S 2 control signal occurring on the barrier gate S3, whose function will be explained later, the clock circuit 1 15 °. The coming into effect of this clock stage is a sign that there are no more control commands stored and consequently it is possible to adopt new control commands from the data memory SP of the central control unit and write them into the memory SP 2 by analogously to the arrangement according to FIG bistable flip-flop oil is set and is thus marked via the control line from the reception area.

If, on the other hand, a control signal occurs at the output of the coincidence gate A '1, the clock stage chain becomes 1 3 to

709 645/61

ί5 left on. There are therefore control commands to be carried out for the controlled time interval. which must now be read out from the memory SPI. For this purpose, the selection register Z 2 of the memory SP 2 with the start address An-AD read from the memory SP 1 is first set with clock ί3 via the switch 71. With clock 1 4, the selected memory section of the memory SP 2 is read and its information content is stored in the read register L-Reg2 transferred. With a cycle <5, the identification address K-AD of the read control command is finally forwarded via the switch 73 for further processing. At the same time it is checked by means of the comparator VG1 whether a subsequent address F-AD is written in the read memory section as a sign that there are still further control commands. Depending on the result of the test, the bistable multivibrator B 3 is set either via the signal output 0 of the comparator VG1 or, if further commands are present, the multivibrator B 2 is set via the signal output χ.

As soon as the feedback is available via the control line be that the control command issued via the switch 73 has been dealt with and does not need to be deleted, depending on the result of the check by the comparator VG 1, either via the coincidence gate K 2, the clock stage f6 or but via the coincidence gate K 3 and the blocking gate S3, the clock stage 1 15, which characterizes the reading process as ended, is activated immediately.

When the clock stage 1 6 becomes effective, the status of the selection register Z 2 is first stored in the register Reg 3 as the last address L-AD via the switch 74. Then with clock ί7 the last read subsequent address F-AD is released via switch 75 for setting the selection register Z 2 to the memory section of the memory Sp 2 marked in this way and then with the switching on of the clock stage t4 the read and output cycle for the memory SP 2 initiated again. This game is now repeated until finally the clock stage 1 15 is activated via the coincidence gate K 3, as already explained above.

If, however, after a control command has been issued from the data memory SP, the feedback via the control line belö that the last control command read is to be deleted, then the clock stage i8 is switched on and the control cycle for the deletion of this command and the rewriting of the link addresses is initiated. The comparator VG 2 first checks whether the status of the selection register Z 2 is equal to the start address An-AD \ st contained in the read register L-Reg 1.

If the result of this check is negative because the two compared addresses do not match, the control signal appearing at the output η of the comparator VG 2 turns on the clock stage 1 13 and consequently the selection register Z2 via the switch 78 with the last address contained in the register Reg3 L-AD is set and the following address F-AD contained in the read register L-Reg 2 is transferred via the switch 77 to the corresponding section of the write register S-Reg2 . With the following clock f 14, the new following address is entered in the memory section of the memory SP 2 , the control command of which was previously read but not deleted.

The further work flow now depends on whether or not the last control command read, which has since been deleted in the memory SP 2, is also the last command of the command sequence to be read during this time interval. This decision is supplied by the comparator VG 1, which is already activated with clock f5, via the two downstream bistable flip-flops B2 and J33. If the next address of the last read memory section was equal to zero and if the bistable multivibrator B 3 is set, then with the stepping pulse the

ίο cycle stage <14 via the coincidence gate K 5 and the blocking gate S3 immediately the cycle stage ί 15 started. The work sequence for reading stored control commands is thus ended, and the work sequence for writing new control commands can be accessed.

is missing to be redirected.

If, on the other hand, a subsequent address was still available in the last memory section read and the bistable flip-flop B 2 was set, the incremental pulse from clock stage 1 14 is passed on to clock stage 17 via coincidence gate K 4, thus initiating the read cycle again.

If, in the other case, the address comparison carried out by the comparator VG 2 with clock ί 8 turned out to be positive because both addresses match, then, depending on the signal state of the two bistable flip-flops B 2 and B 3, either the clock stage f26 via the coincidence gate K 7 or via the coincidence gate K 6 started the chain circuit consisting of the clock stages ί 9 to f 12.

The effect of the clock circuit (26 is a sign that the most recently read and now deleted control command in the memory SP 2 was the only stored control command of the present time interval. The flag MB contained in the memory SP 1 of the selected memory section is therefore cleared and immediately thereafter the Step 1 15 started to initiate the work sequence for writing new control commands.

The activation of the clock stage chain i9 to f 12 is

On the other hand, a sign that there are still further control commands stored, but that, before the read cycle is continued, the following control command is transferred to the memory section identified by the start address An-AD , as already shown in FIG. 6 has been explained is to be transferred. For this purpose, the following address F-AD contained in the read register L · Reg2 is sent to the memory section last read, but which has since been erased with cycle f8, via switch 75 with cycle f9 to selection register Z 2

so transferred and this is set accordingly. The memory section found in this way for the subsequent control command is read with cycle ί 10 and the information obtained in this way is transferred to the write register S-Reg 2 with cycle ill via switches 76 and 77. Furthermore, with the same cycle ill the start address contained in register Reg3 is transferred as the last address to selection register Z 2 via switch 78, so that with the following cycle f 12 the control command cached in write register S Reg2 is transferred to the start address An-AD marked memory section can be written. The rewriting process is thus ended, so that the normal read cycle for the memory SP 2 can be switched back to. However, since the next command to be forwarded has already been read before the rewrite and is still available in the read register L-Reg 2 , in this case not the clock stage f4, but the

Step 1 5 started immediately.

Depending on the output signals d <; r comparators VG 1 and VG 2 as well as the control signals on the control lines be or belö , a number of possible work sequences result in the course of the reading process. The two bistable Kippsiufen B 2 and B 3 are each switched back to the starting position when a final decision has been made about the work sequence to be processed, for example with the control clocks i6, i7, i9, f 15 and 1 26 Reading is achieved in each case when the clock stage 1 15 is started.

Based on the setting of the counting register Zl by a control pulse of the basic clock T, all control commands assigned to this time interval, which are stored in the memory SP 2, are read. Only when this reading process has ended is the command generator shown available for receiving new control commands. As in the arrangement according to FIG. 2, this second working section is initiated with the marking of readiness for recording to the data memory SP via the control line ab by the trigger stage B 1 set by the clock stage f 15

In the event that there are new control commands to be recorded, the chain circuit comprising the clock stages Γ16 to fl8 is started via the control line san and at the same time the memory Reg 1 is loaded with the identification address K-AD of the new command. Furthermore, as in the case of the arrangement according to FIG. 2, the barrier gate S 1 is blocked via the bistable multivibrator B5

However, before a new command can be stored in the memory SP 2 , a free memory section must first be determined in the section area determined by the pending time interval, as already shown with reference to FIG. 6 was explained. For this purpose, the start address from the read register L-Reg 1 is first transferred to the selection register Z 2 with cycle 1 16 via the switch 71, and the first memory section of the section area in question is thus selected

This memory section is then read with cycle ί 17 and the section intended for the identification address is checked for the presence of a command with cycle r 18. This check is carried out with the comparator VG 3. If the memory section checked is already occupied, which is indicated by a control signal at the output χ of the comparator VG 3, the clock stage f 19 is switched on and the selection register Z 2 is cyclically activated by a control pulse subsequent memory section set in memory SP2 . The clock stage fl7 is then switched on again and the newly activated memory section is thus read and checked again. This game is repeated until finally a control signal appears at the output 0 of the comparator VG 3 as a sign that a memory section that has not yet been used has been found.

The chain circuit consisting of the clock stages f20 to i25 then takes over the further program sequence. With cycle ί 20, the corresponding section of the write register S-Reg2 with the identification address K-AD temporarily stored in memory Reg 1 for the new control command to be stored is loaded via switch 79 and written with cycle 21 into the memory section of memory SP 2 found to be free . It is not necessary to write a subsequent address F-AD in the same memory section, since the newly written control command is always the last in the sequence of control commands of equal priority.

The link between the newly written control command and the control commands that have already been saved must then be ensured. For this purpose, the status of the selection register Z2 is forwarded via the switch T10 or 711 to the areas of both the read register L-Reg 2 and the write register S-Reg2 provided for the subsequent address F-AD with clock / 22. Then with clock f23 the status of the register Reg3 is transferred via the switch 78 to the selection register Z 2 and thus the memory section selected which is occupied by the last command of the previous command sequence of the pending time interval. With cycle f 24, the address temporarily stored in the write register S-Reg2 is then written into the selected memory section as the next address for the control command written last. The last written control command is thus finally linked with the respective preceding control command.

In order to further ensure that the link with the previous commands can be carried out in the same simple manner in the case of further control commands to be written in, the address temporarily stored in the section for the following address F-AD of the read register L-Reg2 is activated via switch 712 with clock f25 the register Reg 3 transferred. This register thus contains the address for the memory section in which the last command of a command sequence was written.

At the end of the sequence of operations described clock circuit is again ί turned 15 and again recording standby marked on the control cord. This cycle is then repeated as long as necessary until finally, with the occurrence of the next control pulse of the basic clock 7, the flip-flop B 1 is returned to the rest position for the duration of the reading of stored commands.

In addition to the part of the command generator BF and the program control Pro-St already described, the arrangement according to FIG. 5 in its left part an addition for the case that the number of stages of the counting register Zl should be switchable so that, depending on the effective number of stages, counting register cycles of different durations result. Such switchover of the counting register cycle is necessary, for example, if the counting register shown is used for generating counting pulses in telephone systems and a distinction is to be made between a night tariff N7 and a day tariff 77 with different follow-up times for the individual charge pulses.

The control principle used here will first be explained in more detail with reference to FIG. The memory sections in the memory SPi which are permanently assigned to the individual counting stages 0 to 9 of the counting register Z1 are again shown, each of which contains a start address An-AD of a section area assigned to each counting stage in the memory SP2. For the sake of simplicity, ten memory sections are provided in the memory SP 2 for each counting stage of the counting register for receiving the identification addresses KA D of control commands and any necessary subsequent addresses F-AD .

Furthermore, it is assumed that, starting from a predetermined basic clock T, the to be generated

Counting pulses for the recording of charges require a counting cycle of / Y _n = 10 counting levels for the night tariff and a counting cycle of a total of n = 5 counting levels for the daytime tariff.

During a switchover of the counting register itself and thus the change in the number of stages per cycle, none Difficulties arise, however, when switching the counting cycle to a lower one Number of stages the difficulty of correctly carrying out the counting commands assigned to the counting stages that are no longer required to be included in the remaining counting levels. In the case of FIG. 7 allocation made the section areas of the memory SP 2 assigned to the counting stages 5 and 6 would therefore be the remaining ones Allocate counting levels 0 to 4 of the counting register. This is now carried out in such a way that after Switching from the long to the shortened counting cycle, starting with the first shortened counting cycle, after the completion of the control commands integrated in the respective activated counting stage, cyclically one after the other one of the no longer required counting levels is activated and the one in the associated section area of the memory SP 2 contained control commands via their start address with the command sequence of the previously controlled Section area can be linked.

After the counting cycle has been shortened, first the counting stage 0 is activated, and then, starting with the start address 00, the control commands A to D stored in the memory SP 2 are processed in sequence.

At the end, for example, memory locations 00 to 03 are still occupied with one of the control commands A to D. Before new control commands are written in, the counting register is now set to the first counting stage 5 that is no longer required for the shortened counting cycle. If there are also control commands for this counting stage, in the present case the control commands M to Q in the memory sections 50 to 54, the start address contained in the controlled memory section of the memory SP1, namely 50, is used as the following address in the memory section of the previously controlled section area in the memory SP 2 is written in accordance with the counter level 0 which is occupied by the last command of the command sequence there. In the present case, this is in the memory section 03, which is occupied with the control command D.

This game is now continued until all counting levels that are no longer required, that is, counting levels 5 to 9, are checked and their control commands are incorporated into the remaining counting levels 0 to 4. In addition, the control commands E to G contained in the memory sections 60 to 62 are appended to the command sequence of the counting stage 1 by writing the start address 60 into the memory section It, and so on.

This principle is easiest to implement when the number of counting cycles that make up the shortened counting cycle Counting levels is greater than or equal to the number of remaining counting levels. But it is also feasible if this condition is not met. In this case the individual counting levels would have to be shortened Counting cycle take control commands instead of just one of two or more counting levels of the rest of the cycle.

In accordance with the control principle explained above, the one in the left-hand part of FIG. 5 now as follows: As soon as the switchover command for shortening the working cycle of the counting register Zi is present at the signal input TT and a control signal appears at the output a of the counting register Zl which indicates that the counting register Z1 has now reached the first stage of the counting cycle the coincidence gate K 8, the bistable multivibrators and SS6 Bl set. The flip-flop B 6 effects the switching of the counting register Zl via the control line u by preventing, in a manner known per se, that after reaching the last counting level of the shortened to counting cycle, the subsequent control pulse of the basic clock T acts on the next counting level as in the unabbreviated counting cycle , but the control pulse is diverted directly to the first counting stage of the counting register Zl. The blocking gate S 4 prevents that after the counting cycle has been switched by the bistable multivibrator B 6, the bistable multivibrator Bl is brought back at the beginning of each further counting cycle. This switching state remains until the transition from the day tariff to the night tariff takes place again and the flip-flop B 6 is switched to the rest position, so that the counting register Z1 runs through its full cycle again from this point in time.

On the flip-flop Bl the reclassification of the incorporated into the unneeded counting stages commands against it is initiated by the lock gate is locked S3, so that at first before turning on the clock stage f 15 stored in the transition from reading commands to the writing of new control commands via the coincidence gate K 9 the chain circuit consisting of the clock stages fabis ic is started.

With clock ta , the count of the counting register Z1 in the buffer memory Reg 2 is first ensured via the switch 713. Furthermore, with the following control clock tb , the number n of the counting steps forming the shortened counting cycle is added to the previous count of the counting register Zl and the counting register Zl is set to the memory section thus determined, which is then read with the clock te. The start address An-AD contained in this memory section thus reaches the reader register L-Regi, and the control signal coming from the memory element MB characterizing the occupancy state is passed on via the read amplifier LV to da: coincidence gate KiO and to the blocking gate Si.

If there is no control command for the checked counting level

stored before, the de output takes place:

Lock gate S5 directly through the lock gate S3 previously suppressed activation of the clock stage ί 15.

If, on the other hand, there is a control command in the checkedi

Counting stage stored before, the chain circuit consisting of the clock stages ic / to ig is started via the coincidence gate K 10. With the first working cycle of this derailleur, on the one hand, the:

Switch T & the last address L-AD contained in the memory Reg 3 , which designates the memory section containing the last command of the command sequence just checked, is transferred to the selection register Z2 and this memory section is controlled. At the same time, the following address F-AD receiving part of the write register S- Reg 2 is loaded with the start address An-AD contained in the read register L-Reg via the switch 7 "14, so that the start address d (instruction sequence to be incorporated) m the following clock te as the following address in de the last command of the accepting command folder

containing memory section can be written. With clock tf , the original status of the counting register Zl temporarily stored in the memory Reg 2 is transferred back via the switch T 15 and the counting register is thus set to the level previously taken. The subsequent work cycle tg ensures that the occupancy identifier MB is written into the original counting stage if no control command has been stored so far. Since the current operation sequence ui is now complete, is done with the indexing cycle of the clock circuit tg also previously suppressed activation of the clock stage 1 15 and thus the reversal of the write operation.

The working cycle just described is now initiated until all the counting steps that are no longer required in the shortened counting cycle of the counting register Z1 have been recorded. The monitoring required for this is carried out by the comparator VG 4, which is controlled in each case with the working cycle tb. If the counting register Z 1 finally reaches a counting stage, the value of which is equal to the difference between the number n _{n of} the counting stages of the unabridged and the number n, of the shortened counting cycle, a control signal occurs at the output j of the comparator VG 4, which the bistable multivibrator Bl switches back into the rest position, so that the locking gate S3 is unlocked again.

F i g. 8 finally shows a part of the central command and data memory SP with the associated part of the program control Prog-St, which is suitable for cooperation with the example shown in Figure 5 and already explained commander BF. Using the example of this cooperation, it should finally be shown how several control functions of a centrally controlled mining system can be carried out in connection with just a single counting register in an advantageous manner.

F i g. For this purpose, 8 shows in its upper part a section of the central data memory SP with the associated read and write registers L-Reg and S-Reg, the control register Sf for the selection of the memory sections individually assigned to the individual peripheral devices of the switching system and the common ones Data line DL for the transmission of the data stored in the various sub-areas of the individual memory sections to the individual control units.

In the present case, it is assumed that the associated peripheral devices of the switching system are so-called dialing records, which receive the _M dialing digits sent out by a subscriber in the form of series of current impulses and send them out again as required. The conversion of the individual series of current impulses into the dialing digit _Vi equivalent to the number of current impulses forming a series of current impulses and, conversely, the conversion of the individual dialing digits into an equivalent number of current impulses having a series of current impulses when a dialing digit is sent out on the basis of the in the associated memory section of the data memory SP u) present data in connection with the command generator JSF according to FIG. 5 and the program control Prog-St and depending on the commands communicated via the input and output control I / O from the requesting selection block that a pulse has arrived _b 5 or that a digit is to be sent. Such a command is received by the input memory Re ^ l, which is coupled to a command decoder B.

Each election record is a memory cell in the data memory SP, z. B. the memory line 4, individually assigned, which can be controlled on the basis of the communicated address by the selection register Si. Each of these memory lines is subdivided into several sub-areas, each of which has the following meaning: The sub-area WZi is used to count the pulses of a series of current impulses recorded by the associated selection set, the end of each current series being monitored depending on the markings contained in the sub-area ZB. This sub-area ZB comprises only two bits in the present case. The sub-area NS / ZW is used to record the digit to be sent again from the elective rate or to record a code to measure the intermediate dialing time between two successive series of current impulses, whereby the end of the conversion of a number to be forwarded into an equivalent series of current impulses depends on the marking in the sub-area MBx, which in the present case comprises only one bit. The other sub-areas F, N and. S also includes only one bit, namely the sub-area F indicates the fade-in of an intermediate dialing time, the sub-area N the forwarding of a digit and the sub-area S the synchronization of the control cycle specified by the command generator BF with the central clock generator for generating the series of current impulses to be sent. The other sub-areas SZ-E and SZ-A are used as input and output point counters for the individual dialing digits temporarily stored in sub-areas Z 1 to Zn , which can be individually selected via the digit selector we for input and wa for output.

The following explains the general functional sequence when receiving dialing pulses and when forwarding stored dialing digits in the form of power surges, depending on whether there is a request from the input-output control unit I / O or a call by the command generator ßF.

I. Voting impulse recording

Before the work sequences required for recording the Walil pulse are described using the arrangement shown, the meaning of the markings contained in the sub-area ZB of the command and data memory SP will first be explained. It is assumed that the counting register Zl of the arrangement according to F i g. 5 is incremented with a basic clock T ", the control pulses of which follow one another with an interval of 10 ms, and that the counting register has a total of * counting levels, so that the cycle time of the controlling counting register is a total of 50 ms Zählregisterstu fe is driven, is the data storage, vorausge is that a control command vorliegi stored likewise every 10 ms from the command transmitter ßFangesteuer an initiate from the stored data depending on operation sequence. one and the same Speicherat section of the data memory SP but each ni after a lapse of 50 ms is called periodically until the associated address has been deleted in the central command generator. The cycle duration of 50 ms enables, based on the control functions to be carried out, namely the implementation of series of current impulses
equivalent dialing digits and forwarding ve

709 645,

stored digits with fade-in of intermediate dialing times between the individual series of current impulses, an extremely simple control with very little effort, since the pulse train time of the to be processed Series of current impulses is generally 100 ms with a pulse pause ratio of approximately 60:40 ms.

If you now identify both memory elements of the sub-area ZB with a marking analogous to the information 11 with each new pulse being written in the sub-area WZi, this is a sign that the command generator ßF after 50 ms calls up the same memory section that since writing no more than 50 ms has passed since the last current impulse, i.e. a further current impulse is not yet to be expected. This fact is now characterized in that the read information 11 is modified into information 01. Reading this information after a further 50 ms is therefore a sign that 100 ms have now passed since the last current pulse was written. If this information 01 is converted again, namely the information 00, then after a further 50 ms reading this is finally a sign that a total of 150 ms have passed since the last current pulse was written and the series of current pulses recorded is to be regarded as ended. So you can reference to the three pieces of information 11, 01 and 00 clearly differ in the subregion example, which period last surge has passed since registered and whether the Stromstroßreihe as finished as to look at.

Difficulties are caused, however, by the fact that the pulse repetition time of the series of current impulses to be recorded is not always the same, but can fluctuate. It is therefore easily possible for a new current surge to be written in either shortly before the associated memory section is called up by the command generator or only shortly afterwards, so that a write request can either find information 01 or information 00 in sub-area ZB. If the latter information is 00, the call by the command generator must have been made shortly beforehand due to the other boundary conditions. Information 11 can therefore be written without hesitation in sub-area ZB with a simultaneous increase in the number of current impulses contained in sub-area WZi a => by a 1 and thus the new start of a 100 ms cycle can be identified.

If, on the other hand, one were to proceed in the same way when the information 01 was found in the sub-area ZB w , the monitoring cycle would be shortened by 50 ms, since when the command generator calls up the same memory section immediately afterwards, although the preceding 100 ms cycle has just ended is, the existing information 11 in the sub-area -v> ZB would already be converted into the information 01, as if the first 50 ms interval! would have already expired. To circumvent these difficulties, when there is a request from the input / output control unit I / O to write a further current impulse in the sub-area WZi and at the same time the information 01 is present in the sub-area ZB \ n the sub-area ZB , the information 10 is first written , which is then modified into information 11 when the command generator calls it immediately afterwards and h ^r ) so that the new 100 ms cycle is first initiated.

In front of this, the following functional sequences result:

!. Request by input-output control I / O
A control command coming from the selection set reaches the input memory Reg 1 via the input / output control I / O , and it is first checked what kind of request it is. If there is a dial pulse request, the flip-flop B 1 is set and thus the clock circuit r 1 is switched on via the mixer Mi. Via the switch 7 * 1, the selection record address cached in the input memory Reg \ is transferred to the control register ST of the data memory SP and the associated memory section, e.g. B. 4, controlled. The selected memory section is then read in the cycle f2 via the associated reading device L and the information contained therein is transferred to the read register L-Reg .

Since a series of impulses recorded by the selection set is to be processed, the clock stage i3 is also activated with the stepping pulse of the clock stage f2 via the coincidence gate K 3 and a check is made with the associated work cycle on the basis of the comparator VG 1 whether it is a new request, ie the beginning of a new series of current impulses, or another impulse of an already running series of current impulses. In the first case the sub-area WZ / of the read memory section would be empty, and in the other case it would contain any of the digits 1 to 9.

a) If the start of a new series of impulses is present, the control signal appearing at the zero output of the comparator VG 1 is used to switch on the clock stage f6 via the coincidence gate K 5, so that by means of the 1-adder ADX via the common data line DL and the switch 7 * 3 the number 1 is written into the associated sub-area of the write register S-Reg . Furthermore, both storage elements of the sub-area ZB are marked in the write register via the control switching element Zb, which is designed as a two-stage counter switching element. This means that all the necessary information changes are initially prepared. The new information provided above is written in after the clock stage f 8 has been activated by the pusher S de; Data storage. Further, the address of the associated dial record is * 9 pass through the switch 7 to the buffer memory Puf2 and thus a <request for the central command encoder selected, the new command, as already ai hand the F i g. With derr same work cycle 5 has been described, dam takes over. The work sequence triggered by the request via the input / output control I / O is thus ended, which is indicated by the end marking carried out by the incremental pulse of the clock stage / 8 via the coincidence gate K 8.

b) If, on the other hand, the signal output χ of the comparator VG 1 carries a control signal when checking the memory area WZi with the work cycle f 3, the further work sequence depends on which marking is contained in the section Z of the read memory section, which is also included Clock f 3 is checked by comparing VG 2.

If the output 00 of the comparator VG 2 supplies a control signal because the sub-area ZB contains the information 00, then the coincidence gate

K 7 also switched on the clock stage f6. The memory section that has been read must have been called up by the command generator beforehand. In addition, at least 100 ms have passed since the last current impulse was written in sub-area WZi , so that a 1 must be added again in this sub-area and information 11 to identify the start of a new 100 ms cycle must be written in sub-area ZB.
If, on the other hand, the output 01 of the comparator VG 2 supplies a control signal because the sub-area ZB contains the information 01, then the clock stage 1 5 is switched on via the coincidence gate K 4. In this case, the last 100 ms cycle has not yet ended, but it should expire soon. Accordingly, in the cycle f5, the current impulse number, increased by 1, of the read sub-area WZi is transferred to the write register S-Reg 2 via the adder ADX and the switch 73, and the information 10 is written into the sub-area ZB of the write register via the counter Zb. Subsequently, the information provided in this way is then rewritten at cycle ί 8 and the end marker £ is triggered via the coincidence gate KS.

2. Call by the command generator

As already on the basis of the arrangement according to FIG. Has been explained in detail 5 are passed, the control commands stored in the memory SP2 contained in the program control section for the central data storage, where they are taken over in the input register Reg 2 sequentially with the control each counter stage in the counting register Z \ of Figure 5. When the identification address of each control command called up by the command generator is taken over, the bistable flip-flop B 3 is set at the same time, which then activates the talc stage ta . With the associated work cycle, the current identification address is first transferred to the control register ST via switch Γ10 and the corresponding memory section of the data memory SP is activated. The clock stage / 2 is then switched on and the information contained in the selected memory section is thus transferred to the read register L-Reg via the reading device L. With the following working cycle of the clock stage f 4 subsequently switched on via the coincidence gate K 6, the information read is first of all checked to determine which control state is actually present with regard to the w associated selection set at the time of the call by the central command generator. This check is carried out with a view to the possible conversion of a series of current impulses into the equivalent dialing digit using the comparator VG 2. v>

Three different work sequences are possible in this case:

a) If one of the two outputs 11 or 01 of the comparator VG 2 supplies a control signal, the chain circuit consisting of the clock stages 1 10a and f 106 is started via the mixer gate M 3 and the blocking gate S 2. Under no circumstances more than 100 ms have passed since the last current surge was recorded in the VVZ / sub-area, but at least 50 ms. Accordingly, the marking in the t> ^r i sub-area ZB for marking the time lapse is to be reduced by one unit by a further 50 ms since the last activation. With the work cycle 10a f is therefore via the switches Γ19 and 720 and the common data line DL, the read mark for presetting on the Zählschaltglied Zb and with the subsequent working stroke / IQb the decreased by one unit mark in the partial region ZZ? of the write register S-fte ^ transferred. The information changed in this way is then transferred to the selected memory section of the data memory SP with the working cycle of the clock stage 1 13. This operational sequence is completed, and with the stepping pulse of the clock circuit 13 1 via the control line the message be at the central command generator BF that has been processed by the above-mentioned control command.

b) If during the review of the sub-area ZB by the comparator VG 2 with clock ί4 it is determined that both markers have already been deleted and consequently the clock stage ί 11a is started via the locking gate S1, this is a sign that since the last arrival one Current surge have passed at least 150 ms. The recorded series of current impulses is thus ended and the dialing digit contained in the sub-area WZi is complete. With the work cycle f 11a, the counter ZE for setting the position selector we is increased by a 1 by the 1-adder AD 2 and the new value thus obtained is transferred to the setting register We via the switch Γ11 and the position selector we is transferred to the one indicated by it Partial range set for the individual digits Z1 to Zn . If it is the first digit of a dialing sequence, the digit counter SZ-E had the value zero, so that, as a result of the addition of 1 , the digit selector we is set to the subrange for the first digit Zl. At the same time, the new value is transferred via switch T 12 to sub-area SZ-E of write register S-Reg . With the following work cycle illö, the number contained in the sub-area VVZj is then transmitted via the switches Γ14 and 713 to the selected sub-area, eg Zl, of the write register and the area VVZ. turned off. With the work cycle f 12, the information provided is finally written into the selected memory section and this work sequence is thus ended, so that with the incremental pulse of the cycle stage 1 12, the message to the command generator can be sent via the BF via the control line previously communicated! Control command has been processed and can now be deleted in the command generator.

c) Finally, the output 10 of the comparator VG 2 performs the check with the working cycle / ■ a control signal, the clock stage / 9 is switched on via the blocking gate S. It is immediate ei dialing pulse has already been written in before being called up by the command issuer.

All you have to do is mark the beginning of a new 100 ms cycle. As a result, with clock f9 via the counting switch Zb, both markers in the sub-area ZB d "write register S-Reg are set and then with clock 1 13 in the controlled memory section transferred and the command execution is communicated via the control line be to the command generator £.

443 /?

In all three work sequences that have been explained above, the barrier gates Sl, Sl and S3 prevent that when there is a viachsendebefehles or when the snack is running, which can be seen from the markings in the sub-areas N and F, which were previously are initiated at all.

II. Forwarding of digits

Furthermore, it is now assumed that not a series of rushes received by the dialing network into a equivalent dialing digit, but, conversely, a dialing digit already stored in the data memory to be converted into an equivalent series of current impulses and to be sent from the elective rate.

1. Request by the output control I / O

Is instead a request for dial pulse receiving a Nachsendeanforderung present, then the instruction decoder B set the bistable multivibrator Bl via the control line s. As when setting the trigger stage B 1, the clock stages 1 1 and ti are first switched on one after the other and the information from the associated memory section is read. Simultaneously with the work cycle 1 2, however, the chain circuit consisting of the cycle stages f 14a, ί 146 and f8 is started via the coincidence gate Kl. With clock f14a, the 1-adder AD3 then increases the count of the output point counter SZ-A by a 1 and via the data line DL and the switch 74 to the setting register Wa of the output point selector wa and via the switch 75 to the associated area of the write register S - Reg transferred so that at the end of this work cycle the output serial selector wa is set to the sub-range for the first dialing digit Zl. With the following work cycle f 14b, the selected digit Zl is transferred via the switches 76 and 78 to the sub-area NS / ZW of the write register S-Reg . Furthermore, with the same clock, a marker is set in the sub-area BMx and in the sub-area N of the write register and a possible marking in the sub-area F is deleted so that the provided and changed information can be written into the selected memory section with the subsequent work cycle / 8.

This also terminates this work sequence triggered by the input and output control I / O , and the end marking E takes place at the output of the coincidence gate K 8, as in the work sequence explained in connection with the dial pulse request.

2. Call by command provider

Whether a stored dialing digit is to be sent again in the form of a series of current impulses is recognized by the marking in the memory element of the sub-area N , the corresponding sub-area in the read register L-Reg supplies a control signal via the control line η , which either the clock stage via the control gates K 10 or S4 1 18 or the clock stage 1 15 starts. Which of the two clock stages is used also depends on the marking in sub-area S that is read at the same time. This marking indicates whether or not the current control cycle of the determining memory section in the data memory SP is already synchronized with the central clock generator (not shown) that supplies the series of current impulses to be transmitted.

a) First of all, it is assumed that the forwarding command has only just been stored and that there is still no synchronization with the central clock generator. It is therefore switched on via the blocking gate S 4 when checking with the work cycle 1 4, the clock stage f 15 and checked with its work cycle - control line ρ - whether a pause or a pulse is currently being sent by the central clock generator. During this test process, the bistable multivibrator B 4 is set with the progression pulse of the clock stage f 15 and thus the coincidence gates K 18 and K 19 are prepared for the evaluation of the feedback from the central clock generator. In the event of a response via the control line / as a sign that a pulse is currently being sent, the work sequence that has been started is immediately aborted via the coincidence gate K 19 and the control command called up is reported as completed via the control line be to the command generator BF , because the transmission only begins with the next call can be initiated.
If, on the other hand , it is reported back via the control line P that a pause is currently being sent, then the clock stage f 16 is brought via the coincidence gate K 18. With the associated work cycle, the command - control line sen - is given via switch 729 to the input and output control unit I / O , with simultaneous release of the associated selection set address, to switch the central clock generator to the outgoing line in the associated selection set, so that the from this delivered control pulses thus get to the transmission. At the same time, the synchronization marking is carried out in the sub-area S of the write register S-Reg , which is then subsequently written into the selected memory section with the working cycle f 13. Subsequently, as described above, again via the control line be the Fertigmeldu ng to the control device.

b) If, on the other hand, both partial areas N and S of the read memory section contain a marking, then during the check by the working cycle f 4 via the coincidence gate K 10, the clock stage 1 18 is activated. The coming into effect of this clock stage makes a further test process necessary in order to be able to decide which of the other three possible work sequences is to be initiated, which depends on the one hand on the time monitoring information in sub-area MBx and on the other hand on the information in sub-area NS / ZW of the controlled Memory section. It should be remembered that when a forwarding command was written in , the memory element forming the sub-area MBx was marked at the same time. Is dieüe marker in the review by the working cycle 1 18 before, so this is a sign that ms have elapsed since the setting of the synchronization indicator in the partial region S until 50th So it is not yet to be expected that the first control pulse of the! The series of current impulses has already been transmitted, but will only be transmitted safely after a further 50 ms has elapsed. This second 50 ms time interval is identified by deleting the marking in the sub-area MBx . To the further

nthaltene Nachsendeziffer decreased by 1 until ler value 0 is reached: the marker in the portion MBx eitig with any deletion of the NS in the partial area / ZW i; when the corresponding one of the nachzusenlenden dialed digit number is reached from Steuermpulsen for transmission to MONITOR, is at the same is. The consequent ³ rüfvorgänge be on hand of the comparator VG 4 and the control gate 511, S12 performed and K 15th

bt) If the marking is still present in sub-area MBx , the control signal emitted by the corresponding sub-area of read register L-Reg acts directly on clock stage 1 23 via coincidence gate r> K 15 when working cycle M8 takes effect. This has the effect that the marking contained in the sub-area MBx of the write register S-Äeg is deleted and, on the other hand, in conjunction with the 1-subtractor Sub and:> o the switch Γ8, the digit read from the sub-area NS / ZW is reduced by 1 for the subsequent write process is ready again. This writing process is in turn triggered with clock (13 and then the completion of the command via the control wire be marked.

b2) If, on the other hand, there is no control signal on the control line mbx during the check by the operating cycle 1 18, because there is no marking jo in the read sub-area MBx , and at the same time the output χ of the comparator VG 4 carries a control signal because the in the sub-area NS / ZW has not yet reached the value 0, the control stage f 19 'is switched on via the blocking gate 511. This causes the time marking for the sub-area MBx to be set again in the write register S-Reg , which is then transferred to the selected memory section with the subsequent work cycle f 13. The rewriting of this time marking is equivalent to the beginning of a further 100 ms time interval, which is required for the transmission of a control pulse of a series of current impulses by the central clock generator, with the marking the first 50 ms and the deletion of the marking the second 50 ms of this time interval indicates.

b3) If the check of the control digit contained in the sub-area NS / ZW by the comparator VG 4 with the operating cycle ί 18 shows that the control digit is equal to 0, the control signal appearing at the output 0 of the comparator VG 4 in the absence of the time marking in the sub-area MBx via the blocking gate 512, the clock stage f 21 is activated. The activation of this clock stage is a sign that one of the current impulse series corresponding to the dialing digits has already been sent. The further transmission of control pulses by the central clock generator must therefore be prevented. The work cycle ί 21 reports this with simultaneous release of the address of the associated selection set via switch Γ29 to the input and output control, which then forwards this command.
The clock stage i22 is then switched on with the stepping pulse of the clock stage i21. This now causes a period of time of 500 ms, for example, to pass before the next digit is forwarded, so that successive series of current impulses can be reliably kept apart by the intermediate dialing time. The expiry of this intermediate selection time is also monitored with the aid of the NS / ZW sub-area by counting a corresponding number of control cycles. For this purpose, the sub-area NS / ZW of the write register S-Reg is loaded with the code number 10 with the work cycle (22 via the switch Γ17) and the marking in sub-area Feine is set to indicate the running of the intermediate dialing time and the marking in sub-area N of the write register is deleted . Both pieces of information are then written to the operating cycle 1 13 in the selected memory section so that thus this work order is completed and the control line be carried out the execution mark

c) With each further call of this memory section by the central command generator ßF, due to the identification in the sub-area F when checking with the working cycle i4, either the cycle stage (25) via the coincidence gate K 12 or the cycle stage (24 via the coincidence gate XIl) Clock stages come into play depends on whether the code number contained in the read sub-area NS / ZW has reached the value 0 or not. This is checked with the comparator VG 4, el) If a control signal appears at the output χ of the comparator VG 4, because the code number read is not yet equal to 0, the clock stage i25 responds via the coincidence gate K 12, which, in conjunction with the 1-subtractor Sub and the switch TS, reduces the code number read by one unit and transfers this result to the corresponding sub-area of the write register 5- Reg . The subsequent clock stage (13 then triggers again rum executes the write process for the changed information and controls the command generator via the control line.

c2) If the code number contained in the sub-area NS / ZW has reached the value 0, a control signal occurs at output 0 when checked by the comparator VG 4 with the working cycle f4, which switches on the clock stage f 24 via the coincidence gate K 11. With the working cycle of the clock stage (24, the comparator VG 5 first checks whether there is another digit to be forwarded in the sub-area Z1 to Z π. For this purpose, the counter readings SZ-E and SZA for the input and output point counters are simply combined with one another compared.

If there are no more digits to be forwarded, the control signal appearing at the output j of the comparator VG 5 is used one after the other to set the clock stages (26 and (12

-tf \ n the / ei

brought and thus the marking contained in the sub-areas F, N and S deleted, as well as communicated via the control line belö the command generator that the zuve ifgerufufene control command is done and now, or to be deleted.

If, on the other hand, both of the counter readings checked by the comparator VG 5 with clock f24 are unequal because there are still further digits to be sent stored, the clock stage 1 14a is switched on by the control signal appearing at the iu output π of the comparator VG 5. Thus, the same operation sequence is initiated, as has already been described initially, on receipt of a Nachsendebefehls via the input and output control of I / O The only difference is that now with the advance switching impulse _na α to F i R. 8 illustrates merely a ^{The Α} μΪ da's Sr the gf ichen tasks in the one example, the above mentioned difficulties

or other We, se j ^ _ß ^ ^

can be modified. ™ example!

Tasks also then fulfilled

^SedieTell DaTeSeS 5> in memory SP2 of the

instead of in. ^Ο » ⁶ ' _η 5; _{ε11ε of} the commanding device for the identification addresses ßF ^ n ^ eU _che ^^ _{wQrden for}

_tz would have to be used in the memory SP2 which could be controlled directly via the selection address through the selection register Z2 an-K r kt Fine constant start address An-ADm , ^ Ene kon _Zah , _register s Z1

Memory SPl je: -tarns ^ ^^^ ^

omitted, ^ « _rt ^d J ^ _sp ^W _eiche ; _{n> who} was the first to be singled out in a •. Since the presence 5: i cooirhpr SP 1 indicate immediately

.j ,, 7OkICtHfA i "ihf» rhaiint i ^ in

he follows . ·

wfe from the work explained above the arrangement according to Fig. 8 can be seen in connection with the command transmitter according to Fig. 5, let swh various tasks in the context of emerVermitthingsan-

situation with a single counting register of the command generator with appropriate coordination of the counting register cycle to the individual time conditions to be met in a simple manner by adding additional sub-sections used as counters, such as sub-area ZB for dial pulse integration, sub-area MBx for forwarding of Digits and the sub-area NS / ZW for monitoring the intermediate dialing time, predetermined multiples of the number register cycle are monitored. Different sub-areas can also be used in a simple manner for various tasks by means of additional tax codes, such as those represented, for example, by the tax codes in sub-areas Fund N , so that the overall expenditure on storage volume is reduced.

additional tax code MB also waived

^tet .m ^e £ s to the all Ausführungsbeis ^ len ^ erwendeten switching units in any, in itself

- Be designed in Lekan ™ way. This is particularly true? Ir a counting function performing registers for a _Ke kill circuits discrete

Eemnte can be realized as well as through SJSm adding circuit cooperating memory

aichnre. for example, analogously to the sub-area WZi Γη FiI 8 in conjunction with an adder. The clock stages used t

"rod the same can be used in place of the discreet Switching elements carried out work sequences arrangements in the same way implement the individual work sequences through individual control commands existing partial programs that are in a

Program memory are stored, can be controlled.

For this purpose 10 sheets of drawings

Claims (8)

Patent claims: 1. Central command generator for timely program-controlled functions in switching systems, in particular telephone systems, with a clock and with a memory to be queried by means of at least one counting register, characterized in that each level of the counting register (e.g. Zl) has at least one section of the memory to be identified by the counting register (SPl) is individually assigned, in the identification addresses of control commands that occur at any point in time and should only be triggered by the switching or control functions after a specified period of time or the measurement of specified time segments is to be initiated at the point in time at which the relevant Control command arises, are each written into a memory section of the memory which is assigned to that stage of the counting register that the at the time at which the control command in question, activated stage of the counting register by one of the Qu otients from the specified time period and the time period of the basic clock (Tl, T), with which the counting register is incremented, is followed by a corresponding number of stages. 2. Central command generator according to claim 1, characterized in that several counting registers (z. B. E, Z, H) are combined into a sequential circuit in which each subsequent counting register (z. B. H) with the cycle rate of the respective upstream counting register (z. B. Z) that the individual stages (z. B. 0 to 9) of the individual counting registers (E to H) assigned memory sections (SP) in addition to a subsection for the identification addresses (K-AD) of the individual Control commands have further sub-sections (e.g. a to ^, the number of which corresponds to the total number of the respective upstream counting registers, so that to measure a predetermined period of time (e.g. 0.856 seconds) for this, the setting of all counting registers (e.g. E to HJ the specific phase time of the command generator (e.g. 0.682 see) is added and the time value obtained in this way (e.g. 1.484 see), based on the largest basic clock, in whole-number multiples (4, 8, 4) of the individual counting register basic clocks ( 100, 10, 1 ms) decompose It is important that the identification address (K-AD) of the associated control command (X) is first written into a memory section of the counting register (H), which is incremented with the largest required basic cycle (100 ms) and which is assigned to stage (4) of the counting register, which is characterized by the multiple (4) of the associated basic clock (100 ms), and that in the free subsections (a, b) of the memory section determined in this way, the multiples (8, 4) of the remaining basic clocks (10 and 1 ms) as addresses for which successively the identification address of the control command together with the respective remaining multiple taking over stages (8, 4) of the associated counting registers (Z, E) are written (F i g. 4). 3. Central command generator according to claim 1, characterized in that often to trigger Occurring time-dependent functional sequences (dialing pulse integration, forwarding of digits, Display of intermediate selection times, counting according to zones) separate counting registers are provided, the number of stages (e.g. 5) each equal to the quotient from the specified time period (50 ms) and the most favorable basic cycle time selected in each case (10 ms) is (FIG. 5). 4. Central command generator according to claim 3, characterized in that the counting register (z. B. Z1) is assigned a control device through which the number of stages (eg / J _n ) of the counting register cycle can be changed, and that when the counting register cycle is shortened (eg as a result of switching the counting from night to day tariff) the memory sections assigned to the steps no longer required (eg n, + \ to n ") of the counting register are assigned step by step to the memory sections of the remaining steps (0 to n,) (F i g. 5 and 7) - 5. Central command generator according to claim 3 or 4, characterized in that the memory sections assigned to the individual stages (e.g. 1 to 5) of a counting register (e.g. Zl) for the identification addresses (TC-ADJ or the memory sections identified by these) each have a sub-section (e.g. ZB and MBx ) have, io that times corresponding to the multiple of the counting register cycle can be monitored (FIG. 8). 6. Central command generator according to claim 5, characterized in that the individual stages (z. B. 1 to 5) of a counting register (z. B. Z1) associated memory sections for the identification addresses (K-AD) or those identified by them Memory sections each have a subsection (e.g. Λ / and F) used for special identifiers, so that one and the same memory section (e.g. NS / ZW) can be used for different control functions (e.g. forwarding of digits and displaying intermediate dialing times ) can be used several times (Fig. 8). 7. Central command generator according to one of the preceding claims, characterized in that several simultaneously running or to be triggered control commands via the subsequent addresses (F-AD) of different memory sections of a further memory SP 2) are linked to each other and to the memory section permanently assigned to each stage of the counting register . 8. Central command generator according to one of the preceding claims, characterized in that that the counting registers consist of a memory section, the information content of which is periodic recurring and controlled by a basic cycle or program cycle periodically by one Unit is increased or decreased until a predetermined value is reached, the information content each designates the register level whose associated memory section is to be checked is. In switching systems, especially in telephone systems, there is often the need to carry out To make control processes dependent on the expiry of a predetermined period of time. About the dimension these periods of time are generally the switching elements that carry out the individual control processes individually assigned timing elements in the form of capacitors or from a central one