DE1801381B2 - Data display device for displaying characters in rows on a screen - Google Patents

Description

The present invention relates to a data display device for displaying characters on a row by row Screen stored in a round-trip memory whose character capacity is equal to Number of character spaces on the screen is, with a shift register that has a capacity of one Has characters and connects the input and output of the memory; a clock circuit for Generate clock signals to circulate characters in memory via the shift register during a control predetermined round trip clock cycle; a decoding circuit for individually decoding the im Shift register stored character and to activate the rows and columns of a matrix to a Generate pattern that corresponds to the character stored in the shift register and that by the Crosspoints of the matrix is defined by the interfaces of the activated by the decoding circuit Rows and columns are formed; a sampling circuit for sequential enabling of the rows of the matrix in order to transfer information into a with the for each released row Columns of the matrix related output registers control those cross points identifies which define the portion of the pattern associated with the released line; and one Circuitry for controlling the display on the screen in accordance with that in the output register stored information, the circuit arrangement for the deflection control of the screen is synchronized by the clock device with the circulation of the characters in the memory and a Includes means for line-by-line scanning of the screen, each row of characters from the screen a plurality of rows is formed, the number of which is equal to that of the rows of the matrix.

A display device is already known which has a matrix, a symbol selection logic, a circuit for Scanning the columns and rows of the matrix and a cathode ray tube to display the time to come Time has characters stored in the matrix (Proceedings of the IRE, 1961, pages 185-195). These The device requires an input circuit for entering the characters to be displayed in the operation

Matrix and to synchronize the entered characters with the sampling frequency of the tube, as this Device works in a character-by-character fashion.

There is also another display device known (GB-PS 1045 929), in which the image memory a Has character capacity which is equal to the number of characters to be displayed on the screen. at In this known viewing device, the memory is synchronized with the beam deflection.

The known display devices require a special complex circuit for addressing the characters to be displayed on the screen. In contrast, the invention has the object that the Control of a data display device without any special effort for addressing the characters of the Image storage takes place. For the solution of this object, according to the invention, those in the characterizing part of claim 1 specified means proposed. In this way it is possible for a data display device to provide a control unit which does not have any special ones suitable for addressing the characters to be displayed Clock circuits needed.

Further developments of the invention are given in the subclaims.

Details of the invention are given below with reference to an embodiment shown in the drawing explained in more detail. It shows

Fig. 1 is a block diagram for the character generator and visual display;

Fig. 2 shows part of the scanning mode of the visual display and

F i g. 3 is a timing diagram showing the operation of the memory.

At the time of visual reproduction, the register 51 acts as an input register for the display device; the character present in the register is decoded by a decoder 54 associated with the same Number of output lines (character lines) is formed, how alphabetical characters are present, Decimal digits (10) and associated signs, such as plus, minus, point, etc. The decoder 54 feeds a Matrix 55, consisting of 7 rows and 5 columns of magnetic cores. The aforementioned sign lines are connected to the cores of the matrix in such a way that when a given character line is activated through the decoder 54 all, and only those kernels, which specify the spatial form of the characters which are in state 1 are present. Thereafter, in the matrix 55, each character is represented by a spatial distribution of 7 * 5 = 35 bits reproduced.

Each start of a time calculation signal CS read from the memory 3 via the control circuit 23 causes a line counter 56 to advance one step, the counter repeatedly counting the 7 lines of the matrix in a revolving manner. The counter 56 advances one step after each memory cycle.

The line counter 56 is decoded by a decoder 57 which successively activates the lines of the core matrix, each line being supplied with energy for one complete cycle of the delay line memory, that is, until the next start of the time calculation CS, in which the next line is activated. Each output of the decoder 57 is connected to a separate interrogation line with all cores of the relevant row.

The cores of the matrix 55, which have been set to state 1, give this in bit point D 1 of the shift register 51

current characters again, this state being maintained until the bit point D 10 immediately follows and at the bit point D 1 immediately following it, the kernels of the matrix are brought into the state in which the character following in the memory is reproduced. As shown in FIG. 1, each row line of the core matrix takes effect on each of the 256 D 10 signals which follow one another during the memory circulation in which the present row is interrogated by the decoder 57. Thereafter, the contents of the interrogated core lines are transmitted to a register 59 via the five read lines of the matrix, each of which is connected to all cores of a row, which is carried out at each of the digit points D 10. In this way, during each memory circulation, the register 59 is successively filled with 256 groups of 5 bits which represent an equivalent number of horizontal sections of the display in the matrix 55 of the 256 characters contained in the memory. Similarly, on the next memory circulation, the 256 groups of bits are sequentially entered into register 59 which represent the next horizontal portion of the 256 characters, and so on for the remaining memory rotations up to the seventh.

The register 59 is a shift register in which the transmission of the shift pulses MS during the bit points D 2 to D 6 of each digit point causes the row outputs on the line 77 of the 5 bits to be output from the register during the immediately preceding one DlO bit point. The binary signals given on the line 77 directly control the illumination of the cathode ray tube 98 of the display device 8.

The screen of the cathode ray tube (Fig. 2) is divided into 8 bands RG 1 to RGS , each of which consists of 7 lines. Each band can hold 32 characters, so that the entire screen can contain a total of 256 characters equal to the contents in delay line 3. In FIG. 2, the lines of the first band are labeled L 11 to L 17, those of the second band L 21 to L 27 etc., where the first number after the letter L indicates the line and the second number indicates the line. The beam first scans the first line L 11 in the first band RG 1, then the first line L 21 in the second band RG 2 and so on, with the scan starting from the left for each line. When the scanning has ended the first line L 81 of the eighth band RGS , the beam begins to scan the second line L 12 of the first band RG 1 and then in sequence all the second lines, whereupon the process continues in successive scans.

To carry out this scanning method, the beam is controlled by a deflection control circuit 60 with a character counter 61, which delivers the signal FIRI at the end of each group of 32 digit points and the signal FIME after 256 digit points Memory circulation. It follows that the screen scanning is synchronous with the circulation of data in the memory, that is, it is completely repeated in 7 memory circulations and then repeated in each of the following circulations. Naturally, the time corresponding to 7 memory cycles is much less than the duration of the image on the screen and on the retina of the eye. It follows from the foregoing that the 256 characters circulating in memory are methodically displayed in the visual display on the screen

running from left to right, starting at the top and ending at the bottom.

When booking on the keyboard for the memory cell, the last character booked always contains the bit "i>s", which indicates the last character written in the memory. An identification sign thus appears on the visually displaying screen in the position corresponding to the "£>s" bit. If the counter 56 activates the seventh row L 7 of the matrix and if the stage RU9 contains the bit "bs" = 1 at the same time

then 5 bits = 1 were directly ir the register 59 can be entered, which are moved in the register, with eir on the screen horizontal tick appears indicating the position de: actually the last character currently in the memory; indicates. In this way, the screen offers a complete visual representation of the contents of the Delay line memory, with an exact match between the delay line and the screen is reached.

For this purpose 2 sheets of drawings

Claims (3)

Patent claims: 1. Data display device for row-wise display of characters on a screen, which are stored in a circulation delay memory whose character capacity is equal to the number of character spaces on the screen, with a shift register which has a capacity of one character and the input and output of the memory connects; a clock circuit for generating clock signals to control character circulation in the memory via the shift register during a predetermined circulation clock cycle; a decoding circuit for decoding the character stored in the shift register one by one and for activating the rows and columns of a matrix in order to generate a pattern which corresponds to the character stored in the shift register and which is defined by the crosspoints of the matrix which are defined by the intersections of the Decoding circuit activated rows and columns are formed; a scanning circuit for successively enabling the rows of the matrix in order to control, for each enabled row, the transfer of information into an output register associated with the columns of the matrix which identifies those cross points which define the part of the pattern associated with the enabled row; and circuitry for controlling the display on the screen in accordance with the information stored in the output register, the circuitry for the deflection control of the screen by the clock means being synchronized with the circulation of characters in the memory and including means for scanning the screen line by line, wherein each row of characters on the screen is formed from a plurality of lines, the number of which is equal to that of the rows of the matrix, characterized in that a line counter (56) is provided which is started by a starting character (CS) stored in the memory (3) and is stored in the shift register (51) at each storage cycle in order to cause the scanning circuit (57) to enable the next row of the matrix (55) at each storage cycle, the output register (59) of the circuit arrangement (8) for controlling the screen being the one Information is supplied in sequence that relates to each shared Row of the matrix (55) for all characters that were successively decoded by the decoding circuit (54), whereby all information relating to the pattern of the characters stored in the memory (3), the circuit arrangement (8) for controlling the screen are supplied in a total time interval which comprises as many cycles as there are lines of the matrix (55), and that each character stored in the memory contains a character start signal and the circuit arrangement (8) has a character counter (61) for counting the character start signals (Di) and for generating a first command signal (FIRI) when the counting reaches a predetermined number of characters to be displayed in a row of the screen, and wherein line shifting circuitry (60) is responsive to the command signal (FIRI) to scanning the screen a number of lines equal to the number of shifting Rows of the matrix is, which means that all rows have the same order as the rows of the screen in a cycle period can be sampled. 2. Apparatus according to claim 1, characterized in that the character counter (61) generates a second command signal (FIME) when the count reaches the capacity of the memory, the line shift control circuitry (60) responding to the second command signal (FIME) to move the scan to the next line of the first row of the screen. 3. Apparatus according to claims 1 and 2, characterized in that the screen is a cathode ray tube screen the control circuitry is electric beam intensity control circuitry and the line shift control circuitry is electron beam deflection control circuitry is.