DE1774482C - Capacitive word-oriented memory using field effect transistors - Google Patents

Description

Reading process serves as a Abfiagelcitung. 15 carrier layer of the integrated circuit, this con-

2, capacitive word-oriented memory under struktionsart therefore limits the number of

Use of field effect transistors after a carrier layer buildable memory / rush uml

Claim I, characterized in that, as required, the use of longer IYci-

Storage capacitor increases the capacitance between torber and interrogation lines at the expense of working

Senkcnanscliluß (50 D) to the bit line (26) and to create its false circuit connection (50 W) to the Bc- on elements at high work speeds.

Zugsquelle (40) are connected. 25 This object is achieved in that each

3. Capacitive word-oriented memory under memory cell made of a field effect transistor and Use of field effect transistors, after a capacitor that consists of sinking Claim 2, characterized in that it is connected to the connection of the field effect transistor. Query the word line (24) with a signal that the gate electrode with the word line, the is acted upon, which is the input source connection with the Bitlcitung and the carrier pulse has opposite polarity. Layer connection with a reference voltage source c

4. Capacitive word-oriented memory are connected and that the bit allocation when reading is used of field effect transistors after the process serves as a query line.

Claim 2, characterized in that the advantages are thus achieved that inte-

Source connection {59 S) of the further field effect 35 grated circuit design the space requirement for the transistor (50) to an additional read word- only two elements of a memory cell on the carrier line (24 L) and the sink connection (50 D) gerschicht is very small and already a larger of the same field effect transistor connected to an additional memory than many memory cells on a single borrowed bit interrogation line (26L) can be constructed and at very high speeds, which can be operated during the reading process of the read pulse 40 speed. Despite the emergency supply or the interrogation pulse is taken because of agile regeneration of the memory content. decreasing capacitor charge are read-write

5. Capacitive word-oriented memory under zyklon achievable in the range of 120 ns.
Use of field effect transistors according to a further development of the invention, claim 2, characterized by a further 45 as a storage capacitor, the capacitance between the gate field effect transistor (52), its source, sense electrode and carrier layer of a further field and carrier layer connection ( 52 S, SlD and effckt transistor, whose source connection is connected to the 52 W) the corresponding connections of the field word line, whose drain connection is connected in parallel to the bit line effect transistor (12) and whose carrier layer connection is connected to the reference and its gate electrode (52 Cf) with his 50 source connected.

Sink terminal (52D) is connected. This ensures that the memory cell is not

can be queried for deletion.

Furthermore, according to a development of the

Invention for querying the word line with one

The invention relates to a capacitive 55 Signa! applied which has the storage word-oriented memory using impuls opposite polarity.
Field effect transistors for binary coded data, so that the stored information is deleted

There are already memories with field effect transistor avoided when querying,
ren known from the following publications: Then according to a further training of the

1. IBM Technical Disclosure Bulletin VoI 8 ^6o finding the source connection of the further field effect no. 3, August 1965, pages 461 and 462 transistors to an additional word line and the AS Faber "Integrated High-Speed Read-Senkenanschluss the same field effect transistor to Only Memory with Slow Electronic Write". ^an additional bit interrogation line connected,

to which the reading pulse is supplied during the reading process

2. IBM Technical Disclosure Bulletin, Vol. 8, 65 or the interrogation pulse is taken.

No. January 8, 1966, pages 1142 and 1143, This ensures that the bipolar when applied

P. Pleshko, "Nondestructive Readout Memory Signals on the Same Line Present Kcnsinik-CeH ÜE! S £ MOS Transistors ^: μι f \ f An ^ i

V * · / Ji ' f

lft "'by the" "execution form" the clear para- priickc between the Oiielleberelch and the

The circuit is less critical, which means that the sink area does not normally affect M and

^ ^ i Ei the FehlerÖBlichkeil in operation on a by applying a positive signal to dw ι or

ClCIlVr '* "' '' '" "' VlIlWfK 1 MlIlVlIbM WllUIVIitWU KIIUi

Finally, gcrn'ilü the BrOndunji is another

f, se üß is connected, can also ™ * '? ^ Μ * ^^ ™ £ »ί

* fi is achieved that the electrical para-, It can) «" ^ gK · "Meter of the circuit can be made less critical, in which dicBuJt. JWIJ £ which leads an essential point of view in the "5 and sink normally" ^ 2SkL de au S; 5ung of memories in integrated circuit - the gate electrode is blocked, ^ i »but ditj * '· Tcchi il is where a large number of active agnaic the circuit given for control purposes below at the same time on a carrier layer can be alleviated accordingly nta

^F. .1 ,, i «n .1.1M '.» Iif »inn..rii! .Iii iii.p« nriii'.Kfihrii'.hfi- DWi working method of the in Mg- 1 gt / ciM ¹ - "·» » ''

(iben of information in the

'Pi, Ilri connection is shown in Hanu in the drawing in m ™habenerin ^ * ^' ^ by the ^ ■ „ω, α, connections in einom ernndunppmU! «FOr, ede ^^^ ί ^ ₁ . j _c de ^P "," i _1; onu, le ..., fc ™ n «M« »cls cine, SiKicter.clle for db in Spciclia is wortorgamsjcr ndI« * c ** «.

Audiiru ^ beispids' a, Save _C ™ lle, which is in Spcicl ,,, - ™ £ · -; % £% £, while "end

^P fig. 4 a, 4 b two different types of signal 35 .te "^" ggiSeSHrter SebS. During the application to the word and bit lines of the in F. g. on before "" ^^ ', ^ ,, ^^^ is shown memory for the execution of read and two cn r «b un« each _{n jn diesc] be}

Write operations in this memory and W _1n ^ i written by using the bit driver

F i Ά- 5, 6, 7 electrical circuit diagrams of three other word positions t.on ge ^ "" eoen, inuu _bit l _citU ng

AusfüUgsbeispicle of the invention mountains ₄ o Le, | JJ ^ gJende ^ nf4 _e ^a ; ^f _erscnicdcnc , provided memory cells. , "" UfnWn are shown in FIGS. 4a and 4b.

The memory shown in Fig. 1 is an array in these figures with an order of 3 X 3 - 9 memory cells 10, of which Dk Abfwgeeyiale ^ ^sina _le " _{substantially larger} , each derive from a field effect -Transistor 12 and a f * ^ ld "eZ \\ t as this in practice consists of capacitor 14. In this embodiment ^ 45 ^ phtu ^

For example, only 9 memory cells are shown, as each one has to kick. The Betneb dena ^ _Bes J _{hreibu the} Ar representation of Erfindungspnnzips enough! N the ^ J ^ J ^ '^ n upper part in FIG. 1 practice can naturally be far gröBcr? Anontaiji- ^^^ ZtzdL · 10 indicates gen such memory cells perform everyone ^^ "^ Pspeicheizelle stored Informa field effect transistor 12 in each memory" le IO corresponds 5o The ^ n ^ this sgi π * / _{Μ grc zero,}

holds a gate electrode 12 G, on which signals to ^^^^ gutvnnoto 30 are present

Control of the current flow between a source by '* e at F storing a b.na-

connection 125 and a drain _{connection 12D- voltage indicated low and the condensers} .

will give. Another connection exists to the en Nun u * d, ese P ^ _{m nichl} , _aden . _B e, m

_Support layer or the plate on which dw 55 sator ^ 14 w rd m Ejns ^ ^ _{g an}

Field effect transistors are formed in the 12 W EinsPJg? ^"1 emer _{h" heren iti}

are shown. Each of these transistors is enmjo- ^^ J ^ ^l £ 5eneator 14 is thus charged

Herter field effect transistor. Such field effect value un ^α ^ J j _{t in the} memory cell of the

As metal-oxide-semiconductor-transistors are: the '^ ™ _{nd a binary} one or a binary one

sistors known. All field effect transistors advertising 60 condensate ££ "££" he _{peich Z} elle depending on the

stored on a P-type carrier layer or a zero .mta in the H. At rest

Platelets made of silicon. The source and charge of the ^ ^B _{between LcS} e- and

Sink areas are N-doped and have a | ™ _op tations a in capacitor 14 gc-

■ planar surface. These two areas are _{Schreiboperatw Fe} , _deff ekt-Trans.stor

through a bridge on the surface of the support 65 ^s P « ^c ^ te Lad ™ ß .. of _{the condenser} .

The platelet connected immediately next to the ^ ^old ^ '^ ^r p _e i _dei iekt transistor is normally

gate electrode UG lies The field effect transistors »'fieser Fddeffe ^ ^ ^ ^^ _fuf ^

have reinforcing effect, which is to say that the gesperri u

Thus, in spite of the loss via the sink connection 12 D via the carrier layer to the carrier layer connection 12 if in the capacitor 14 a charge can be stored for a time, the capture is in comparison to the time required for an Lcsc write operation.

During a read-write operation carried out in the first word position in the memory, the corresponding word line 24 is excited with a positive pulse, as shown in FIG. 4a. This voltage is applied to the gate electrode 12 G for each transistor in the first column. The voltage applied to the gate electrode causes the bridge to conductively connect the source and drain areas in the transistor. If it is assumed that a binary one in the considered >. If the memory cell is to be stored, the capacitor 14 is charged and when the field effect transistor 12 is conductive, the capacitor 14 discharges through it and sends a signal to the BH-Icitung26, which is connected to the source terminal 125 of the transistor. This signal is sent via line 26 to an interrogation amplifier for the first bit position and can be sensed by this and transmitted to other parts of the data processing device in which the memory is used. If the word line signal is applied to the line 24 and a binary zero is stored in the memory cell, the capacitor 14 has little or no charge and the memory cranode 30 has a low potential. Then no signal is given via the conductive field effect transistor 12 on the bit line, which indicates a binary zero in the memory cell. During reading, only memory cells of the selected word are connected to the bit line and the word lines of the other memory cells are de-energized and can therefore neither apply a current to the word nor take it from it.

After the first part of the read-write cycle has ended, new information is written into the memory cells in the first column by applying appropriate signals to the bit lines 26 under control of the bit drive shown in block 22. The signals given to the bit lines 26 can represent the same information that was originally stored in the first column of the memory, but new information can also be written. The operation of the interrogation amplifier and the bit line Trcibc-r at the investor! of information signals to the image line 26 is the same as in conventional memories and is therefore not described in detail. If a binary Hins is to be written during the second part of the read / write cycle, a positive signal is given on the corresponding bit line 26. When a binary zero is to be written, the bit specification 26 remains essentially Ne / Hpolenlial. During the second part of the Lcse-Sdirciboperalion maintaining the voltage of the Schrciblcifung, as shown in Fig. 4a, and i \ cr field effect transistor 12 remains conductive between Oiicllc and sink. Thus, the signal given to the bit line 26 charges the capacitor 14 either to zero potential or to the higher positive voltage, whereby the voltage given to the line line 26 becomes a binary aspect. The writing signal on the word 24 is maintained until the capacitor 14 is fully charged. At this point the voltage on the word line drops and this takes the signal from the gate electrode 12 (7. The field effect transistor 12 then switches off and now represents a high impedance in the charging circuit. After the word line signal, the bit line signal also ends and so on it is ensured that the capacitor 14 is charged approximately to the voltage that was on the bit line at the time when the field effect transistor 12 blocked.

After completing the second part of the read-write cycle is thus a binary zero or Hins in each capacitor 14 stored in the first storage gap and the voltage at the storage anodes 30 indicates whether a binary one or zero is stored in the memory line.

One shown in FIG. The other Lcse notation shown in FIG. 4b differs from that in FIG. 4 a, insofar as the voltage of the bit line is normally kept at a positive value and a negative pulse is given to the bit line in order to reduce the voltage to zero when a binary zero is to be written into a memory cell controlled by this bit line. If in practice the impulses shown in FIG. 4b are used, a large signal emitted when the capacitor 14 is discharged during readout indicates a binary zero, and a small signal indicates a binary one. During the write part of an Ixse write cycle, there is no signal above the reference voltage of the bit line for writing a binary one, but only a negative signal for writing a binary zero.

In the scaling shown in FIG. 1, each memory cell only requires one field effect transistor and one capacitor. Since the entire circuit can be produced on a single carrier layer when using the known integrated technology, each memory cell requires only a very small area of the carrier layer, whereby a high packing density can be achieved. The memory itself is destructive memory that

This means that the information is read out every time it is read out deleted and must be rewritten if it is to remain in memory. Besides that the stored information must be regenerated periodically, as it is due to the charge of the condenser

So sators 14 is stored and this type of storage is not permanent. There are various options for regeneration. In this way, a word position in the memory can be regenerated every tenth cycle, while the other cycles for

normal memory operations can be used. In such a case the Regencralions cycle goes through all word positions one after the other. The regeneration can also be carried out periodically Reading out and rewriting of all word positions

Follow. The return frequency depends to a large extent on the size of the capacitor 14 and the for the discharge of the capacitor responsible crawling back when the field effect transistor 12 locks. The derivation takes place mainly via a

backwardly biased half-bond and, as such, is very dependent on the temperature at the point of connection dependent. Operating temperatures of clwa 100 "C are possible at lower temperatures

1774 432 (q

7 8

However, significantly longer storage times can be formed area 38 which both reach the drain connection. Since the current loss in the memory cell 12D of the field effect transistor 12 and includes the coating in the static state of the order of 14 nano-C of the capacitor fourteenth In the in F i g. 3 watts or even less, the memory can be kept in the version shown, in which the same reference at a lower temperature. 5 characters are used as far as possible

The entire memory of FIG. 1 can not pass through as an internal sink connection 12 D and forms a networked circuit on a large silicon carrier ncn coating of the capacitor 14, but it becomes a

layer can be produced. A favorable embodiment, metallized connection to the drain connection 12 D approximately example of a memory cell is in the Vig. 2 manufactured at 42, which is connected to the upper lining 14Λ of the

and 2a. The carrier layer designated by 32 is connected to the capacitor 14. As before separates

is on the entire surface with a thick layer of a thin oxide layer 14 B the covering 14 4 of

Silicon dioxide 34 covers, with the exception of the locations of a diffused N + -conducting coating 14 C, which

on the carrier layer on which connections to the other covering of the capacitor 14 are formed. the

places or individual parts are to be assembled. The carrier-to- ground connection for the capacitor 14 is made through

layer 32 is P-doped and the source and drain 15 a metallized conductor 44, the diffused

area for the storage cell (12 D and 12 S) , lining 14 C is touched.

formed by diffusion of N-conductive impurities over the surface of the carrier layer shown in FIGS. 2, 2a and 3, so that the capacitor 14 is structured in such a way that form a series connection of the capacitor. The two N + regions, which are avoided as the source «o with the capacitance, which are normally used and the sink, are connected to one another by a bridge at the backwardly prestressed connection of a surface of the carrier layer. Feldcffekf facility is available. The further connections shown in FIG. 2 are made directly to both connections of the capacitor horizontally and not vertically as in the illustration, and not over the silicon figure. 1 and from this in aluminum on the upper carrier layer 32. The connection for the condenser surface of the carrier layer, which is a part of the silicon carrier layer, a projection extends over the conduction is heavily N-doped . This type of construction is to rich, and the secure the Quellcnanschluß 12S and the transmitter, that all positively separated into the circuit kcnanschluß I2D and the gate electrode 12 does not form G existing smaller capacity in series with. The gate electrode 12 G is located by a relatively 30 to the capacitor 14 and therefore does not have the thin oxide layer 36 from the surfaces of the build-up of a large charge of this capacitor platelet :; separated. limit. Dia.e structure turned out to be advantageous

The source connection 125 is actually a counterpart to those in which 7. B. the condenser

Part of a vertically extending surface, as in Fig. 2 sator directly between an aluminum connection and

it can be seen that both the source for each field 35 of the p-dotted carrier layer with a thin

effckt transistor is formed in a row as well as the bit-oxide intermediate layer. Bc! this

line 26 forms for this row in the memory. The type of construction complicates the normal barrier layer

Drain connection 12 D is part of a larger on the surface of the P-doped carrier layer

Area with the general designation 38 in the build-up of a large charge of the capacitor that

Figures 2 and 2a. This area closes another 4 ° does not drain quickly.

right-angled section according to FIG. 2, which is designated with three further exemplary embodiments of the invention 14 C and one! the linings of the con are shown in FIGS. Each of these dcnsafors 14 forms. Immediately above that by examples differs from that in F ί g. 7 geDiffusion formed coating 14 C is a ycierter example mainly in that the thin oxide layer i4B, which forms the dielectric of the 45 capacitance, which is used to store the information in the capacitor. The second coating 14 Λ is that each storage cell is charged, the capacity of deposited aluminum. This top layer between the gate and support layer of another 14 A is connected to the metallized conductor 14 D on the Fddcffckt transistor. The surface of the carrier layer in these figures is connected. This exemplary embodiment is also advantageous to the corresponding connections 50, as integrated memory cells are produced in the memory with other capacitors 14 which require a minimum of details and are connected and ended at the ground connection in accordance with the query can be. Nevertheless, the position in FIG. 1. The carrier layer itself is connected to earth via the capacitance of a reference voltage source 40 used as a storage medium. Fcldcffekt-Transistor in each of these designs. The entire carrier layer on which the memory is formed 55 normally not as large as the capacitance of the individual capacitor shown in Fig. 1 should be connected to a reference voltage. Where a P-doticrtc backing is used it will hold the charge for such a long time. As in this case, the capacitance of the Fcldcffekt transistor is applied for this purpose can of course usually a negative bias voltage. By increasing the dimensions of the gate using an N-doped carrier layer, 6 ° clektrodcn areas can be increased, in each of which these can be connected directly to earth. Ausfülirungsbeispiclc shown in Fig. 6, 5 and 7

Another embodiment of an integrated, only the structure for one memory cell is shown,

The storage structure is shown in the sectional view of the yes part of a larger one in FIG

Fig. 3 shown. This structure is different from memory forms. As a lot of cables and individual parts

of the embodiment of FIGS. 2 and 2a in 65 in all embodiments here the same functions

take over the type of connector 12 D on the condc- tions and have the same structure, cnt-

satorl4 In the embodiment shown in FIG. 2, the reference numbers in FIGS. 5, 6 and 7 speak

this connection is carried out as far as possible by the continuous process shown in FIG. 1 used.

The in F i g. 5 only requires a different amplitude. The on the gate electrode 12GT J • two field effect transistors, one of which the given negative read signal has the wrong Polarij-j | Input transistor (field effect transistor 12) and the fact to make the field effect transistor 12 conductive züij other the output transistor (field effect transistor and thus has no effect on the field ^ 50). The gate electrode 12 G of the input transistor S effect transistor, so consequently does not delete: * | is connected to the corresponding function 24, the information stored in the memory anode 3 is its source connection 125 with the corresponding function. The one on the f bit line connected to the word line. The sink connection 12 D of the field effect source connection 50 5 given negative signal er φ, transistor 12 is to the gate electrode 50 G of the field possible but a line via the field effect ^ || Affect transistor 50 connected, the source io transistor 50, if at this time a binary one ^ §§ [connection 505 with the word line 24 and its stored on the memory cranode 30 and therefore | ψ Sink terminal 50 D connected to the bit line is a positive voltage at the gate electrode Si G ii . located. The signal on the word line then overflows | ψ If a binary one in the memory cell overall the field effect transistor 50 to the Bitabfragelcitung f Ü is to be written, is illustration in accordance with a 15 and indicates that a one in the memory cell overall \ ji, positive voltage applied to the word line 24 . stores is. If a zero is stored, the <$ H This voltage is applied to both the gate electrode gate electrode 50 G with respect to the source connection f _? W 12 G of the field effect transistor 12 as well as on the 505 not sufficiently positive to make the field · ύ M source terminal 505 of the field effect transistor 50 effect transistor 50, and it is given ψ feg. When a binary one in memory cell ao does not generate a pulse on bit line 26. To get a ^ | ¹ J is to be written, a positive pulse will optimal operation of the one shown in FIG. 5 is given to the bit line 26 and when a binary chcr cell is to be achieved, the threshold voltage I * ^r "should be written to zero, this line of the field effect transistor 50 is kept in the size with the> as shown at zero potential A binary one is to be written on the memory anode 30 in the one state. 35 Voltage and with the read pulse on the word ";" and if as a result a positive signal on the line should be comparable. B <i such a constructive * bit line 26 is added, so passes this signal Tiou is the field effect transistor 50 conductive only of the field effect transis- when the read pulse is applied to the source terminal 12 5 on the word line '· siors 12 and the sink terminal 50 D of the field is and the voltage at the storage anode effect transistor 50. At this point, 30 makes 30 is. Otherwise, memory cells that do not read the positive signal on word line 24 of the field could make the bit line "discharge" effect transistor 12 conductive, so that the signal on and part of the interrogation signal during read bit line 26 has this field effect - Derive transistor on operation. The carrier layer connections 12 W, the gate electrode 5OG of the field effect transistor 50 and 50 W, which are connected to the carrier layer, is given. Since the source 35 on which the field effect transistor is formed at this point in time, the high positive voltage of the words should also be biased as negatively as the line 24 has and the sink connection 50 D is biased on the word line 24 Reading pulse is. Dapositive voltage of the bit line, which prevents the ver field effect transistor 12 on the gate electrode 50 G connections in the field effect transistor 50 forward before the field effect transistor 50 from being tensioned during reading.

sen not conductive. In order to conduct this NPN transistor The embodiment shown in Fig. 6! To do this, the gate voltage must be more positive than it differs from the one shown in FIG. whose gate electrode is a transistor. If the field effect transistor 12 45 52 G and its sink terminal 32 D both conducts directly, but the gate capacitance of the field is connected to the storage anode 30, animal effect transistor 50 via the field effect transistor indicates voltage, whether a one or a zero in • 2 up to the voltage value of the bit line 26. Which is stored in the memory cell. The source word pulse on the word line is terminated before the bit connection 525 of the field effect transistor 52, the line pulse, so that the charge in the field 50 should ensure that the voltage at the memory _; Effect transistor 50 is stored. If during anode 30 does not get too high, a zero is connected to bit line 26 of a write operation. If the voltage at the memory j should and the bit line 26 is held at zero potential anode 30 exceeds a predetermined value, no charge will of course be applied to the gate electrode 52 G, whereby the I electrode 50 G of the field effect transistor 50 is stored. 55 Field effect transistor conducts until the voltage at the?

The information content of the in F i g. 5 shown storage anode 30 to the corresponding value

Storage cell is caused by the voltage on the storage unit. The additional installation of the field effect.

cheranode 30 reproduced. The voltage on the transistor 52 in the circuit makes its elec- i

scm point is high when a charge is less critical in the capa- ric parameter, which of course is a j

city of the field effect transistor 50 is stored, 60 important! Point of view in the production of %

which indicates a binary one. The voltage across memories in integrated circuit where is a big one

the storage anode 30 is approximately at earth potential number of active elements at the same time on one '?

tial if a zero is stored. The stored carrier layer can be made and all within

Information is read out by working the circuit's design parameters

voltage on the bit line at around zero potential 65 if the panel is to be used,

g g g p, as Tableau is to be used,

holds and on the word line 24 a negative signal without any reserve cells connected or Pro- - *,

indicates that the opposite polarity of that used during program linking techniques

the signal given to the write operation and the The embodiment shown in Fig. 7 '' i

774

Similar to those of FIGS. 5 and 6 in that only two field effect transistors are required for each memory cell sidd. This embodiment differs in that in contrast to that with only i Bili tttt

Field effect transistor 12, which the stored charge and thus the voltage at the storage anode 30 influenced.

When reading out, a negative signal is generated by

Wli 24 L

a word line and a bit line equipped 5 approximately -5 V on the read word line 24 L gevnrfif>riof> n Rekneeien here two word lines 24 S. If at this time the memory cell

g p p

stores a binary one and the storage anode 30 is at a higher positive voltage between 3 and 5 V, the gate electrode 50 G is at a positive voltage which exceeds the voltage at the source terminal 50 S by a value which is greater than the threshold voltage of the field effect -Transistor 50. This field effect transistor then conducts, so that a signal on the bit query line 26 L ge di Li hl

previous examples here two word lines

and 24 L are provided, one of which for

Reading and the other is used for writing.

Two bit lines 26 5 also exist in the same way

and 26 L, which are used accordingly. Although the use of additional word and

Bitlines the arrangement of multi-conductors on the

requires integrated circuit board, turns out to be

! This embodiment is advantageous to the extent that _ ,, ·, ·, _M

4iaft than when bipolar signals are applied to the 15 and to the connected to this line ^ same line present construction restriction interrogation amplifier is transmitted. .

⁶ - - - · ·· ---'- ^J! - If there is a signal during a write operation

the bit write line 26 S is given, the one in Fig. 7 ^ -ng.-you! ": Sneicher cell remains unaffected

FeW ^ rmödichkeit "during operation on a so flows, if not this one ^ i ^ .ikt <>'<" signal on

Minimum is decreased, as well as the ground the write word line 245 is given.

Production of large numbers of operational memory cells on a plate is facilitated. As

beforehand, it is saved by loading a

Capacitance in the circuit, mainly the capacitance

between the gate electrode and the carrier layer of the

Field effect transistor 50. When a zero in the

Storage cell is stored is the storage anode

30 essentially at zero potential when a one

same line present construction restrictions are omitted. Also through this Construction the electrical parameters of the circuits even less critical, thereby reducing both the lihki ähd d operation on one

similarity Hcher, the memory cell in a read operation is not affected, if not a signal on the read word line 24 /. ^ g? ^u - ^a n will.

The individual parts of the in Fig. 1 gc ^ cigcen Aun / -i ^u "Wu. Can be combined with those of the embodiment shown in Fig. 5. Thus, a special capacitor can be used to store the information representing charge, which then

stored they wirdhat "a positive voltage 30 to the gate electrode of a second field-effect Tranz B 5 V, the write word line 24 S is coupled with sistors to achieve read a non-quenching apparent from the gate electrode 12G of the field effect transistor 12

As explained above, in all of the embodiments shown,

Letter given on this line. The information to be written in the present invention is determined by the level of the voltage 35 information in the form of a charge on a capacity on the bit write line 26 S, which is only stored with speed in the memory cell. The charge at the source connection 125 of the field effect transistor is either connected in a separate capacitor GE-12. This line leads essentially stores or in one of the field effect traniichen 0 V if a zero is to be written and is sistors of the memory cell existing capacity, by a 'corresponding signal! at a voltage 40 tests have shown that under unfavorable conditions of about 6 V when a one is written, the charge dissipation is long enough. The amplitude of the positive signal on the
Schrcib-Wcrdeituü ", _z g 12 V ₅ must be at least
Schwellwsrtspamiung ^ which yes to the gate electrode
12 G of the field effect transistor 12 is put to 45
to make this conductive, be greater than the positive
Signal on the bit write line 26 S. With one one
Binary one representing the signal on the bit write line 26 S loads the line of the field effect transi-. _ .. stors 12 the capacitance between gate electrode and 50 follows. The regeneration does not need to form a carrier layer of the field effect transistor 50 all at once. but can be interspersed during a read-write. This charge is retained when the operation is first carried out. When applying the write signal on the write word line 24 5 and the speeds and operating modes described above then the bit signal on the bit write line 26 5 will only end 10% of the total storage time. The voltage at the storage anode 30 harbors 55 the regeneration needed and the time for one then at 5V. In addition, there is a capacity at the effective read-write cycle is less than 115 nanometers or backward biased sink connection of seconds.

gg gtg sufficient g

sam takes place, so that regeneration is only required approximately every 200 μ5. When looking at a 200 word string, read and write operations can be performed in 100 ns. So everyone can Words in memory are regenerated sequentially in periods of 20 μβ and then the memory operations executed in 180 με (1800 read-write operations) before the next regeneration cycle is carried out Di Ri b l

1 sheet of drawings

Claims (1)

1 '■ * V Another publication about the ή / Pnleninneprtiches.! Creation of field K ^ t-Transistorcn, ■ <jie in a V ₁ • I. Kupnzlilvor wortorlenticrter storage under storage mode in pcm operating Pholodoteklor ^ '■ ■ ^ Use of field effect transistors -for / be, is in the Zcilsclirift Electronic », I. Mw 1967, f, ijinilr encoded data, marked by this - ö "on pages 75 to 78, by O.P. Weckler in the ^ :, shown that each storage cell consists of an article »Charge Sloragfc Lights Hie way ior holm- ,,: ^; Fe! De (rect-Transislor (l2) and a KondcnKa- State Image Sensors «takes place,
'-JOr (M) exists, which continues with the sink connection Bin essential! when using (Ι2Λ>) the field effect transistor * is connected to field effect transistors for storage purposes that the gate electrode (12G) with the word line> o the connection of several such transistors in _iA * ;,