DE1564704A1 - High frequency transistor - Google Patents
High frequency transistorInfo
- Publication number
- DE1564704A1 DE1564704A1 DE19661564704 DE1564704A DE1564704A1 DE 1564704 A1 DE1564704 A1 DE 1564704A1 DE 19661564704 DE19661564704 DE 19661564704 DE 1564704 A DE1564704 A DE 1564704A DE 1564704 A1 DE1564704 A1 DE 1564704A1
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- Germany
- Prior art keywords
- zone
- base
- layer
- frequency transistor
- high frequency
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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- 238000000034 method Methods 0.000 claims description 13
- 239000004065 semiconductor Substances 0.000 claims description 13
- 238000009792 diffusion process Methods 0.000 claims description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- 230000008021 deposition Effects 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 claims description 6
- 238000000197 pyrolysis Methods 0.000 claims description 5
- 230000000873 masking effect Effects 0.000 claims description 3
- RMAQACBXLXPBSY-UHFFFAOYSA-N silicic acid Chemical compound O[Si](O)(O)O RMAQACBXLXPBSY-UHFFFAOYSA-N 0.000 claims description 3
- 239000000758 substrate Substances 0.000 claims description 3
- 150000001298 alcohols Chemical class 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 230000002787 reinforcement Effects 0.000 claims description 2
- 235000012239 silicon dioxide Nutrition 0.000 claims description 2
- 239000002210 silicon-based material Substances 0.000 claims description 2
- 239000013078 crystal Substances 0.000 description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- RTZKZFJDLAIYFH-UHFFFAOYSA-N Diethyl ether Chemical compound CCOCC RTZKZFJDLAIYFH-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000012159 carrier gas Substances 0.000 description 2
- 238000000407 epitaxy Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 241000575946 Ione Species 0.000 description 1
- LTXREWYXXSTFRX-QGZVFWFLSA-N Linagliptin Chemical compound N=1C=2N(C)C(=O)N(CC=3N=C4C=CC=CC4=C(C)N=3)C(=O)C=2N(CC#CC)C=1N1CCC[C@@H](N)C1 LTXREWYXXSTFRX-QGZVFWFLSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 239000012190 activator Substances 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical group [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
- H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
- H01L21/02214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and oxygen
- H01L21/02216—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and oxygen the compound being a molecule comprising at least one silicon-oxygen bond and the compound having hydrogen or an organic group attached to the silicon or oxygen, e.g. a siloxane
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
- H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
- H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
- H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Spectroscopy & Molecular Physics (AREA)
- Chemical & Material Sciences (AREA)
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- Ceramic Engineering (AREA)
- Bipolar Transistors (AREA)
Description
Die Erfindung betrifft einen Hochfrequenztransistor, insbesondere einen Silicium-Planartransistor, mit kleinem Basiswiderstand. The invention relates to a high frequency transistor, in particular a silicon planar transistor, with a small base resistance.
Es ist bekannt, planare Siliciumtransistoren mit epitaxial aufgewachsenen Schichten herzustellen. Besteht insbesondere die Basisschicht des Halbleiterbauelements aus einer auf einen als Kollektorzone dienenden Grundkörper aufgebrachten epitaxialen Schicht, so ist durch die Möglichkeit einer konstanten Dotierung im Vergleich zur diffundierten Basiszone ein besonders kleiner Basiswiderstand gewährleistet.It is known to produce planar silicon transistors with epitaxially grown layers. Exists in particular the base layer of the semiconductor component from a an epitaxial layer applied as a collector zone serving as a base body, then by the possibility of a A particularly low base resistance ensures constant doping compared to the diffused base zone.
Unterlagen {Ar:. 7 § I Abs. 2 Nr. l Satz 3 des Änderungsees, v. 4.9.196?< Documents {Ar :. 7 Section I, Paragraph 2, No. 1, Clause 3 of the Amendment Lake, v. 4.9.196? <
909850/1221909850/1221
Da dan Produkt aus Basisv/ideratand und Koliektorkapazitüt eines Transistors zwecks Erzielung einer möglichst hoch liegenden Grcnsfrequens so klein v/i ο möglich gehalten v/erdcn muß, wird die Basiszone zur Verringerung der Kollektorkapazität "begrenzt und dadurch die Fläche des pn-Übergangs zwischen · Basis und Kollektor verkleinert. Dies geschieht in der Weise, daß durch 7/cgiitsen überflüssigen Halbleitermaterial*} die bekannte Mesaforn gebildet wird. Da beim Übergang auf immer kleiner werdende Geometrien, wie- sie bei den nach der Planartechnik hergestellten Bauelementen üblich sind, hinoichtlich der Abdeckung der Basis- und Emitterzone beim sogenannten Mesaützen technologische Schwierigkeiten auftreten, wurde nach einem Wog gesucht, die gestellten Forderungen hinoichtlich der Hochfrequenzeigenschaften zu erfüllen.Since then the product is made up of a basic supply and a Koliektorkapazitüt of a transistor in order to achieve the highest possible The lying green frequency is kept as small as possible must, the base zone is limited to reduce the collector capacitance "and thereby the area of the pn junction between Base and collector reduced in size. This is done in such a way that by 7 / cgiitsen superfluous semiconductor material *} the known Mesaforn is formed. Since the transition forever smaller geometries, as in the case of the planar technique manufactured components are common, respectfully the cover of the base and emitter zone when so-called Mesaützen technological difficulties arise looking for a surge to meet the demands made with regard to the high-frequency properties.
Eg wird deshalb gemäß der Lehre der Erfindung ein Hochfrequenztransistor vorgeschlagen, bei dem die Basiszone durch eine weitere, .nichtkontaktierte, hochdotierte Zone von entgegengesetztem Leitungstyp wie die Baoiszone seitlich begrenzt ist, wobei sich die seitliche Begrenzung der Basiszone bis in die Kolloktorzone des Transistors hinein erstreckt. Durch diese Ilaßnahme wird eine begrenzte Basiszone trots Epitaxie, die nicht ohne weiteres maskiert durchgeführt worden kann, hergestellt.Therefore, according to the teaching of the invention, Eg becomes a high frequency transistor proposed in which the base zone by a further, .non-contacted, highly doped zone of opposite Line type like the Baois zone is laterally limited, whereby the lateral limitation of the base zone is up extends into the collocator zone of the transistor. With this admission, a limited base zone is created trots epitaxy, which cannot be carried out easily masked, manufactured.
909850/T221909850 / T221
■Es ließt in Rahmen der Erfindung, daß sich die Basiszone durch eine könnt ante- Dotierung auszeichnet.■ It reads within the scope of the invention that the base zone characterized by a can ante doping.
Ih einer Y/eiterbildung dec Erfindungsgedankens ist deshalb eine epitaxiale Basisschicht vorgesehen.Ih a development of the idea of the invention is therefore an epitaxial base layer is provided.
Gemäß einer besonders günstigen Ausführungsform der Erfindung beträgt die Dicke der Basiszone an ihrer seitlichen Begrenzung maximal 0,8/un und zwischen Emitter- und Kollektorzone naxir.al 0,4/un. Die Dicke der Emitterzone v/ird dabei auf ungefähr 0,4 .-um eingestellt..According to a particularly favorable embodiment of the invention the thickness of the base zone at its lateral boundary is a maximum of 0.8 / un and between the emitter and collector zones naxir.al 0.4 / un. The thickness of the emitter zone v / ird is then approximately 0.4.-Um adjusted ..
Es ist besonders vorteilhaft, wenn die Kollektorzone durch eine durch epitaktische Abscheidung auf einen nicderohnigen Substratkörper gebildete hochohmige Schicht von bestimmtem Leitungstyp dargestellt ist. Durch diese Maßnahme v/ird die ' Kollektorkapazität klein und die Kollektorabbruchspannung hoch gehalten.It is particularly advantageous if the collector zone is through one by epitaxial deposition on a non-existent one Substrate body formed high-resistance layer of a certain conductivity type is shown. By this measure the ' Collector capacitance small and the collector breakdown voltage kept high.
Es liegt im Rahinen der Erfindung, sowohl die Emitterzone ala auch die die Basiszone seitlich begrenzende, nichtkontaktierte, hochdotierte Zone durch maskierte Diffusion zu bilden.It is within the scope of the invention for both the emitter zone ala also the non-contacted, which laterally delimits the base zone, to form highly doped zone by masked diffusion.
Zur Herstellung des auf der Erfindung beruhenden Transistors wird ein Verfahren vorgeschlagen, das dadurch gekennzeichnetFor the manufacture of the transistor based on the invention a method is proposed which is characterized
90 9850/122Ί90 9850 / 122Ί
BAD ORIGSNAkBAD ORIGSNAk
ΡΛ 9/493/812 - 4 -ΡΛ 9/493/812 - 4 -
ist, daß in einen als Kollektorzono dienenden Halbleiterkörper durch maskierte Diffusion eine nicht zu kontaktiorende, hochdotierte Zone so eindiffundiert wird, daß ,sie die vorzugsweise durch epitaktischo Abscheidung auf dem .Halbleiterkörper gebildete Basiszone von entgegengesetztem Leitungstyp seitlich begrenzt, nachdem nach erfolgter Maskierung der Halbleiteroberfläche mittels einer Oxidschicht die als seitliche Begrenzung der Basiszone dienende hoch-* dotierte Zone durch v/eitere Eindiffusion von Aktivatormatcrinl von gleichen Leitungstyp verstärkt ist und daß gleichzeitig mit der Verstärkung der die Basiszone seitlich begrenzenden Zonen der die Emitterzone bildende Bereich oindiffundiert wird. Durch diese Maßnahmen wird erreicht, daß die epitaktische Schicht mit einem Minimum an thermischer Eelastung wahrend des Horstellungsprozensos beaufschlagt wird und daher die Ausdiffusion aus der Basiszone kloin gehalten werden kann. Zur Erzielung eines besonders kleinen Basiswiderstandes wird zur Bildung der Basiszone eine Epitaxieschicht mit konstanter Dotierung in einer Dicke von ca. 1 /um ' aufgebracht.is that in a serving as a collector zone semiconductor body a highly doped zone which is not to be contacted is diffused in by masked diffusion in such a way that , they preferably by epitaxial deposition on the .Semiconductor body formed base zone of opposite Conduction type limited laterally after the semiconductor surface has been masked by means of an oxide layer the highly doped zone serving as the lateral delimitation of the base zone by further diffusion of activator material is reinforced by the same conductivity type and that simultaneously with the reinforcement of the base zone laterally delimiting Zones of the area forming the emitter zone is oindiffused. Through these measures it is achieved that the epitaxial layer with a minimum of thermal Load applied during the listening process and therefore the out-diffusion from the base zone can be kept kloin. To achieve a particularly small one The base resistance is an epitaxial layer with constant doping in a thickness of approx. 1 μm to form the base zone 'upset.
Das erfindungsgemäße Verfahren ermöglicht aber auch während der epitaktischen Abscheidung die Einstellung eines beliebigen Dotierprofils. Außerdem ermöglicht es eine tiefliegende 2aci:;ione bei gleichzeitig hoher Basisdotierung unterhalb des Emitters.However, the method according to the invention also enables any setting to be made during the epitaxial deposition Doping profile. It also enables a deep 2aci:; ione with a high base doping below of the emitter.
f BAD ORIGINAL 909850/1221 ^ f BAD ORIGINAL 909850/1221 ^
PA 9/493/812 - 5 -PA 9/493/812 - 5 -
Eine derartige Strukturierung ist bei doppeldiffundierten Transistoren keinesfalls möglich.Such a structuring is with double-diffused Transistors by no means possible.
Die Bildung der für die Maskierung der Epitaxieschicht vor-'gesehenen Oxidschicht geschieht durch Pyrolyse von Siliciumenthaltenden Verbindungen mit Luft als Trägergas bei möglichst tiefen Temperaturen, beispielsweise bei 300 - 400 C. Als besonders vorteilhaft zur Durchführung der Pyrolyse haben sich die Kieselsäureester von sowohl ein- als auch mehrwertigen, niederen Alkoholen, insbesondere Kieselsaure-Tetraäthyleater, erwiesen.The formation of those provided for masking the epitaxial layer Oxide layer happens by pyrolysis of silicon-containing compounds with air as a carrier gas at as possible Low temperatures, for example at 300-400 C. They are particularly advantageous for carrying out the pyrolysis the silicic acid esters of both monohydric and polyhydric, lower alcohols, in particular silicic acid tetraethyl ether, proven.
Durch das folgende Ausführungsbeispiel soll der auf der ■Erfindung beruhende Transistor, sowie dao zu seiner Herstellung vorgeschlagene Verfahren an Hand der Figuren 1-5 naher erläutert werden.Through the following embodiment, the transistor based on the invention, as well as its production proposed methods are explained in more detail with reference to FIGS. 1-5.
Als Ausführungsbeispiel wurde die Herstellung eines npn-Silieiurr.-Planartransistors mit epitaxialer Basisschicht gewählt. Es ist aber ebenso möglich, derartige Haibleitoranordnungen mit einer pnp-Zonenfolge herzustellen. The production of an npn-silicon-planar transistor was used as an exemplary embodiment chosen with epitaxial base layer. However, it is also possible to produce such semiconductor sensor arrangements with a pnp zone sequence.
Die Erfindung kann sowohl bei Verwendung von Silicium "als The invention can be applied both to the use of silicon "as
·■■ '■■-■"'■ · . ■ - 6 -· ■■ '■■ - ■ "' ■ ·. ■ - 6 -
- - ".. -;;. - ■ ■■ 109 8 S ti tilt " : * " BAD ORiG^AL- - ".. - ;; . - ■ ■■ 109 8 S ti tilt" : * "BAD ORiG ^ AL
PA 9/493/812 - 6 -PA 9/493/812 - 6 -
auch Germanium als Halbleitermaterial angewendet werden.Germanium can also be used as a semiconductor material.
Außerdem läßt sich dan Verfahren in sehr vorteilhafter Weise auch zur gleichseitigen Herstellung einer Violzahl von Bauelementen, die auf einer Halbleiterkristallscheibe untergebracht sind, γ??--"-r.de:··. ·In addition, the process can be very advantageous Way also for the simultaneous production of a number of components on a semiconductor crystal disk are accommodated, γ ?? - "- r.de:··. ·
Die Herstellung eines npn-Siliciun-Epitaxial-Planartransistors ger.äß der Erfindung beginnt, v/ie in Pig. 1 dargestellt, mit einem n-Siliciumplättchen 1, das in bekannter Weise aus einem Einkristall hoher Dotierung herausgeschnitten wurde. Dieses Kristallplättchen v/ird in einem Ofen bei ca. 1100 C einer mit einer Dotierung versehenen SiCl.-Dampfatmosphäre ausgesetzt. Hierbei wachst eine ca. 25/um starke Schicht 2 au3 hochohmigem n-I!aterial auf, die als Kollektorzone do3 herzustellenden Halbleiterbauelements dient. Im nächstfolgenden Verfahrensschritt v/ird die Siliciumoberfläche oxydiert und dabei eine SiO?-Schicht gebildet, in die nun mittels bekannter Fototechniken und mittels Fluorwasserstoffsäure Fenster 4 geätzt werden, durch die zwecks nachfolgender Unterbrechung der später abzuscheidenden epitaktischen Basisschicht n+-Ge- > biete 5 eindiffundiert werden. Mit 3 sind die auf der Oberfläche nach der Fensterätzung stehengebliebenen Bereiche der SiO^-Schicht bezeichnet.The manufacture of an npn silicon epitaxial planar transistor according to the invention begins, v / ie in Pig. 1, with an n-type silicon wafer 1 which has been cut out in a known manner from a single crystal of high doping. This crystal platelet is exposed to a doped SiCl.-vapor atmosphere in an oven at approx. 1100 ° C. In this case, an approximately 25 .mu.m thick layer 2 of high-resistance material grows on, which serves as the collector zone do3 for the semiconductor component to be produced. In the next process step, the silicon surface is oxidized and an SiO ? -Layer is formed, into which windows 4 are now etched by means of known photographic techniques and by means of hydrofluoric acid, through which windows 4 are diffused for the purpose of subsequent interruption of the epitaxial base layer n + -Ge-> area 5 to be deposited later. The areas of the SiO ^ layer that have remained on the surface after the window etching are denoted by 3.
909850/ IIl 1 -' f bad909850 / IIl 1 - 'f bad
ΡΛ 9Λ9 3/012 - y -ΡΛ 9Λ9 3/012 - y -
In Anschluß daran wird, wie in Fig. 2 gezeigt, nach Entfernung der SiOp-Reste auf der Oberfläche des Halbloiterkristalln (1, £, 5) eine p-leitende Schicht 6 epitaktisch in bekannter Weise in einer Dicke von ungefähr 1 /um niedergeschlagen, die mittels Pyrolyse von Kieselsäure-Tetraäthylester mit Luft alG Trägergas bei möglichst tiefen Temperaturen, beispielsweise bei 300 - 4000C, mit einer SiO2-Schicht 7 bedeckt wird.Subsequently, as shown in Fig. 2, after removal of the SiOp residues on the surface of the semicircular crystal (1, £, 5), a p-type layer 6 is deposited epitaxially in a known manner to a thickness of approximately 1 / µm, by means of pyrolysis of silica Tetraäthylester with air ALG carrier gas at as low temperatures, for example at 300 - 400 0 C is covered with an SiO 2 layer. 7
In diese SiOp-Schicht werden, wie in Fig. 3 gezeigt, abermals Fenster (14, O) mittels Fluorwasserstoffsäure in den Bereich der vordiffundierten Zonen 5 (Fenster 14) und für den Emitterbereich (Fenster 0) mit Hilfe der bekannten fotolithografischen Technik geätzt, wobei die Teile der SiOp-Schicht stehenbleiben, die mit IC bezeichnet sind» Im übrigen gelten die gleichen EcEugszeichen wie in Fig. 2.As shown in FIG. 3, windows (14, O) are again etched into this SiOp layer by means of hydrofluoric acid in the area of the prediffused zones 5 (window 14) and for the emitter area (window 0) with the aid of the known photolithographic technique, wherein the parts of SiOp- Sc hicht stop, which are denoted by IC "Incidentally, the same EcEugszeichen apply as in Fig. 2.
Dann wird die in Fig. 4 dargestellte Emitterzone 9 gleichzeitig mit der n-f-IIachdiffusion der äußeren Umrandung der p-Basissone 6 durch Eindiffundieren von Phosphor in einer PpOr-Atmosphäre hergestellt. Hierbei wird die vor der epitaktischen Abscheidung zwecks Unterbrechung der p-Zone gebildete, n+-diffundierte Zone 5 durch eine weitere Zone 15 von gleichem Leitungstyp verstärkt. Zur gleichen Zeit erfolgt auch die n+-Ausdiffusion aus dem Substrat (1, 2). Die übrigen Bezugsseichen haben die gleiche Bedeutung wie in Fig. 3. The emitter zone 9 shown in FIG. 4 is then produced simultaneously with the nf-IIachdiffusion of the outer border of the p-base zone 6 by diffusing in phosphorus in a PpO r atmosphere. In this case, the n + -diffused zone 5 formed before the epitaxial deposition for the purpose of interrupting the p-zone is reinforced by a further zone 15 of the same conductivity type. At the same time, the n + out-diffusion also takes place from the substrate (1, 2). The other reference characters have the same meaning as in FIG. 3.
9 0 9 8 5 0 / 1 22 1 RAD 0R',6f?4AL.9 0 9 8 5 0/1 22 1 RAD 0 R ', 6f? 4AL.
Pig. 5 zeigt, der besseren Übersicht regen etwas vergrößert, einen gernäß der Erfindung hergestellten Siliciura-Planartransistor ohne Kontaktierung und ohne SiOp-Schicht. Ec gelten die gleichen Bezugαζeichen wie in den übrigen Figuren. Zur Fertigstellung des Halbleiterbauelements werden nach Freilegung von Basis und Emitter mittels fotolithografischer Ätzung die Ohn'cchen Kontakte durch Aufdampfen von Gold, Nickel oder Aluminium im Vakuum angebracht. Die durch zusätzliche Diffusionen entstandenen Bereiche 5 und 15 bleiben ohne Kontakte.Pig. 5 shows, somewhat enlarged for a better overview, a Siliciura planar transistor produced according to the invention without contact and without SiOp layer. Ec the same reference symbols apply as in the other figures. To complete the semiconductor component, the base and emitter are exposed by means of photolithographic Etching of the little contacts by vapor deposition of gold, Nickel or aluminum attached in a vacuum. The additional Areas 5 and 15 resulting from diffusions remain without contacts.
Will man, wie z.B. bei integrierten Schaltungen, den Kollektorkontakt an der Oberseite des Kristalls anbringen, dann kann man die Kollektorkontaktierung im Bereich 15 anbringen.If you want the collector contact, as is the case with integrated circuits attach to the top of the crystal, then you can attach the collector contact in area 15.
Durch die Lehre der Erfindung ist die Möglichkeit gegeben, unter Anwendung der Epitaxie für die Herstellung des Basisbereiches und mittels an sich bekannter Verfahrensschritte in der Planartechnik Hochfrequenztransistoren mit besonders kleinem Basiswiderstand herzustellen. Durch die in besonderer V/eise gestaltete Strukturierung, vor allem der Abgrenzung der Basiszone, durch zusätzlich durchgeführte Diffueionsprozesse ergeben sich Vorteile, die bei doppoldiffundierten Transistoren der herkömmlichen Bauweise keinesfalls gegeben sind.The teaching of the invention makes it possible to use epitaxy to produce the base region and by means of process steps known per se in planar technology, high-frequency transistors with particularly produce a small base resistance. Due to the special structuring, especially the delimitation the base zone, through additional diffusion processes carried out there are advantages that are by no means given with double-diffused transistors of the conventional design are.
14 Patentansprüche
5 Figuren. -Q-14 claims
5 figures. -Q-
9 0 9 8 5 0/1221 BAD ORIGINAL9 0 9 8 5 0/1221 BAD ORIGINAL
Claims (1)
Trüger/bei möglichst tiefen Temperaturen, beispielsweisegas
Weaker / at the lowest possible temperatures, for example
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DES0105812 | 1966-09-12 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| DE1564704A1 true DE1564704A1 (en) | 1969-12-11 |
Family
ID=7526887
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE19661564704 Pending DE1564704A1 (en) | 1966-09-12 | 1966-09-12 | High frequency transistor |
Country Status (3)
| Country | Link |
|---|---|
| DE (1) | DE1564704A1 (en) |
| FR (1) | FR1551938A (en) |
| NL (1) | NL6710792A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3302025A1 (en) * | 1983-01-22 | 1984-07-26 | Telefunken electronic GmbH, 6000 Frankfurt | Process for producing an epitaxial-base transistor |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3604986A (en) * | 1970-03-17 | 1971-09-14 | Bell Telephone Labor Inc | High frequency transistors with shallow emitters |
-
1966
- 1966-09-12 DE DE19661564704 patent/DE1564704A1/en active Pending
-
1967
- 1967-08-04 NL NL6710792A patent/NL6710792A/xx unknown
- 1967-09-08 FR FR1551938D patent/FR1551938A/fr not_active Expired
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3302025A1 (en) * | 1983-01-22 | 1984-07-26 | Telefunken electronic GmbH, 6000 Frankfurt | Process for producing an epitaxial-base transistor |
Also Published As
| Publication number | Publication date |
|---|---|
| NL6710792A (en) | 1968-03-13 |
| FR1551938A (en) | 1969-01-03 |
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