DE1564148C3 - Process for the production of integrated semiconductor devices - Google Patents

Description

The invention relates to a method for producing integrated semiconductor devices, in which the consisting of several contacted zones of different line types, electrically against each other isolated semiconductor components in trough-shaped recesses lined with an insulating layer of a substrate can be formed by the depressions of the substrate with a monocrystalline highly doped semiconductor layer of a certain conductivity type, followed by a more weakly doped one Semiconductor layer of the same conductivity type and with further semiconductor zones forming the components fill out.

The more recent development in semiconductor technology is moving towards miniaturization of semiconductor arrangements, in order to achieve higher operating speeds, lower manufacturing costs and greater component reliability. In one manufacturing process, multiple semiconductor devices are incorporated into a single substrate made of the same material as the semiconductor components. With other manufacturing processes the semiconductor components are formed in a substrate made of any material. These

ίο Manufacturing processes are extensively developed, about the installation of semiconductor components in large and complex electronic systems, such as e.g. computers, and thus to increase the working speed. However, about the cost The manufacture of the individual semiconductor components for the computer must be improved Process for the series production of large quantities of active circuit elements are developed. The individual components contained in a substrate must be electrically isolated from one another so that any electrical connections can be made to each other and to the outside world.

Various semiconductor devices are used to isolate each of a plurality of semiconductor devices on a single substrate Isolation process used.

It is known that each of the individual semiconductor components is replaced by an additional one in the reverse direction electrically isolate the prestressed PN junction. A disadvantage of this insulation technique is that the reverse biased PN junctions represent an undesirable capacity that the Properties of the circuits are known to have a very unfavorable effect.

Another insulation technique consists in placing electrically insulating material between the semiconductor components to provide in such a way that electrical short circuits between two or more of the semiconductor components be prevented. The present method is directed towards this type of isolation.

In the production of integrated circuit arrangements, which consist of several electrically separated Semiconductor components exist, it is often useful to make the electrical connections to the individual to produce active layers of the semiconductor components in such a way that the impedance of the current paths is as low as possible.

It is known that a sub-collector area with a higher concentration of impurities as a result of higher Conductivity as a collector area can be created around a low impedance path to build. It is advantageous to use this principle in the production of integrated circuit arrangements, and to conduct the collector current through a highly conductive sub-collector area. When using Due to the construction of an NPN transistor, the subcollector area is a highly doped “N +” area that is connected to adjoins the collector area. The collector current flows from the collector area into the highly conductive one "N +" range and finds a path with low impedance. One connected to the "N +" area electrical supply line therefore represents a current path with low impedance.

When building integrated circuits with transistors of the NPN type, it has already been proposed that by diffusion an “N +” zone through the collector area of planar transistor structures and thus create a connection to the "buried" "N +" area. Through this

Diffusion process, however, in many cases either the existing PN junctions are destroyed or the interfaces of the PN junctions during the diffusion process taking place at high temperatures badly damaged or distorted.

A method is also already known in which integrated semiconductor arrangements are produced with semiconductor components that are insulated from one another and consist of several zones of different conduction types. For this purpose, trough-shaped depressions are produced in the surface of a substrate and these are lined with an insulating layer. Subsequently, polycrystalline silicon is applied as a carrier substance to the surface lined with the insulating layer and the original substrate is ground off from the underside until the insulating layer is exposed. The semiconductor islands remaining within the insulating layer are then provided with the further semiconductor zones which form the desired component. A version is also provided for this procedure, ¹ J ^); in which a flat, highly doped semiconductor zone is introduced into the surface of the substrate before the trough-shaped depressions are made in the substrate. After completion of the arrangement, this flat, highly doped zone forms a layer within the isolated semiconductor islands and can be used as a sub-collector. This method, too, has the disadvantage already described that this flat, highly doped zone cannot easily be contacted. .

It is therefore the aim of the invention to provide a method in which highly conductive subcollector areas during the process in a simple manner reaching to the surface of the semiconductor device be designed so without the previously necessary step of diffusing in a highly conductive Zone to be able to contact the sub-collector area.

To solve this problem, a method proposed for the production of integrated semiconductor devices of the type mentioned that the highly doped semiconductor layer is introduced into the depressions of the substrate in such a way that it is up to Surface of the substrate is sufficient and that it is contacted on the surface.

A particularly advantageous embodiment is that for introducing the highly doped Semiconductor layer in the depressions of the substrate in a correspondingly highly doped semiconductor layer generated depressions arranged in a grid-shaped pattern by photolithographic etching processes, these depressions and the remaining surface of the highly doped semiconductor layer with the Insulating layer and a semiconductor layer serving as a substrate are coated and that then the highly doped semiconductor layer up to the the depressions of the semiconductor layer filling parts of the substrate is removed that then from the islands of the highly doped semiconductor layer remaining in the depressions of the substrate by photolithographic Etching process trough-shaped depressions are etched out, so that the in the depressions of the substrate remaining highly doped semiconductor layer up to the surface of the substrate is enough, and that these trough-shaped depressions then epitaxially with the semiconductor zones of the Semiconductor components are filled.

The monocrystalline, highly doped, cup-shaped semiconductor layer reaching to the surface of the substrate can be used in a manner known per se as a sub-collector for contacting the following can be used as a collector serving semiconductor zone.

In order to avoid warping or cracks in the semiconductor arrangement during the manufacturing process, it is advantageous for the individual layers

ίο Material with roughly the same coefficient of thermal expansion used.

The method according to the invention is explained in more detail below with reference to the drawing. It shows F i g. 1 is a diagram of the process sequence, which in cross section a semiconductor arrangement during represents the individual stages of the manufacturing process according to the invention and

2 shows a cross section through the finished semiconductor arrangement.

ao In the one shown in FIG. 1 shown scheme of the process flow a substrate 10 is shown as the first step, which is used for epitaxial growth of a monocrystalline Semiconductor material is suitable and preferably consists of a highly conductive material.

The highly conductive substrate 10 forms the sub-collector area in a later process step. A The preferred material is highly conductive silicon, which is produced in the conventional crystal pulling process from a corresponding melt is drawn. Then the single crystal is cut into slices so that you can a relatively large surface 12 is obtained on which the subsequent growth and coating steps should take place.

In step 2, a masking layer 14, preferably made of silicon oxide, is placed on the surface 12 of the substrate 10 either by pyrolytic coating or by conventional thermal oxidation processes at temperatures between 950 and 1200 ° C applied. An etch-insensitive material is then created by photolithography Brought to the oxide layer 14 in a grid-like pattern. In this grid-like pattern are the intersecting or perpendicular lines on the silicon dioxide layer free of the etch-insensitive material, but the intervening surface parts the oxide layer 14 covered. A subsequent etching process does not remove this from the etch-insensitive one Material covered silicon dioxide removed, so that grid-like channels in the oxide layer 14 arise on the surface of the substrate 10. Then through the grid-like channels in the Silicon dioxide layer 14 through from the monocrystalline silicon substrate 10 corresponding channels 16 etched out.

For etching out the channels in the SiO, layer 14 can e.g. B. a solution of HF can be used. A suitable etching solution for etching the channels in the substrate 10 is a solution of nitric acid, acetic acid and hydrofluoric acid and is set in terms of volume composed of five parts of nitric acid, two parts of acetic acid and one part of hydrofluoric acid. on In this way, channels of any depth can be etched into the substrate 10. Is the one you want When the depth is reached, the etching solution is either diluted or the entire structure is sprayed off to cope with the etching process to stop.

In step 3, a silicon dioxide layer 18 is formed

5 6

be introduced onto the surface of the substrate 10 and into the ca 1 percent by volume; prevent this

näl 16 generated. The silicon dioxide layer 18 is used for nucleation or growth of the

as an insulating layer and, like the masking monocrystalline silicon, can be applied to the masking

approximately layer 14 are produced. layer 22.

In step 4, a carrier layer, the preferred 5 In step 9, after the SiO ₂ layer 22 consists of polycrystalline silicon, has been removed by etching, for example, a base growth is applied 32 of the silicon dioxide layer 18 towards the collector area 30. The polycrystalline silicon layer is now used as a conduction type in the collector region 30, rather than diffused or alloyed in the further process (steps 5 to 10). A di-substrate forms. io den structure. The basic diffusion can be caused by

In step 5, the masking and diffusion process that originated in step 4 is therefore used

dene structure reversed, so that the substrate 20 takes place,

located below. If a transistor structure is required,

In step 6, a subsequent emitter diffusion or -Ie-

or a combination of both methods the largest 15 yawing process an emitter area 34 in the base area

Part of the original substrate 10 including rich 32 so that one can have multiple semiconductor transistors

the flat raised portions of the silicon dioxide layer on a single substrate 20. The emitter

18 eliminated. There are areas of the polycrystalline area 34 is of the same conductivity type as the KoI-

Substrate 20 exposed. Selective etching enables the detector area 30. The emitter diffusion can through

The flat raised portions of the SiO, layer use conventional masking and diffusion processes

can be left in order to reduce capacitive effects.

adorn, and then a SiO ₂ coating with the F i g. 2 shows the final structure of a half-illustrated opening, as described below, which is produced with a protective layer 36. of a suitable material, such as. B. one on

A third silicon dioxide layer 22 will be placed on the glass layer formed 25 of an oxide layer, best-free polycrystalline silicon regions 20. Lines 38, 40 and 42 are applied to the highly conductive monocrystalline silicon base region 32, the emitter region 34 and the sub-regions 10. Connected through a suitable masking collector region 28 of the transistor, and etching processes are made in the layer 22. For this purpose, for example, holes are produced in genes 24 above each of the highly conductive regions 10 of the protective layer 32 and aluminum or is produced. The SiO ₂ -ScMdIt 22 partially extends another suitable electrically conductive material also over the highly conductive areas 10, whereby an important function, described below, is evaporated through a mask inside the holes in order to fill individual electrical contacts. . to each of the active areas of the semiconductor device

In step 7, the highly conductive monocrystalline 35 device is produced. Since the individual electric

Silicon area 10 partially etched away so that lines to the sub-collector areas instead of to

A thin sub-collector area remains, which is led to the collector areas

Silicon dioxide layer 22 extends out. As a low-impedance Ätzlö- path for the collector current. the

Solution is the approximately cup-shaped insulating layers 18 and SiO _{2 in connection with the etching of the mesh}

ters in the original substrate 10 described solder 40 are used for mutual electrical separation of the

sung used. This etching solution etches the SiO ₂ semiconductor components.

Layer in the time in which the desired amount of As an example of the small dimensions of the substrate 10 is eliminated, not gone. A F i g ensues. 2, it should be mentioned that the hollow under the edge 26 of the SiO ₂ layer final platelet thickness is approximately 200 μm, the depth 22 which delimits the openings 24. A region 28 45 of the final transistor structure about 8 μm, that of the original substrate material 10 remains, depending on the depth of the base region, about 2 μm and the depth of the back and extending to the bottom of the emitter region was about 1.5 μm. It should be clear to the specialist oxide layer 22 that diodes (as in

Step 9 shows a single crystal silicon layer, field effect transistors and others

rich 30 epitaxially on the monocrystalline silicon 50 semiconductor components also according to the invention

Subcollector area 10 deposited. He instructs the proper procedures within an integrated

the same conductivity type as the sub-collector area 10 semiconductor device can be produced,

but contains a smaller concentration of A significant advantage of the invention

Defects and serves as a collector area. The process is the formation of the interface between

drive the epitaxial growth of thin sub-collector area and collector area shortly before

Silicon layers are known; it is Z. B. described end of the process, especially after the coating

in the article “Epitaxial Silicon Films by the Hyung with polycrystalline silicon, so that a temperature

Drug Reduction of Silicon Tetrachloride «prevents this transition from temperature distortion and

H. C. Theurer in "Elektrochemical Society", vol.

108, p. 649, from 1961. In the 60 listing between subcollector and collector area

A small amount of HCl can be sustained by steam gas flow.

1 sheet of drawings

Claims (2)

Patent claims: 1. A method for producing integrated semiconductor devices, in which the from several Contacted zones of different types of conductors, which are electrically isolated from one another Semiconductor components "in trough-shaped, with an insulating layer lined recesses of a substrate are formed by the Wells of the substrate with a monocrystalline highly doped semiconductor layer of a certain Conduction type, a subsequent more weakly doped semiconductor layer of the same Line type and filled with further semiconductor zones forming the components, characterized in that the highly doped semiconductor layer (28) in the depressions of the substrate (20) is introduced in such a way that it extends to the surface of the substrate (20) is enough and that it is contacted on the surface. 2. The method according to claim 1, characterized in that that for introducing the highly doped semiconductor layer (28) into the depressions of the substrate (20) in a correspondingly highly doped semiconductor layer (10) by photolithographic Etching process produces depressions (16) arranged in a grid-shaped pattern; these depressions and the remaining surface of the highly doped semiconductor layer (10) with the Insulating layer (18) and a semiconductor layer (20) serving as a substrate are coated and that then the highly doped semiconductor layer (10) up to the recesses (16) the semiconductor layer (10) filling parts of the substrate (20) is removed that then from the islands of the highly doped semiconductor layer remaining in the depressions of the substrate (20) (10) trough-shaped depressions are etched out by photolithographic etching processes so that the highly doped semiconductor layer remaining in the depressions of the substrate (20) (28) extends to the surface of the substrate (20), and that these trough-shaped depressions then filled epitaxially with the semiconductor zones (30, 32, 34) of the semiconductor components will.