DE1562123A1 - Circuit arrangement for controlling the establishment of a connection in a telecommunications, in particular telephone switching system - Google Patents

Description

009808/0750

:-No. 8064 ISE / Reg. No. 3810

2-1 Case: A.Lauwers-M.van Brussels

Fitel: Circuit arrangement for controlling the establishment of a connection in a telecommunication system, in particular a telephone exchange

List of I - control circuit Designations Reference Original language / $ / E translation / (/ D sign link I. input (junctor circuit) input marking terminal entry 0 output Xjunetor circuit) decoupling diode rectifier exit JUO junctor circuit relay Connection set LIC line circuit make contact (of relay Hr) Subscriber circuit OTO outgoing trunk circuit input control terminal outgoing connection line diode rectifier transmission 3T1 ... ST4) relay 3T5 ... ST8 I switching stage make contact (of relay Lkr) Coupling stage rni ΦΙΙ1 ^ first selection circuit ΤΜ4 ) output marking terminal Marker a, b, c, d, e ") output control terminal k, l, m, n, o ) second selection circuit Intermediate line Π, Fl, H, J make contact Marking input ά11, ά12 marking lead: Decoupling diode Mr control lead relay hi, h2 relay Make contact (of relay Hr) Q1 make contact (of relay Lar) Control input d »1, d'5 009ff08 / 07b0 diode Lkr relay Ik Make contact (of relay Lkr) Sd first selection circuit "πιο ΈϊΟ Λ Mark exit Control input S02 second selection circuit; r, s, t, lt, ^
T1, T2, T, T35 Working contact 6th Marking vein q Control core Lar relay la Make contact (of relay Lar) * - 39 -,

- 39 -E - No. 8064 ISE / Reg. No. 3810

A.Lauwers
Case:

1 RR 7 1 7 ^

-M. van Brusse!

Trunk 2

Title ι circuit arrangement for controlling the connection setup in a telecommunication system, in particular a telephone exchange

Directory of the row wire Designations Row wire Relation··" UnprungMlanguage / P / E Translation / f / D sign column or input marking Columns or markings .; _; . Brat relay wire relay gang wire Γϋ, 1/41, $ ...) common output terminal common exit d1.4 / d1.8j J diode rectifier output marking lead diode Marking output wire d5.1 ... d5.29; Input marking terminal Marking input d5.4 ... d5.32) input entry Lar1 / Lar5 · · · outlet exit Iiar4 / Iiar8i
Lkri ... Lkr29.
Lkr4 ... Lkr32 code store circuit Relay winding ^j Code memory Ia1 / la5 «··
Ia4 / la8j selection or decoder circuit Working contact (of the above Decoding circuit UrI ... Ik29. · ♦ relay winding relay winding the relay Relay winding Uc4 ... 1k32 <make contact make contact Working contact (of the above al, a2) j the relay) Id ... k8) ) diode rectifier Diode I. c1 .. «c4) row wire Row wire I 9 · · · · t7 * t "y column wire Column wire I. b1 ... b4)
11 ... 14) code store bistate device bistable code memory switch g1 .., g4 enabling bistate device preparatory bistable I. H1 ... H4)
J1 ... J4) Circuit I. 11, 12 - 40 - I. 01, 08 0S01 00 980.8 / 0 750 001 Ltr1 ... Iitr4 It1 ... lt4 d1 ... d4 U, V x, y BS1, BS2 BS3

E no. 806 »ISB / Reg. No. 3810

A.Lauwers-M.van Brussels 2-1 Case:

Titles circuit arrangement for controlling connection establishment in a telecommunication system, in particular a telephone exchange

List of terms used

fteiug ·· sign

Original * prunflwproche / # / E

Translation ^ D

OSCA, OSOB DOi., DOB

DOAB

AHD gate

individual code store ciroui

individual decoder or selection circuit

common decoder or selection iirouit

ooA, cob σ individual check circuit ΟΟΑΒ BS1 ... BS5 common check circuit BS6 single block 1 ... G8,) code bistate device 9 ... G12 ) enabling bistate device bar ra AND gate EIr relay rl contact (of relay ear) 1 ... 11 relay 1 ... h1 contact (of relay EIr) 1 ... g32 row wire 1 ... d32 column wire 1, Ea ... Bh output marking lead f1f J5 »2 Ϊ diode rectifier »1, z'2) first potentiometer circuit »A, B ^M h. make contact resistance

TJHD-Gate individual Oode store individual decoding management

common deodorant circuit

individual test circuit common test circuit, single block bistable code memory circuit preparatory bistable

circuit

UMD gate

Beiais

Contact (of the Relais Bar) Beiais

Eontakt (des Beiais EIr) Row wire column wire marker output wire diode

first voltage divider

Working contact ^ resistance

009808/0750

E no. 8064

ISB / Re ₈ . No. 3810 A.Lauwers-läl
Case:

el 2-

Tltth Circuit arrangement for controlling the connection setup in , a telecommunication system, in particular a telephone exchange

List of terms used

!•train·* sign

translation ^ D

\ PD1, PD2, PD3 R2, Hi .. "El Rar, · .Hhr
ra ... rh

Hir ... Slr

R3

R'i ... E "l H" a ... E'h

potential detector circuit

second potentiometer circuit

relay

change-over contact

relay

change-over contact

resistance potential evaluator second voltage divider Eelais

Changeover contact (above

Relay)

Relay.

Changeover contact (above

Relay)

resistance

009808/075 ^

Claims (1)

_ 51 - "" "T567T23 ' ISB / fceg. 3810 Patent claims Circuit arrangement "no control of the connection setup in a telecommunications, in particular telephone switching system, whose coupling network is provided with a view.!" Inputs of different Xtps, for example S-subscriber circuits, connection «Bate inputs _$ connection sats outputs, furthermore with a number of switching network _{connection paths of different 3Jyps 9} the Sirian pairs τοη inputs of different lyps and over one or more switching stages -proceed, also ■ It inputs of different types at at least one end of the Yerbin & ungawege and sit a number of markers, because & mreh marked «that the markers (XH ₉ Q £ 1 to 3314) are each assigned to control inputs (I ₉ O) or specific coupling _{stages (SH 9} ST5s SOJS ₉ ST6 $ Sf3» SI7 | S3W-, 8T8) and to these are connected, the connection paths belong to different fTps 2. Circuit arrangement according to claim 1, characterized in that each marker _{selects one of its marker outputs (P2 S} P2; G) which are connected to the associated inputs (I ₉ 0) or to the marker _{inputs (H 9} J) of the associated specific coupling stages . 3. Circuit arrangement according to claim 2, characterized in that each marker has a number of marker outputs which are mmlmmmu & am- equal to the total number of assigned inputs or / equal to the sum of the marker inputs of the assigned specific coupling stages. January 15, 1968 Krü / H - 52 - 009808/0750 ISB / fieg. 3810 4 «circuit arrangement naoh claim 3» characterized in that that each marker (0311) that is selecting one of its bits the marking inputs (H, J) of the associated double stages connected to the marking outputs, has marking outputs, of which at least one (G) with at least two marking inputs, one in each case at least two of the associated specific Eoppelstufe (Sl 1, 615) is connected. 5. Circuit arrangement according to claim 4, characterized in that that each marker (TM), which causes the selection of one of its marker outputs connected to the assigned inputs, with its marker outputs (F2, P2) to certain (I, 0) these inputs is connected. 6. Circuit arrangement according to claim 5 »characterized in that the double stages of each connection path are in legs between these inputs and that the markers produce a connection path in such a way that the marker (3K) marking the inputs at one end of this connection path is first put into operation and for so long is kept in operation as long as the connection path must remain switched through, while the markers (TM1 to TMM-) marking the coupling stages for this connection path initiate the successive response of the switching elements connected in series in the coupling stages associated with this connection path. 7. Circuit arrangement according to claim 2 to claim 6, characterized in that each marker, the selection of one of the assigned inputs causes two selection circuits (801, SC2). - 33 - 009808/0750 ISE / Äeg 3810 8. Circuit arrangement according to claim 2 to claim 6, characterized marked »that a) the selection circuit of each marker (IM, TM1 to TMM-) has an Oodespeioher (GSOA), a first decoder circuit; (DCAB) and a second Heodier circuit (BOA) comprises that b) the first decoder circuit (DOAB) has a number of marking elements (Ltr1 to Ltr32) each with a first input, a second input and at least one output which is arranged in a two-dimensional matrix are that c) in this matrix the first inputs of the marking elements line by line on line wires (11 to 11), the second Entrances of the marking elements column by column on column wires (al to hl) connected and the marking outputs (g1 to g32) through the outputs of the marking elements are formed that d) the second decoder circuit (DOA) has a number of inputs and has a number of outputs, the outputs being the row and column wires of the two-dimensional Control matrix and these inputs are connected to the code memory (CSOA) that e) the code memory the identifier of one of the marking outputs stores and, based on the storage of such an identifier, a corresponding row wire and a corresponding one Column wire of the matrix and thus a marking element arranged at the intersection of these wires excited which grants access to that marker output whose code word is in the said Oodespeioher was saved. - 34 00 980 8/07 50 - 34 -ISB / Reg. 3810 ^: ' 9. Circuit arrangement according to claim 8, characterized in that that each marking element has a lelaie winding (Ltri to Ltr32) and a diode (d1 to d32), which, connected in series, between the first ÄLngang and the »riding J & ngang this one Harklerelements lie, and the Harkierrelais is formed by at least one normally open contact (It1 to It32) and that one spring of the normally open contact is connected to an output (g1 to g4) of the marking element and the other is connected to a marking voltage source, so that after the Uarkierrelals a Harkler potential is applied to the output of this marking element. 10. Circuit arrangement according to claim 9 »characterized in that ■ that in each HarkLerer (ISH) initiating the selection of one of the associated operations, the other! Or the normally open contacts (r, s) belonging to the Harkler relays are connected in groups, with each group having contacts belonging to different Beiais, that furthermore dl · Contacts of each group each connected in parallel and in series with a certain second working contact (H, T2) on dl · Harkier voltage source are connected and that a second selection circuit (S02) initiates the selection of one of these second working contacts 11. Circuit arrangement according to claim 3 to claim 10, characterized marked that a) each coupling stage (SSI to S58) by a number of coupling elements (Iar1 to Lar6; Lkr1 to Lkr32) each with one first input, a second input and an output is formed, which are arranged in a second two-dimensional · η matrix that - 35 - 009808 / 07SO 5810 . b) the first inputs of the coupling elements line by line Row wires, the "wide inputs of the coupling elements * column by column to marker input or column wires CgI to g4) and the outputs of the coupling elements are connected column by column to common outputs (b1 to b4; 11 to 14), and that ·) The simultaneous creation of a control character on one Row wire and a marker to a column wire through the associated marker the first input and «ride input of a coupling element arranged at the intersection of these wires is excited and thus causes the response of this coupling element, which its output * gang around the assigned common output (b1 to b4j 11 to IA-) with a corresponding potential. 12 «Circuit arrangement according to Claim 11, characterized in that that each coupling element has a Belais winding (Lar1 to Lar4 | Lkri to Ikr32> and a diode (d1,1 to d 1,4; d1 to dJ2), both in series between the first input and the second input of this coupling element are located, and the coupling relay is formed by a working contract (Ia1 to Ia4 $ IkI to Ik32) and that this working contact is on on the one hand the connection point of the relay winding with which the diode is connected and, on the other hand, to the output of the coupling element. 13 · Circuit arrangement according to Claim 8, characterized in that that the outputs of the second decoding circuit (DCA) are each connected to a Beiais (Bar to BIr), which when actuated a control potential to a certain row wire or Lay the column wire. 14. Circuit arrangement according to claim 8 or claim 1 ?, characterized characterized in that an additional second decoder - 36 -009808/0750 - 36 ISE / Reg. 3810 dialing (DOB) with a number of inputs ^ and a number Outputs are provided that these inputs are connected to a further Oodespeicher (OSOB) and these outputs also control the row and column wires of the two-dimensional matrix and that a blocking circuit (Zr, Z'r) that simultaneous operation of the two second decoding circuits prevented. 15. Circuit arrangement according to claim 13, characterized in that that a) the relays in a group (Eir to EIr) assigned to rows (i1 to 11) and in one of the columns (al to h1) assigned group (Rar to Ehr) are broken down that b) each relay has a changeover contact (ri to rl ^ j ra to rh) has that o) the series-connected Euheseiten of the Umsehaltkontakte the first (second) relay group in series with a first resistor (R1, or R2) between the terminals a first (second) DC voltage source, the rest sides of the changeover contacts each by one second resistor (Ri to Rl; Ra to Rh) are bridged that d) the assigned row wires (i1 to 11) or column wires via the working sides of the changeover contacts (al to hl) of the matrix are excitable and that e) the connection point of the first resistor (R1, R2) with the neighboring resistor (Ri or Ra) is connected to a potential evaluator% ΈΊ) 2 or PD1), which responds when there is no resistance or more than one - 37 -009808/0750 - 37 - ISE / Reg. 3810 Resistance of the second resistors through, the rest side of the assigned changeover contact is not short-circuited. . \ 16. Circuit arrangement according to claim 15, characterized in that that an additional test circuit (COAB) of the following structure is provided: a) Each column wire is on an individual first Resistance (RVa to R'h) to one pole of the second DC voltage source connected, b) each row wire is connected via an individual second resistor (R ¹ i to R ¹ I) and a common resistor (R3) to the other pole of the second DC voltage source in such a way that the diodes (d1 to d32) are normally blocked, and c) the connection point of the individual second resistors with the common resistor is connected to a third potential evaluator (PD3), which detects an impermissible increase in the current through these resistors (R3, R ¹ a to R ¹ I, in particular due to the short circuit of a diode) ) responds.