DE1549746A1 - Device for recognizing patterns - Google Patents

Description

Applicant: Stuttgart » October 9, 1967

Hughea Aircraft Company P 1672 S / kg

Genttnela and Teale Street

Culver City, Calif, "V ₀ St = Aa. -

Device for recognizing patterns

The invention "relates to devices for recognizing patterns, and more particularly relates to a self-organizing system capable of" learning to recognize patterns "

In the new field of learning machines,

In recent years various systems have been developed that are able to »recognize or classify

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Learning to cough on the basis of previous experience _a Each of these self-learning systems essentially consists of three clearly distinguishable sub-systems or fields ο These are the input or scanning field, the association field and the output or response field o

The input field generally consists of a relatively large number of τοη load or read elements, such as photosall, which, depending on the sampled signal, provide output signal 9. The association field consists of many interlinked, adaptable logic elements that function as a function supply of them supplied by the photocells of the reading field signals Ausgangseignale "in typical Ausführungeformen the logic elements are Sohwellenwert-Sohaltungen where the Sohwellenwert, above which produces a Ausgangseignal is an" adjustable · is why these elements who called adaptable »The machine's output or response field, like the association field, consists of adaptable logic elements ₀

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They dee adaptability or the learning behavior system derives from the total change of the reactions of the individual logic elements abc These reactions during the training period of the system modified _E to detect known pattern ^ so that each known pattern liefertj an output signal that is unique to the pattern “The practiced system recognizes an unknown pattern when the unknown pattern generates an output signal; related to one of the unique signals associated with known patterns *

It will be apparent to those skilled in the art that it depends directly on whether it is easy or difficult to teach the system to recognize clear patterns, how easy or how difficult it is to modify the reactions of the various logical elements, so that different patterns, Although they are very similar, they produce different distinguishable output signals. It is therefore to be understood that a major task in the design of such systems is ₍ to increase the number of recognizable patterns without significantly increasing the number of logic elements and connections, because of such systems Increase the effort, the costs and the difficulties of maintaining the Syotem in operating condition would significantly increase ο

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The invention is accordingly based on the object to provide a novel adaptive and sißh self-organizing system for pattern recognition ,, which is characterized by a relatively © infachen construction and einweiobar easily White istο These objects are achieved by a system _t in the Leee ^ Elementej for example photocells which on a © position encoder «ι? Address patterns, linked in any way and scanned by a pseudorandaia pattern generator «. The output signals of the reading elements are combined in at least one equal value logic detector in order to generate a series or sequence of output signals. The output signals of the reading elements _P which are fed to the detector can be ordered in such a way that W all are added output signals of the elements and ^ when tibet an adjustable threshold value _f βla Ausgangesignal dee detector habenο result signals This output of l43se ~ Eiemente to old? stimulating signals are designated »

Furthermore, the detector may be operated so ,, that it responds to output signals of the reading elements, the barrier _t-Signaie bildon _s the reaction of the threshold

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Logic detector to prevent the stimulating signals »At In such an arrangement, the detector only supplies an output signal that forms a rope of the output signal sequence then ^ when the added stimulating signals exceed the thresholds » value plus the added blocking signals exceeded < > Further links between the threshold value detector « QG posture and the stimulating and blocking signals to be described in more detail in accordance with the teachings of the invention in = the way to be realized < >

As a result of the scanning of any connected reading elements with the help of the Pseudorandora-Mustergöneratore a sequence of output signals is provided by the detector circuit for each of the Leθθ elements scanned pattern is unambiguous o By recording or Save each sequence of output signals and later The unknown can compare with a sequence of output signals provided by an unknown pattern Patterns are recognized «if the result generated by it corresponds to a sequence that represented a known pattern

In this way, a system is provided which iat in lying, "with a relatively modest number of dependent

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to recognize patterns from their response to adjustable logic elements that have been shown to him beforehand «, a be» The special advantage of the new self-learning system is that it can be easily controlled in such a way that it clicks on a = clear, if very similar coughs, clear signals for identifying each one of a large number

of inputted patterns delivered where each cough characterized by a clear sequence of signals

In one embodiment of the invention, the system has an arrangement by which the Sequences of output signals, which represent known patterns, are modified, which is hereinafter referred to as reward or Punishing is referred to as the possibility of incorrect identification of an unknown pattern on one Reduce minimum »To be expressed differently during During the teaching period, the sequences of Auegange signals that represent known patterns are subjected to modifications in order to su ensure that every sequence is unique for a given pattern * Therefore, if an unknown pattern creates a such a sequence or a very similar one produces that unknown mother can be identified with a higher degree of accuracy

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The invention used wage and penal technology during the apprenticeship period to allow the machine to generate a clear sequence of patterns which the machine has learned to recognize. Each Ausgangesignal the sequence can also be considered so that the next pattern of Folge.anzeigte By this embodiment, the OF INVENTION ~ d \ mg accordingly provides a device which is as _"P teuerbar that it comprises a unique sequence of signals in response to a A clear sequence of patterns shows where each signal or all signals in the sequence are related to a following pattern in the pattern sequence. This embodiment of the invention enables, for example, the system to wander through a maze

Further details and embodiments of the invention are given in the following description, _s in which the invention with reference to the initial "shown in the drawing führungabeispiele further described and explained in", the description and the drawing to be extracted features may be used individually in embodiments of the invention for can be used individually or in any combination.

O/.

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Show it:

1 shows a general block diagram of a device according to the invention,

2 and 3 are block diagrams of the input field of the device according to FIG

4 and 5 are block diagrams of two different embodiments of the association field;

6 shows a function table to explain the arrangement according to FIG. 5 _f

7 and 7a are block diagrams of further embodiments of the association field Sf

Figo 8 is a schematic diagram of a threshold Logi.kdetektors _s

9 shows the block diagram of an embodiment of the output field

Figo 10 is a block diagram of a *? jhm management form of a follow-up code j ^% 6ra _{t /}

-5 _{; 1} 5 _{Q 8}

BAD ORIQfNAU

11 and 12 are diagrams to explain the mode of operation

the present invention in detecting cough success and

Fig. 13 is a block diagram of part of another Embodiment of the invention ".

In the simplified overall block diagram of an embodiment of the novel, adaptable, learning systems According to the invention, the above-mentioned input, Asso = * As can be seen, the input field comprises reading units 18 which can consist of a multiplicity of photocells which can be arranged in a specific matrix depending on the coughs that occur from the reading units have been scanned, output signals to be supplied to a suitable Handom switchgear 20. Inner » half of the switching mechanism 20, the output signals are the linked to different reading units and statistically sampled at a rate that is determined by pulses ο, from a clock pulse source or clock 22 to be delivered. During each pulse time interval that by the time between two successive pulses β

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is defined, the association field 14 is provided by the switching mechanism 20 with a set of signals »which the» the reading unit 18 speaks to the pattern scanned by it as a function of the special switching or scanning indicates the state of the switching mechanism 20 during the certain pulse intervals. -

The set of signals provided by the input field 12 is supplied to the Aeaoziationsfeld 14 at different training "of the present invention implementing form a different number of differently linked logical threshold" detectors comprises _o Be that illustrated in Fig. 1 embodiment, the associative field 14 has two threshold IiOgik = detectors 24 and 26, each of which receives a ψ different part of the signal set supplied by the input field 12 in a manner that will be described in detail later the cables led him input signals exceed the set threshold value, the Detekter provides an output signal, In the embodiment of Figure 1 dl ₀ · Ausgangseignale of the detectors 24 and 26, the old and _θ β O ^ beeeiohnet

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are fed to a logic unit 28, the function of which is to provide an output signal only when the signal θ _{θ is} greater than Q ^, ie greater than the output a signal of the detector 26 »The output signal of the unit 28 forms the output signal of the association field H, which is fed to the output field 16

The number of logical threshold value detectors depends on the special combination used, as will be explained in detail later, as well as on the special technique of scanning the input field 12 “If the scanning takes place one after the other in one scanning cycle? which comprises a selected number of pulse time intervals _f, such as N intervals, the output signal of the input field comprises 12 K sets of output _{signals P,} each set of which is fed to the aseociatory field during a different one of the H pulse time intervals Association field in turn consists of N output β signals which, according to the teachings of the present invention, are _f binary signals. That is, each of the N output signals of the ABB association field is either a binary ONE or a binary HULL depending on the binary output signal

109816/1506

the logic unit 28 "Consequently werdem has the complete scanning of the reading unit in response to a pattern of a series or sequence of N binary outputs of the Asaoziationsfeldes 14 to W sequence supplied to the output section 16 in such a device

As drsichtlieh _f contains the output section 16, a memory 3O ₈ which is controlled by a memory controller 32 from Figo 1 and "represents the output dee Assoaiationsfeldes 14 with the output of the logic unit 28; is connected by a gate 34 ο The outputs of the memory and the AesosiationsfQld.es 14 are connected to the two inputs of an AND gate 36. The output of the gate t can be connected to one or more output units 40 either directly or via a sequence encoder 38.

In short, is the function of memory? any sequence of output signals from the association field 14 which represents a different pattern that the machine has been taught to recognize? save "Then during a subsequent scan of the same Number the Ausgangesignale the Association field and the Save the AND gate were supplied to a" series of binary EIIJBon and NUILen »u create · This series ki>, rm a AuBgii'bouerk 40 supplied

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_s are counted by either the ONE's or the NULL's, so that the numerical value or the determined number is indicative of the special pattern * that the machine or system has learned to recognize. When encoder 38 is used, different portions of the sequence of ONE's and NUIL's are fed from gate 36 to different output units, each of which counts the ONE's or ZERO's that are fed to them.

The memory 30 can be envisioned as having a plurality of multi-bit fields or keepers, each of which can store a sequence of output signals from the association field 14 in dependence on a different one of the coughs that the system has been taught to recognize. It is assumed, for example, that in response to the cough of the letter ¹¹ E "which the system is to recognize, the input field 12 is scanned successively during a cycle of N pulse intervals, so that an output signal of the association field 14 results which consists of N binary signals, among which, for the purpose of explanation, for example, there are 180 ONE's, which are in a certain "for the pattern" E "characteristic sequence among N-180 ZERO's

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are distributed. In accordance with the principles of the invention, the result will be of output signals representing the pattern "E" and from now on referred to as E-FοIge, in one word of the Memory 30 is stored, which is used to store the S-sequence is determined. It is understandable that during a fol- ^ the scanning cycle of pattern "B" during 180 pulses » at intervals the inputs to AND gate 36 are binary ONE's, resulting in binary ONE's as the gate's output. These binary ONES are then fed to an output unit 40 which is assigned to the special pattern "E" to be recognized and in which the count results in the value 180 o Xn the same way, the system can be operated to assign other patterns such as the letter "P" recognize to store an F-sequence in another word of the memory 30 which, when it is read out during a subsequent scanning cycle of the F-pattern, results in a different numerical reading to which the F-sequence is fed o the output signal of the work or the works 40 is characteristic of the output signal of the output field 16 _O

The preparation or practice of the system takes place in the . Welse that the threshold values of the detectors in the association - Field 14 can be set so that depending on the tone jtdea

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the output field 16 supplies a unique numerical value for individual known patterns; which "if it is generated by an unknown pattern, is used to assign the unknown cough to the special pattern that supplies this special numerical value." . Accordingly, it can be assumed that an unknown pattern _s which, when scanned by the reading unit 18, supplies the output signal 180 _{s represents} the letter £ _s

In a realized embodiment of the invention has it turned out; that by setting the threshold values in association field 14, the system can be made to do so can ,, a variety of input patterns based on recognize numerical values; from the output field in Depending on each and every one of these patterns can be generated » Before the patterns were identified, each of them was scanned by the reading unit 18 during the training period and one The sequence associated with the pattern is stored in a memory 30. The stored poles were then associated with the sequence of output signals compared that of each of the unknown patterns

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were supplied., In this comparison, the numerical Output signal of the 'field 16 used for this purpose; the unknown To assign a cough to one of the known coughs ^ the same thing numerical output signal provided This technique was used to identify alphabetical symbols by adding the yon numerical output generated by an unknown symbol was compared with the known numerical output signals obtained from each of the known 26 alphabetical Symbols were generated »

Even though it turned out to be? that such a system works quite successfully ^ is understandable j that very similar though different sexton same numerical output can generate = signals and that consequently the distinction or secure identification dor pattern may be callous "occur, for example _$ Such difficulties when the Versuoh made is to statistically distinguish between two symbols such as "E" and "1" . To reduce the risk of incorrectly identifying patterns, a pay and penalty circuit 42 is used in accordance with the teachings of the present invention to control memory 32 to monitor, which in turn controlled the memory 30. The circuit 42 can contain a pay area and a penalty area. In short, the pay area is used

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154I74S

Number of EIHSs in the memory word that is known to one. .. To increase the pattern assigned i & t _v , while when the penalty circle is used, the number of ONE's in each storage word is reduced. To reduce the risk of incorrect identification of patterns, the penalty circle of the circuit 42 is used to Modify the contents of the memory words, each of which represents a sequence of output signals generated by a different known pattern, so that when each word is correlated or compared with the sequence of pulses generated by a sampled pattern that deviates from the pattern with which the word is associated, a minimum of the numerical output signal is generated ο

As described above, it is assumed that the memory word 180 assigned to the pattern "E" contains ONE's, so that the output signal of the plant 40 has the value 180 when the letter B is scanned . It is further assumed that when this Speioherwort is compared with a sequence of output signals of the association field 14, which are obtained when scanning the book table "F", the output signal of the work 40 has the value 25, which was due to the similarity between the letters E and F zuüokzu-

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1141741

lead is. Such a numerical output signal can be seen as analogous to a committee of 130 exports, which are supposed to recognize the letter B and of which 25 experts recognize the letter E and with the letter? To reduce the number of experts who mix up the two letters or coughs, according to the gates of the invention, the penalty circuit of circuit 42 is used during the training period of the system to change the memory word assigned to the letter E and the To reduce the number of EIHSs contained therein, so that then _; when the modified memory word E is used in conjunction with a scanned letter V , the output of the plant 40 is reduced to a minimum . This is analogous to the finding that the committee of 180 experts for recognizing the letter E is reduced in size by the, number of experts.

of the committee, which can confuse the letter S old with another letter, such as F. This technique has proven to be highly effective in reducing the risk of erroneous identification tob masters.

Ee is now directed DICR attention Figo 2 "in te verifiable uo a simplified diagram of Eingabefoldoe 12

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acts. As can be seen, the input field contains the empty units or elements, such as photo cells 18, which are arranged in a specific matrix to form a reading field 19 on which a pattern _s such as the letter E ₁ can be placed. Each of the elements produces an output signal as a function of the part of the pattern which it scans. In FIG. 2, the output signals of all the reading elements θ which form the reading field 19 are denoted by arrows 50a to 50n. It goes without saying that the number of output signals is equal to the number of reading elements 1 «which form the input or reading»! *. These output signals are fed to a logic and sampling circuit 55, the function of which is to combine the output signals of the reading elements into signal sets which are designated by arrows 57a to 571. Each signal set of the circuit 55 represents the output signal of a different combination of interlinked reading elements 18. The signal sets of the circuit 55 form the output signal of the reading field 12, which is fed to the association field 14.

The circuit diagram of one embodiment of the logic and sampling circuit 55 which has been practiced is shown in Figure ₀ to which reference is now made

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Embodiment of the invention consisted of 100 reading elements 18, the output signals of which were fed to 20 OR gates, of which the four gates 01, 02, 019 and 020 are illustrated in FIG. 3 o Each of the OR gates has five inputs and a single output to ₀ The outputs of the various reading elements can be connected to the ODEfi gates directly or with the help of statistical switches 3, four of such aND gate A1 _s A2, A19 and A20 shown the outputs of the aND gates 20 provide a set of signals represents the wirdο * supplied to the Assoziationefeld 14

The other inputs of the AND gates are each connected to a different bit of a multi-bit shift register 61 which, together with a modulo-2 adder 62, forms a digital pseudorandom pattern generator 63. As can be seen by a person skilled in the art, the generator 63, the may have more than one modulo-2 adder, a pseudorandom sequence of ZEROS and ONE's. The shift register 61 is advanced by the clock pulses ο that from the clock pulse source

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(Figo 1), so that during each clock pulse = * Xntervalles a different sequence or a different pattern of NUlLs and EXNSs is preprogrammed in the shift register. The patterns generated in this way are all different and do not repeat themselves until the main cycle is completed was when the register 61 of N bits containing the main cycle © ine period of 2 ^N -1 iüaktimpuls © »Bai has the Ausführungabeispiel described are the 20 AND gates A1 through A20 with the bits of a twelve <= bit Rögisters t. @ tied ₉ so that the pattern

i?
Cycle has the duration of 2-1 or 4095 clock pulses «, In the following the main cycle is also referred to as the sampling cycle ο.

From the foregoing description it will be apparent to those skilled in the art that during each clock pulse interval from the binary state of the bottom register bit to which the AND gate is connected and from the output of the OR gate associated with the other input of the aND gate is connected, on whether a given aND gate provides an output ", the aND gate A2 in the example illustrated in Figo 3 Taktimpule ~ interval and A19 independently of the signals to them by the qThe gates 02 and 019 are supplied, an output signal in Ferm a

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binary NUIL, Heil them with bits of the shift register which are in the binary NULL state. On the other hand, the AND gates A1 and A20, which are connected to bits of the shift register, can change the .la state a binary ONE, depending on the binary signals, which are fed to them by the OR gates 01 and 020, also provide a binary EIIiS as an output signal ο The off » output signals of the OR gates depend on the Signals that are fed to them by the reading elements 18 o As a result, during each clock pulse interval it supplied a unique set of 20 signals from the outputs of AND gates A1 to A20, which is a function of the special digital Mustοrs in the scanning cycle as well as the special combination of reading elements is that with the multitude the OR gates are connected «.

It should also be noted that when the digital pseudorandora pattern generator 63 is used, the AND gates A1 to A20 supply a different set of signals during each clock pulse - = - interval and therefore provide 4095 signal- to the association field 14 during a complete sampling cycle. feed sets. However, it should be pointed out that by a large increase in the number of logical bleaents in the holding 50, all signal sets are one at the same time

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Association field 14 can be supplied, which is sufficient is great to get all temporally coincident signal sets in To set relationship »In the following, however, for the purpose of simplicity of explanation, the new teaching of the invention described with reference to the series operation, in which the signal sets of the input field 12 to the association field 14 one after the other during a series of 4095 clock pulse intervals be supplied o

The association field 14 can be written in short as a circuit be "which provided in binary output signal as a function of applied thereto sets of signals and an adjustable threshold value Bas association box 14 may include one or more Sohwellenwert-rLogikdet"kt0ren> enthÄlJfcenL :, _f each of which an adjustable threshold value has ₉ each I'etektor can respond to all or a portion of the signals ^(of each. set of signals as may be supplied from the input field "each detector produces a binary output signal as a binary oNE only _t when the zugeiUhrten it signals the the selected threshold value: If the association field 14 contains more than one detector, the binary output signals of the various detectors are combined to form a single binary output signal as a function of the signal relationship between them eu,

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Figo 4 shows the block diagram of a realized Ausführungaform the Association field "two threshold logic detectors are In this embodiment, as shown in FIG _o ί shown, 24 and 26 are provided whose threshold values a threshold adjuster 24U bzwo 26ü is adjustable by means. As shown, the detector 24 receives half of the output signals of the input field ₉ namely the output signals of the AND gates A1 to A10 and the detector 26 receives the other half of the output signals? namely fed from the AND gates A1 to A20p ο Each detector generates a binary output signal _f which represents a binary ONE _t only if the ten signals “which are fed to it? exceed the threshold value imposed on it by its threshold value adjuster o It is assumed arbitrarily? that the output signal of the Sehwellenwert-Logikdetektcire 24 an excitation signal Q represents _f while the output signal of the detector 26 is a Spori'öignal O ^ represented In the particular Ausführungsboispie! the binary output signal G ^ of the detector 26 is fed to an inverter 65 _p the output of which is gold-plated with one input of an AND gate 67 o The other input of the UiiD gate 67 is connected to the output of the detector 24 o The Nagator 65 and the AND- Gates 67 form susamaieu the logic 28ο shown in Pig, 1

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As indicated by the special logic operations, the binary output signal of the AND gate 67 is a ZERO if the threshold value of the detector 26 is exceeded in any combination of the ten input signals fed to it, then its output signal is a binary ONE and the output signal of the inverter 65 is a binary ZERO o Accordingly, the binary ZERO at the output of the AND gate 67 is independent of the value of the binary output signal © _{Ä of} the detector 24 o If, on the other hand, the output signal of the detector is a binary ZERO and consequently the output signal of the inverter 65 is a binary ONE is, the output of the AND gate depends on the binary output of the detector 24 and is a binary ONE when Q _{Q is} a binary ONE and a binary ZERO ₉ when 9 _{A is} a binary ZERO »From the above it can therefore be seen ; that it depends on the binary characteristics of the set of signals supplied by the input field and on the threshold values which are generated in detectors 24 and 26 by the low-value bin dividers 24U and 26U assigned to them "whether the output signal of the AND gate 27" is the output signal of the association field forms a binary ONE or a binary ZERO let »PUr any given setting of the threshold values that the two

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Detectors are supplied »supplies the Aaaoaiationsfeld 14 an output signal that depends on the special Signaleatis either a binary NUXL or a binary ONE isto So if the association field has a sequence τοη 4095 Different sets of signals are supplied, forms dad Output s signal of AND gate 67 a sequence iron 4095 binary » Signals that represent either binary ones or binary IULLs and generated during the complete defrost cycle will", '

In the ^{arrangement shown in I 1} Ig ₀ 4, the output signal of the AND gate 6? a puncture of the signals in a single set of signals which is supplied to the asaoaiation field 14 during a single clock pulse interval. The signals which are fed to the detector 26 from the AND gates A11 to A20 are only used to prevent the generation of a binary SINS as the output signal of the AND gate 67, because they are processed by the detector 26, which, if it a binary EJMS al output signal supplies, the supply of a binary HUIL to a of entrances

of the AND gate 67 causes, again «* the

Generation of a binary ZERO as output signal de «flattere. lur follows. Egg wuyde found! dafl di · Äp | indliohktit

109815/1901

the association field 14 can be increased by the different signals of each signal set for both Excitation and blocking functions are used * without da 13 the size and complexity of the field of association is increased significantly. This can be done in such a way that an output signal of the association field is generated, ™ which is a puncture of the signals in two sets of signals generated during a two discrete clock pulse intervals and whose signals are used for both excitation and blocking »

To explain such an arrangement, reference is made to FIG. 5; in which the inverter 65 and the AND gate as well as shown in Fig. 4; The output signals (© _e and G _{1 of} the detectors 24 and 26 are also connected to a delay unit 71 and 72 respectively) Inverter 65d is supplied, while the output signal of the generator unit 72 is supplied directly to the other input of AND gate 67d. The output signals of AND gates 67 and 67d

1 η 9 Ö1 B / 1 B 0 β

- 23 -

two inputs of an OR gate 67x are supplied, whose output signal represents the output signal of the association field 14.

The delay units 71 and 72 are identical and cause a time delay, the length of which is equal to a whole number of clock pulse intervals. the signals applied to AND gate 67d represent the output signals of the same detectors generated during an earlier clock pulse interval. For purposes of explanation, it is assumed that the time delay generated by the two units 71 and 72 is the same the duration of two clock pulse intervals is * Furthermore, it is assumed that the output signal of the detector 24 during the first clock _{pulse interval θ θ1} and during the next but one clock pulse intervals _{θ @ q2} . Correspondingly, the output signal of the detector 26 should then also be activated during the first clock pulse interval O ₁₁ and during the most extreme clock pulse interval O ₁₂ . From Fig. 5 it is then possible that

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During these successive clock pulse intervals, the AND gate 71 only supplies a binary ONE as an output signal if θ _{β2 is} a ONE and © _{i2 is} a ZERO, while the AND gate 67d only supplies a binary ONE as an output signal if during the earlier clock pulse interval Q ^ were a ZERO and O ^ a binary ONE o The output signal of the gate 67x, which represents the output signal of the Asaozlatlonfeldes 14, is a function of the signal sets that the threshold value detectors 24 and 26 during each of the two discrete Clock intervals were supplied in such a way that the signals which were used during a clock pulse interval for excitation purposes are later used for blocking purposes, while the signals ₉ which are used during the earlier clock pulse interval for blocking purposes ₉ during the following Clock pulse intervals are used for excitation purposes »

The operation of the logic shown in Fig. 5 can be summarized in the form of a function table, which is shown in FIG ₀ 6, Aue the table is ersiohtlioh that the output signal of the gate 67x which is shown in the reohten column always a binary ONE is if one of the two gates 67 or 67d has a binary ONE as the output signal af ^ fljtg / -jg Q 8

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In another embodiment of the association field 14 "the one in?} G. 7, the Assoslatlona field has a β-wave value logic detector 75 which only sends a binary output signal to the output field 16 if an input signal supplied to it by a subtractor 74 exceeds a threshold value set in the detector may be an analog signal representing the difference between the output signals from adders 76 and 78. The adder 76 forms the sum of the output signals of the AND gates A1 to A10, while the adder 78 forms the sum of the output signals of the AND gates All to A20 · If the signals added in the adder 76 with X. » The index e indicates that the signals have an excitation function, the signals added in the adder 78 with X ₁ , the index i indicating that the signals have a blocking function, and the adjustable threshold value in the detector 75 is rewarded with it θ _{the output signal of the detector 75 labeled X Q} can be reproduced by the following pre-calibration puncture:;

X ₀ «sign C; iW _e X _e - ^ W ₁ X ₁ - $

In this equation, W ₀ and W ₁ are weighting functions which do not assume negative values and which serve to determine the various signals that are sent to the two adders.

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assign different weights. The sign function takes either the value +1 or -1, whichever is closer The agreement made can be evaluated as either a binary ONE or a binary ZERO. So while in the previously described embodiment examples of the association field U of each detector such as those shown in FIG Detectors 24 and 26, is supplied with signals that exert either an excitation or blocking function, the Detector 75 of FIG. 7 is supplied with a signal from subtracter 74 which is an output signal, which represents the combined effect of signals that are also considered to have excitation and blocking functions can be.

In yet another exemplary embodiment of the invention shown in FIG. 7a, the signals supplied by the AND gates A1 to A10 are fed to two threshold value logic detectors 75a and 75b, which supply _{corresponding output signals © ea} and © _ia. In the same way, the output signals of the AND gates A11 to A20 are fed to two threshold value logic detectors 75c and 75d, the output signals of which are denoted by Q ^ and Q ^. The output signals of the detectors 75a and 75o are in a logic level · 79 »

109615/1506 · /.

combined, which contains eXnen negator and an AND gate and performs a puncture which is the same as the function performed by the inverter 65 and the AND gate 67 of FIG the output signal θ ^ a ZERO and the output signal © _, _ a binary ONE areo In such an arrangement, the output signals of gates A11 to A20 fulfill a blocking function, while the output signals of gates A1 to A10 have an excitation function. In the same way, the output signals of the detectors 75b and 75d are combined in a logic stage 79b, which is identical to the logic stage 79a o The output signal of the stage 79b is only a binary ONE if the output signal of the detector 75b is a binary ZERO and the output signal of the Detector 75d is a binary ONE o As a result, the signals of the gates A11 to A20 fulfill one with respect to the output signal of the control unit 79b. Anregungefunktion, while the signals of the gates A1 to A10 have a blocking function ₀ The outputs of the stages 79a and 79b to an OR gate 79x are supplied, whose outputs signal forms the output signal of the Assossiationsfeldes fourteenth

109815/1506

It will be understood that various circuits can be used to construct a threshold logic detector suitable for practicing the invention. " However, the circuit shown schematically in FIG. 8 has proven to be particularly versatile and expedient for the invention. This circuit is highly adaptable and enables the above-mentioned threshold values to be set easily. The detector circuit 80 according to FIG. 8 has ten inputs , which are designated with PI to P10 "and a single output 82" A variable resistor Ry supplies an adjustable analog threshold value in a manner to be described below is such that the input is connected to a first reference voltage, for example -6 V ₁ when the corresponding AND gate delivers a binary EIHS while epannung at another reference, for example, to Hasse, applied to the AND gates A1 connected to A10 , if the output signal of the relevant AND gate is a binary NUIiIi «.

DU Bingang © P1 Mq P1S are connected via Y / iderstandso R1 to R10 with a common anaohlußpunkt D1. The Span- mjr.ig BM Aneohlußpuakt D1 is a function öar digital signalö

1545746

at "the various inputs P1 to P10, the resistors RI to H10 can have different resistance values, so that they assign different weighting factors to the input signals. They form a passive resistance summing circuit, which is also known as a Khirkoff adder and a summation of the The detector circuit 80 also contains a tunnel diode T1, the anode of which is connected to the connection point D1 and the base of a transistor 83, the emitter of which, like the cathode of the tunnel diode T1, is connected to a reference voltage of -6 V, for example "The collector of transistor 83 is connected _{to another reference potential via a resistor R ß} - for example to OV or ground. This collector is also connected to the base of a transistor 84 via a parallel connection of capacitor C1 and resistor Rq." The emitter of this second transistor 84- is also connected to the first reference circuit angesohlossen retr, for example, -6 V, whereas the collector of this transistor to the output 82 of the circuit and via a further resistor R ₀ with the second reference voltage, for example OV connected istο The adjustable Sohwellenwert is of a resistor R _4. supplied, on the one hand with the Ansohlußpunkt D1 and

109815/1508 ./.

BAD ORiGiNAL

on the other hand is connected to a movable tap of the variable resistor Ry. She. Connections this variable resistance are on the one hand to ground and on the other hand to a further reference potential of, for example -18 V connected. The threshold value is changed by changing the position of the tap of the resistor Ry is set.

As is known, a tunnel diode forms a bistable element, which can be switched between two stable operating states, often as a tunnel area (low voltage and high current) and as a diode area (high voltage and low Electricity). When the tunnel diode T1 works in the tunnel area, the base of the transistor 83 is located only slightly above = 6 V, so that the transistor S3 is in the non-conductive state The collector of this transistor and the base of the Traneistort 84 are at ground potential in the conductive state, so that his collector and old him the associated output 82 will be close to -6 T, which represents a binary ONE · If, on the other hand, the tunnel diode T1 operates in the diode range, transistor 83 is conductive, while transistor 84 is non-conductive or blocked.

• A 1 01981 B / 1 50 6

As a result, you will find the collector of the transit gate 84- and output 82 essentially at ground potential, which corresponds to a binary IfUIiL «.

The threshold value at which the tunnel diode W T1 is switched from one state to the other is determined by the setting of the variable resistor Ry, while the switching itself is determined by the summation at the connection point D1 as a function of the digital signals at the inputs P1 until F10 is controlled _e The so-called holding has proven to be extremely advantageous, v / eil a tunnel diode can be switched at very high speed; switching only takes a few ficoseconds. Furthermore, the switching threshold value is very sharply defined and. the energy required for switching is much smaller than that required for other, more common circuits. In addition, the circuit using a tunnel diode has proven to be very stable.

The preceding description has shown that the new system according to the invention has a plurality of leeward elements which form a leeward area with which the au recognizing Pattern is brought to congruence. The reading elements deliver

109815/1606

output signals as a function of the sampled pattern. The output signals of arbitrarily selected reading elements are stored in a large number of logic elements, such as the O3XBH gates 01 to »020 according to Pig. 3, linked together. The output signals of the logic elements are sampled} to form sets of output signals, each of which Sata represents the reaction of another combination of the read elements to the sampled Huster "You signals of each Satzesι which the output signal form an input field, a field of association are fed by in a threshold value detector circuit linked together tder be analyzed. The signals of each set are divided in order to execute excitations and / or blocking functions, so that only when one or more adjustable threshold values are exceeded by different combinations of signals, a binary BINS is generated as an output signal by the alarm field. Another case is provided by de "Aseoziationsfeld" ine binary Luell al · training 'gang · signal. Des Ae * eeiationeftId * wm vt.it «rbin ■ © be operated, d * 3 te tin binary * Auegftngisign * i Utftit, since · a function of Signaita from mthr mis tint% itt, wit t · wordtn itt.

in Ttrbindun " with dtn f ^ * 5

■ iwi-i s / 1

BAD ORlQfNAL

Regardless of its mode of operation, however, let the Auegangesignal dee Aeeesiatlonsfeldee a group of binary signals, the τοη of a sequence τοη Elisen and MULLen is formed · Soloh a group is pharakterletisoh for a certain, τοη the reading eleaenten erfsfitee pattern and is used, mother to identify su or to recognize su that are an equal binary Bend group down. It should be noted that the group τοη, binary output signals of the AseoBlatlonsfeldee as a result appears when the signal seeds suggested to the aesosiation field are sucked up one after the other, beieplelewelee old help of the digital pseudorandoa switchgear 63 described with reference to fig a sufficiently large number of τοη logical cleavages all Signal devices that characterize a special pattern elnd, equal parts, so that the Assoslatlons-

that a sufficiently large number τοη

dft gets «! · Group το« binary XUUtn

AROUND*

becomes dl in 4 * Opel

109818/110

BATH ORIGINAL

, * »Fr

to provide an output indicating the type of pattern being scanned »The contents of the memory can be used for any known cough can be modified in order to bring the output signal of the output field 16 to a minimum, if the content of the known hustler is compared or correlated with a sequence that is determined by any, is generated with the well-known non-identical pattern « For example, as stated above, a word in the memory 30 which is assigned to the letter E can pass through Reducing the number of ONES contained therein can be modified in such a way that if the storage word E with a sequence of binary signals from the association field 14 compared or correlated as a result of sampling any pattern other than the letter E, the Output signal of the output field a 16 HULIi or a minimum is. As a result, an unknown pattern can be identified as the letter E with great certainty if a Sequence of binary signals from the association field 14 'which are known as Result of the scanning of an unknown mother delivered is compared with dea memory word E and here a Significant output signal is heard.

109815 / 1B0B

The number of ONE's in the memory word E is reduced with the aid of a reward and penalty circuit 42. As explained above, this circuit can be thought of as a wage circle and a penalty circle »Die The function of the wage groups is simply the number to increase the ONE's in each of the memory keepers in the memory 30, while the penalty circle has to reduce the number of ONE's contained therein ο There are currently many Methods are known for writing data into memory words, it goes without saying that those for modification The circuits required for the stored words can consist of various arrangements of logic circuits are adapted to the particular memory used = For example, the wage and penalty circuit 42 can be one by hand have actuatable switch which, when actuated, triggers a monoflop to a pulse of a certain duration during which either ones or zeros are stored in one of the memory words that is known in Way was transferred to a write register, not shown, so that the desired binary signals can be written therein during the specific time period.

109815/1506

The ability to modify the content of any memory word associated with a known pattern is of the utmost importance because it increases the ability of the system disclosed here to distinguish patterns which are not present on a particular part of the reading field 19 (Fig. 2) needs to be arranged, but rather can be arranged in any desired position on the field. For example, a memory word assigned to the letter X and hereinafter referred to as memory word X can be rewarded during the lorn period of the system to to provide a relatively large output signal when the letter X is arranged in any of many different positions on the memory field 19, while a penalty or reduction in the number of ONE's stored in the memory word X occurs when another letter, such as the letter L _{9 is brought} into different positions on the reading field 19 ο If necessary, k The threshold values in the association field 14 can be adjusted in order to ensure that the memory word X contains a sufficient number of ONE's that do not correlate with ellipses. to provide an Auaganga signal indicating the letter X.

109815/1506 ^{# /} *

BATH ORIGINAL

In another embodiment of the invention that can Output field 16 have a plurality of output channels, which represent numerical output signals, which in the following simply referred to as output signals. These output signals are used to display the content of the memory to be controlled so that in dependence on each pattern of a sequence of scanned coughs the output signals in the plurality of output channels for one of the successive ones The system according to the invention is therefore not limited to individual Recognize patterns and, depending on them, output signals but also able to display a variety of sequential read patterns.

To explain this variant of the present invention is on Flg. 9, which is a simplified blook diagram of another embodiment of the output field 16 represents. In the embodiment shown in FIG. 9, the Memory 30 from a large circular swipe register or a delay line whose delay is sufficient to store 4095 bits therein. Ee be auoh assumed that the sequence of binary signals sent by

Association field supplied as a result of reading a pattern comprises 4095 bits. The output signal of the memory 30 and the sequence supplied by the association field 14 are fed to an AND gate 36, which is connected via a sequence encoder 38 to a plurality of output channels Z1 to Z4. "The channels Z1 to Z4 correspond to the output unit 40 in FIG. 1" as described above is to provide ₅ during jjedes time intervals a Ausgangeslgnal that the two supplied thereto / iinär signals in relationship sets the puncture of gate 36 * the gate delivers a binary oNE in & er when the two supplied binary * signals binary him ONEs oind <the puncture of the Folgecodierers 38 _consists} the signären Auegangssignale of the gate 36 of the plurality of output channels successively supplying * Comparing or Ir.orreliert him trains led binary signal sequences bit by bit while the encoder 38 has the task of the two _f the output signal of Gate 36 to distribute the four output channels »The encoder 38 can be operated eo that it is the A output channel 21 feeds the result of the correlation of bits 1, 5 t 9 "... 4092 of the two binary signal sequences, whereas the results of the correlation of bits 2, 6, 10, ... 4093 are fed to output channel Z2" The Results of the correlation

109815/1506

the bit 3, 7, «« ο 4094 the output channel Z3 and the results of the correlation of the bits 4 ₉ 8,. · <> 4095 fed to the last output channel Z4 «

A possible embodiment of Folgeoodierers 38 is _t shown in Fig. 10 is made to the now made. The encoder includes a circular shift register 38s which comprises four bits labeled 38a through 38d. During each time interval a ONE is stored in one of the bits and a ZERO stored in the other three bits. As from Flg. 10 can be seen; the bits 38a to 38d are each connected to an input of one of the AND gates 101 to 104, while the other input of each of the gates is connected to the output of the AND gate 36. The outputs of the gates 101 to 104 are connected to the output channels Z1 to Z4. During each time interval only one bit of the shift register stores a binary ONE ₁ so that only one of the four AND gates 101-104 is supplied with a binary ONE by the register. As a result, only one of the output channels can be supplied with a binary ONE at a time, provided that the AND gate 36 supplies a binary ONE. In the embodiment shown in FIG. 10, when the signal supplied by gate 36 is a binary ONE, gate 101 is excited so that the

109815/1506 " ^{/ f}

BATH ORIGINAL

Output channel 21 a binary ONE is fed o During of the following clock interval, the gate 102 can as a function of the signal supplied by the gate 36 be stimulated *,

From the foregoing it can be seen that the use of an output field as shown in FIG is, a plurality of output signals can be supplied from a plurality of output channels, each of which the correlation between different parts of the two binary signal sequences, one of which is stored in memory 30 and the other is supplied in dependence on a read pattern from the association field, represents α the plurality the output signals can be used either manually or automatically to determine the content of the sequence in memory 30 reward and / or punish, so that for each pattern read the plurality of output signals an indication of • delivers in the following pattern, which is to be read in a sequence of external patterns «

For a better understanding of the last aspect described of the invention, reference is made to Fig. 11, which is about • acts in a simple diagram that shows a variety of

109815/1506 /

represents sections X1 to X10. Each pattern in the sequence is intended to represent an extension of the previous pattern. Accordingly, assume that the patterns from the Sections X1, X1 + X2, X1 + X2 + X3 etc. exist. When the output channels Z1 to Z4 are considered the north, south, east and West are defined to represent, the system according to the invention can be operated in such a way that when reading a Pattern, which is only represented by X1 and is assumed to be the first in the pattern sequence, the output signals of the four output channels can be controlled in such a way that the output » signal is greatest in channel Z1, which represents north, indicating that the following pattern is the The result is one that has a portion extending northward from the pattern X1 just read. That that is, the closest pattern consists of the sections X1 + X2.

The control that causes the output channel Z1, the largest Having an output signal is redeemed by rewarding the bits in the memory 30 assigned to the output channel 21 with the aid of the wage circuit of the wage and penalty management 42. Baa leaning is done by writing binary BIN8s in some the bits 1, 5 »9 to 4092 in such a way that the output signal dee Auigatmkanalee Z1 becomes the largest of the four Auegabekanals.

109815/1608 ' ^{/ #}

Thereafter, includes what is shown on the reading field 19 (FIG. 2) Pattern the swatches X1 + X2. The output signals of the four output channels are observed again and with the help the wage and penalty circuit 42 controlled in such a way that the Output signal of the output channel Z1 is again the largest and thereby indicating that the following cough is one which moves north across the pattern just scanned has also extending section, so a pattern with the sections XUX2 + X3.

The contents of the memory are modified as each successive pattern is scanned. From FIG. 11 it can be seen that after the representation of the patterns which comprise the sections XI to X4, the section of the following pattern, that is to say X5 _{f, is} located to the right or east of X4. Therefore, when displaying a pattern comprising the sections X1 to X4, the content of the memory 30 is adjusted by rewarding and punishing various of its parts so that the output of the channel Z3 "representing the east becomes a maximum. When the pattern comprising the sections X1 to X6 is displayed, it is again desirable that the output signal of the channel Zt be the largest because the subsequent pattern section X7 is located north of X6.

109815/1506 ^#A

The process of modifying the contents of memory 30 is continued for everyone following this; until the complete sequence of patterns has been read =, Danaeh can ee eri-ox'cier- · borrowed S9in> repeat this operation several times _P vreil successive modifications that can affect the capabilities of the "machine to display previous patterns =, s can Naüh multiple passage of the contents of the memory 50, however, so madifisiert ee, _LN? that the output of the ignale Vielsahl το.η output channels as a function of scanning GEDES each represents a display pattern for the subsequent Must it provides eggs = SERIO Accordingly, it can the system that can be brought to _? Each of the patterns a?. · Sequence to be recognized and signals jsu deliver _f the ftl ??: the next pattern "" characteristically indo .. f.- ■

When setting up the system for generating output signals which, depending on each pattern of a sequence, indicate the next pattern, a situation can arise in which the special sequences of the binary signals are rewarded or punished for the contents of the memory the association field of gate 36 .. after reading the "ar ■ _ echiedeaen pattern of the sequence supplies, is insufficient, \ m the wrong results su * ra; ie.l" n. In such a case

O / ·

109115/1501 BATHROOM OBlQiNAL

, 1548746

_'s change ollow up the signal flags * /' te & mi flrle setting Yeraehiedenen thresholds in Assossiationsfeld · dia depending vq-u ^ ereohieflentn sampled £ .1 reap ersetigt "-Will, öerart with the contents of the memory kox can be röliert? ₈ that the output signals QfiiiB generated as a _{function of the pattern read provide 0} for the closest pattern in the sequence

The operation in the adjustment-of the system _v ea to the correct response to the veranschauliohtön in Eig ₀ 11 pattern capable _f lab in'Tabellenform in Pig "12 summarized = The IAB & llft are jeweila the channel to _s in .Abhängigkeit of j-aöem must have patterns of sequence a maximum · Aiisgangaaignal "Ea understands 8iöh _s that al-äae'Ausganges ign-one? Β channels by rewarding d _o h _o assigned by Erhö'hen the number of EXliÖen Add to that channel bits 9 and / or "punishing durßh ₅ d οhY reducing the number of EXNSen be placed in the bits of the other channels _P to a maximum can be ₀ Consequently, rewarding and Beatrafan commonly referred to as modifying the memory contents · what the reward and / or punishment Each part shall mean the memory contents.

109115/160

From the foregoing it can be seen that the system according to the invention is not only. Output signals, each of which represents a display for a "different Musfesr" and output signals that represent special Mustex * in the reading field? lieferts but darübsrhinaus 1st able to Setsen patterns in order that parts of a pattern sequence are * as shown in FIG, 11 Teransehaulicht L3t ₀ If the pattern according to E ¹ Ig are ₀ 11 considered maze - can the new "just described “System can be made or learn to supply output signals in dependence on each position or each section of the maze, which are characteristic of the next section of the maze. Therefore, this Systeja _s can be considered as a system that is able to automatically go through a _maze-f *

So far it has not been assumed that rewarding or punishing takes place in a memory word that is derived from the output signal the association field 14- is formed "," Such an arrangement is shown in Figures "■ Γ and 9 o The invention

± st - ^ e ^ ocTj ** ltöineswegö limited to this ο Rather, wage and penal techniques within the Aeeöziations- ' ftldee 14 on the separate Auagang suitable · the threshold

BATH

f- which deliver the stimulating or sperreride'η Aufgangsβigna-Ler = So example syr0iseöle output saignale of the Söhwellenvrert logic = · ciutalctören 24 'and 26 (FXg =' 4T ₃ die, designated with θ and O ₄ aiad _r separately rewarded or "punished v; erden / üia two m & difl · · , Yxer ta binary sequences' z \\ -eraeugen ·, - one of which goes to the anregaiiead. \ U8gangssisnaXeh öea detector 24 and the other zn den.-aper ^ end- often "iAusgangssighia-icn ύο & Detektors 26 in Be-Ef.elmng Pte}: ric These-moä if! ziert binary sequences can then in zvfef .. separate memory details and combined with Srsoiigimg a single binary sequence ; signal dee association field 14

-.Zorn beKeeren Veratändnis such an arrangement is based on 'l ^ igc * 5 Ba sug geno.miaen _t which shows how the output signal dee 5,.' I | iw ^ llenwert «'IjOgikdetektoi' 24 (Pigs 1) a memory 30 · tlbex iln gate. 34a and an "input" is routed to TJKD-ßatterg 36a *, the other input of the gate 36 is connected to the memory 30a, which together with the "amtn" it de "gate 34a is controlled by an input 32, di · their · · it * y of the wage and penalty circuit 42 in the same • expensive i * t ₉ , as e · was described above with reference to FIG

Similarly, the Ausgangsßignale Q ^ of the threshold logic detector 26 $ the blocking signals represent _s through a gate 54b to a memory 30b and an input of an AND ~ gate 36b fed ■> The other input of the gate is connected to the output of the memory 30b connected

The memories 30a and 30b can be controlled independently of one another by the circuit 32 in order to store modified binary sequences which represent the output signals of the detectors 24 and 26. The modified poles in the gates 36a and 36b can then be correlated with the output signals of the two detectors and are then fed to the logic 28, the output signal of which represents the output signal of the assembly field 14. As described above, the logic 28 can consist of an inverter and a UIiD gate such as the inverter 65 shown in Pigs 4 and the AND gate 67. As shown, the output of the logic 26 is supplied to the Polgecodierer 38 which, as described above be "registered, different parts of the binary _{sequence, etc.} which the output signal of the Association field 14 forms, different output channels as the channels 21 to Z4 which supplies _f ao that the combined output signals of the output channels

9015/1506 BATH ORIGINAL

1649746

kösnöis are used; each of a variety of tint patterns Must order wi

It was üeianaöh a new * adaptable system he to · recognition of patterns written and illustrated kannj learn BeInBt anäuapreohen a pattern and eih daaii related ateliendas Auogangssignal deliver aov / ie ant iodine pattern to address viiwt pattern sequence and Off = · su gangaslgnale deliver _f the on a different pattern of ikilga X) BgQgQn ßiziäc It · is for the skilled person TerBtänäliohi. that the arrangements shown can abgewandeltwerden ₉ Ohii-Ώ the scope of the invention to ^T Terlaaseno The invention is therefore not limited up the Ausführungsbeiapiele shown o- ■ ■. .

109815/1 5Qi6

BATH ORIGINAL

Claims (1)

~ 54 ■. Claims Caow i ii iwi i ι ι μι im ■ - Adaptable and self-learning device for the detection of patterns with a multitude of laser elements emitting laser field; an association field containing at least one Sohwellenv / e.-ct detector and an output field evaluating the output suitability of the association field j characterized by? that the Lesefuld,. _f (12) has means {2.0}; to scan the signals delivered by the learners (18) when reading a pattern: l & ginar bea'Simmton statiatisohen sequence and to generate a sequence of signal sets _? γόη which each sentence the signals of a different combination of LeaeeXemente. C18) represents that the threshold value detector .., (24 ₁ 26) in the association field (H) mindostena. on, a part of each signaleatea of the sequence responds and delivers an eratee binary = signal? if the signals of the sentence a exceed the threshold value, ao that the association field (14) supplies a sequence of binary signals in which the distribution of the ZEROs and ONE's is a function of the pattern scanned by the Leaeelementen "and that the output field (16 ) a memory (30) for the sequence of 1098 15/150 6
BATH ORIGINAL Binary signals and a correlator (36) coupled to the Asaozlationafeld (14) and the memory (30) on ». veiist to compare the sequence of binary signals contained in the memory (30) with a signal series supplied by the association field (H) as a result of the scanning of a pattern and to leave an output signal dependent on the result of the comparison ern _$ that is a statement about the scanned pattern or? in the case of a pattern sequence via which the scanned pattern represents the following pattern ο 2c device according to claim 1, characterized in ₃ that the serving for statistical sampling of the read elements means -umfaßt (20) of the reading field (12) a plurality of öattern (01 to 020), each of which has a plurality of inputs and an output, to provide a function of signals of a certain amplitude at each of its inputs an output signal of selected amplitude that the Ieseelemente (18) of the gate are each provided with at least one input connected in an arbitrary manner, and in that means are provided (61 _S 62 and A1 to A2Ö) are to the outputs of the ο / ο 109815/1506 BAD ORiQINAt To scan gates statistically and to generate the sequence of Signalaätzign to be fed to the Asöoslationa field ο 3-. Device according to claims 1 and 2 _r dadurol in that the reading elements (18) provide a binary ONE at its output respectively, when they detect a portion of the iäu read pattern _s and a binary _UITLL: if no part of the Mustere present _t that the Do gates (01 bid 020) only deliver a binary ONE at their output? if there is a & its input oina certain number of ONE's; and "that the binary output signals of the gates are sampled in a statistical manner, - so that the signal sets of the poles fed to the association field (H) are formed by binary signal sets, 4c The device according to claims 1 to 3 _f can- «eichneti that the gates (01 to 020) are formed by OR gates and the means for statistical scanning of the gate outputs i AND gates (A1 to A20), of which Each has two inputs and one output, and comprise a Randora switchgear (20)? dae has a shift register (6t) with a large number of bits, which generates a unique sequence of χ bits, that the outputs 109 8 15 / ItQ6 BATH ORIGINAL 154974S represents OR ßatter (01 to 020) jQvreilq with an input of a represent ÜHP ~ gate (Al to A2Q) and the S of the Ssliieberegietsrs (61} to the other input minde least 3inss exerts USKKGatter (Al are to A20) Yerbuntfen so that the binary output signals of the i ÜHD gates form a set of i binary signals during 3-edea bit of the χ-bit sequence of the StsMeberegister and 'uemnaoh χ sets of tone i binary signals are generated ₉ ölo "which form the output signal of the Lssefeldee (t2)» · rriohtOiig after eiiiam aex · previous daclucali gekennaslalirvet ₅ that the association field (14). ■ ßiria Helirsahl ^; / ßii Sohv.'ellenwert - I) etektpren (24 and 26)., iti each points to an adjustable Söliwellanwrt and IiQgife (28) Torgösehen 1st,., which points to the initial. Ölgnala (O _Ä and O ^} responds to the threshold detectors and only then draws a binary ONE as the output signal of the , Aaao ^ iationafeldeo (H), if the outputs are signals ^ dar! Joiivreillanviert- ^ etektoron .in a certain binary BAD ORJQfNAL 6, _"f device according Anspruch.5 characterized; äQß provided two arrays you threshold detectors 24 {UNAE 26) SiUa ₅ of which the one on © inen part, preferably half, and the other on the other part inen © _f preferably the other half of the signals of each Signalsat supplied by the reading field (12) is responsive, and in that the logic (28) Auggangssignal in the form of a binary bINS, _f generated when the first detector array (24) an output _signal? particular one binary ONE ₉ and the wide detector arrangement (26) deliver no output signal j, in particular its binary HULL; 7ο device according to claims 5 and 6 _; characterized by the fact that each. Detector arrangement has two threshold value detectors (75a and 75b hm> 75o and 75d) .; of which one (75a bswc 75d) delivers a binary EIHS and the other (75b or 75o) a binary NUIiL as an output signal when the signals sent to it exceed a threshold value _? that a first logic = stuf3 (79a) to the output signal of one detector (7 & a) of the first arrangement and of the other .Detector (75c) of the other arrangement and a second logic stage (79b) 109815/1506 BAD ORiGJNAL ~ 59 - to the Auagangaeignal of the other detector (75t)} of the first arrangement and the one detector (75d) of the second arrangement respond and in each case an output signal, in which the signals of one detector a binary EIHS and the signals of the other detector a " binary iTTJI »L represent" and that © ine further arrangement (79x) available iet _like the oils of Ausgangsaignale bgiden = logic levels (79a and 79b) is supplied v / ground and which provides a binary oNE al βi.Auagangssignal when at least one of both. Logic levels have a binary ONE as output signal * Device according to one of the preceding; Claims. · That u L-oh characterized aaJ3 the output signal of the! Correlator (36} a "?" Numerical indication of the coincidence between selected signals of the signal sequence supplied by the association field (14) and corresponding signals of the stored signal rim, '· 9c device according to one of the previous ÄTJspreh.e ₅ ■ '. Characterized ₅ öaü the memory (30) of the output .feldeo (16) vcn a Umlauf-SchieberegiB-töi 'or a 109815/1506 BAD ORIOtNAL Delay line wirö.- formed _t the bsswo AEIE a number of Bite au save T & rmagj oil © the ansa & lder bits of Signalfolgß supplied from the Aßsosiationaf8,1 (1 (14) equal, and in that means "uia continuous reading of the. Signals stored lind ssum Write one signal for each read signal verge "sohan sindo 10. Device according to a dor Yorfcer claim « _f characterized _? that the output field (16) contains a wage and / or "penalty circuit {42} linked to the memory (30) on the modification of the gfrspfiioheiFtflK ... sequence of binary concepts:, ·,. ') / *> a ^ ^; ' - ■ 11c Varriohtung ηεοίι claims 10 and 11 _f thereby -marked; that cUIg in the circulating shift register (30) stored signal sequence by varying the number of the binary signals present in certain places in the memory raodlfizable i 12o Apparatus according to claim 10 or 11 _t characterized in that üie labor and / or penalty circuit (42) functioning during selected Seitintervalle the BATH When comparing the signal sequences supplied by the association (14) with the stored signal sequences, the number of coincident elites should be reduced ₉ if it exceeds a ventilated number, and increased if it is smaller than a torbeatimifted number. 13 »Device according to one of claims 1 to 4, characterized in that the asaoäiation field {14) has a two threshold value detectors (24 and 26)» which deliver a first and a second sequence τώη binary = signals (Θ _Λ or Θ /), that a first memory (30a) for the first signal sequences (ö_) and a second memory (30b) for the second signal sequence (Q ^) are provided, that means (42) are provided,. To store the stored sequences of the binary signal Q to modify independently of one another that means ('36a, 36b and 28) are provided to correlate the two modified sequences with sequences supplied later by the threshold value detectors (24 and 26) and to form a third sequence of binary signals » which is fed to the output field (16). - • * λ ΒιΛ ^; ' BADpBJQiNAi. 10981571506 St., Blank page