DE1537853C - Circuit arrangement for a cyclically operating electronic receiving, evaluating and recording device for measuring traffic in a telephone exchange - Google Patents

Description

ι 2

The invention relates to a circuit arrangement for electronic devices with their own code. The known solutions for electronic reception, which work cyclically, are not very reliable and the evaluation and registration device for traffic can only be used to a very limited extent.
measurement for several trunk lines in a remote A circuit arrangement according to the invention speech exchange. In such a device 5 contains a. Time-division switch (time-space are criteria that come from the various remote multiple switches), which the exchange lines to be tested, speech lines come and - z. B. on dialing alternately with the reception, evaluation and digits, the call status, the duration of the call and the registration facility in connection. These data relating to the recording of charges and the establishment consists of a logical control switch invoicing, alternately by an IO device, to which a binary phase counter for addition, time division multiplexing device receives, evaluates, and subtracts, the four delay lines stored in a flow memory and on a ( Circulating memory) and a - logical counting circuit output device, e.g. a hole punch, a tape and is described elsewhere (German recording device, a register or an over- patent application S103905 Villa / 21a ¹ ). On the transmission channel, transmitted so as to enable a documentation counter, there is an output register which stores the result and a telephone traffic measurement relating to the operations each time this allows the various trunk lines to be borrowed. Result to an output device, ζ. Β. a hole punch,

It is therefore the object of the invention, which is passed on in a.

Telephone switching system existing equipment The aforementioned control logic circuit receives

not only for establishing the connection between not only those of the checked trunk lines

See the participants to use, but they are incoming signals, but also the signals from

also for the recording of the charges of the individual output of the phase counter, order the case by case

Participants (to be taken into account by counting calls and tariff off status at the meter output

Wahl) and can also be used for traffic measurements. .

use which devices data for examinations 95 The invention is explained in more detail below with reference to def £ to improve the utilization of the telephone drawing! it shows
lines and the switching equipment supply F i g. 1 is a block diagram of an embodiment and thereby both economical and sufficient example of a device according to the invention,
work reliably. F i g. 2 the distribution of the signals in the circulating

There are already devices known that store the above 30 of the phase counter,

fulfill the tasks mentioned. Usually it is F i g. 3 the sampling of an undisturbed signal (a)

electromechanical devices and a disturbed signal (b) by a scanning

that work with relays, selectors and pulse counters. signal (k),

Their main disadvantages are: Large space F i g. 4 is a graphical representation of various required by the large dimensions of the electro- 35 scanning pulses, which are generated by a single clock genemechanical Components, relatively low workers are produced,

speed and high maintenance requirements, except- F i g. 5 shows an embodiment of a decoder shell One can generally use a single device that does not have the outputs of the multi-channel phases use for several channels, but connect the counter to the logic control circuit, must provide a unit for each channel. At 4 ° F i g. 6 is a circuit diagram of part of the logic The reason for these disadvantages is the area of application control circuit, which is used for troubleshooting and such devices, especially on remote dialing systems, are used to generate clock signals for pulse length measurement,

The operation of several trunk lines according to one- Fig. 7 is a circuit diagram of part of the logic

other by a time division multiplex device has 45 control circuit that is responsible for registering the connection

compared to the advantage that the number of the dung state is used,

Construction of devices of the above type required F i g. 8 is a circuit diagram of part of the logic

borrowed circuit arrangements significantly reduced control circuitry used to register the selected

can be, since one and the same scarf digits are used, and

arrangement information that varies from 5 ° F i g. 9 is a circuit diagram of part of the logic

NEN trunks originate, can process. One control circuit that belongs to a clock,

However, directions of this type are only worthwhile, The circuit arrangement shown in FIG

when scanning the trunk lines in proportion- contains two time division multiplexers Ai ₁ , M ₂ , through the

moderately short time intervals, which in practice involve several cores A _x , A ₂ ... A _n or C ₁ , C ₂ ... C _n

may be a maximum of approximately 1 ms. This is done by 55 of η trunk lines with a logic circuit

indicates that the devices are connected to the RK during a cycle, which in turn provides information about

different trunk lines only each for essential connections C ₁ ,, S and R to a multi-channel

lent shorter periods of time, for only a few. Bi-directional counter (binary phase counter) CPB

Microseconds, are available. supplies. The counter CPB consists of a logical

The well-known electronic time-division multiplexing circuit RC and four delay lines L ₁ , L ₂ ,

mediation systems (see e.g. Siemens magazine, L ₃ , L ₄ , which form circulating storage.

37/163, Vol. 2, pp. 61 to 67, and IEEE Transactions rather serve not only to accumulate the bits, but also

on Communication and Electronics from November as dynamic memory, so that in the individual

1964, pp. 612 to 620) can, however, be consecutively in certain bits counted on the channels

knew electromechanical devices only with difficulty 65 time intervals at the entrance of this circulating storage system

adjust. The problems consist primarily in appearing until a new count has its value and

. the translation of the criteria by which changes their arrangement,

Electromechanical devices supplied code in the When a pulse T arrives

3 4

Gates P ₁ , P ₂ , P ₃ , P ₄ the transmission of the phases of the different group also called »digital

Identify the signals present at the outputs of the counter CPB to filter «. In the second phases (2, 12, 22

an output register RU. A signal (time signal) is counted to the logic switch to 82), which the

tion RK are working as an auxiliary circulating storage task, the duration of the in the first phase

Auxiliary delay line L ₅ and a shift register 5 to measure tapped signals. These signals that

R _fs , referred to as the »next phase register« - derived from the counter CPB , begin every-

net can be connected. ^ times if there is a voltage jump on line A.

Each of the four circulating memories of the selector CPB occurs to earth, and they provide the time information,

contains ρ bits that are consecutively in the same and that are required to generate the dial pulses and

periodically recurring time intervals, the so- io other telephone criteria within the specified

phases, appear at the exit. Recognize the respective tolerances

four at the same time at the output of the circulating accumulator In the third phases (3, 13, 23 to 83)

appearing bits correspond to a decimal number K digits registered, which correspond to the call status.

between 1 and 16. This number K appears to speak cyclically. In the other seven phases of the den

at time intervals that correspond to the transit time of the circulation »s trunk lines allocated to groups C _s

memory, except if digits of the dialed number are counted at the inputs, which are up to

Cp, S and R of the counter signals arrive. When stored for transfer to the output register RU

The arrival of the signal C " will be stored in the memory in the chert.

phase concerned instead of the number K the number When receiving signals that the selected

K + l stored if the sign - »o digits and telephone criteria are concerned at the same time, is used with

signals = 1 is present while the number K-1 is time-division multiplexed, as shown in

is stored when the sign signal S the F i g. 3 is shown in which you can use a

Has value 0. Sampling signal K the voltage state of the official

The signal R is a reset signal that lines all 4 bits Λ, and C ₁ at regular time intervals,

of the phase concerned. 13 e.g. every 6 ms, scanned. So every 6 ms will be all

In the described embodiment, inter-trunk lines are queried, for which purpose 100 μ $ are required, the circular memory contains 100 bits, each of which is 1 ^ s . The sampling signal IC is created by being separated from one another, so that the 4 bits of a coincidence of the sampling signal M _A with any sampling phase i pulse every 100 μβ at the output φ _ν φ _η , φ ₂₁ to ψ _{Β1 of} the first phases,
seem to be. Like F i g. 2 shows, the 100 bits circulating through relay inductances, contact bouncing, memory are divided into ten groups for capacitor discharges, etc., interference pulses can be divided into 10 bits each. The first nine groups IC to arise, which cause an erroneous recognition of the dialing PC are a connection path or a pulse to be checked and the telephone criteria, assigned to the trunk, while the last when they coincide with the scanning. Such group 0, which contains the bits of phases 91 to 100, is switched off by criteria that hold, to implement a very precise clock, the first phases called "digital filters" are used, which are used to determine the conversation time. each group are delivered and the device does not serve time. to that transmitted by the selection pulse

On output lines A and C the time-division multiplexed instantaneous value, but instead on the time integral devices M ₁ or M ₂ , the voltage 4 ° of these impulses occur one after the other, similar to voltage states (battery or earth) of the trunk line - in the case of electromechanical devices,
gen Ai and C _1, respectively. During the first ten phases 1 the digital filter works according to the following to 10, the first exchange line is exactly for the principle: For each sampling signal K determines the allocated period of 10 μ5 connected, while logic circuit RK whether the counting after the second ten phases 11 to 20 the second 45 is connected upwards (addition) or backwards (subtraction) trunk line, etc. up to the ninth and should take place what from the scanned voltage last trunk line. For this, the multiplex value "battery voltage" or "earth" depends, switch controlled by various sampling, if in the count up the number 2 ^m reaches all will be (m = number of circulating memory of the counter produced by a single clock generator. This in F i g. 50 pulses shown sawn 4 CPB which understood in the phases of the digital filter of a main scanning signal M _4, which will apply the time), is blocked counting. When the duration T _A has and occurs with the time interval T _c , counting down, the counting is blocked if, out of ten, pulse sequences C ₁ , c ₂ to C ₁₀ , the duration of which has reached the number 1. If there are no changes in the voltage state equal to one tenth of T _A and the time of the exchange lines, the distance is equal to T _A , out of 100 signals φ _ν φ ₂ 55 there are _{circular memories or delay bis (P 100} , whose duration is equal to one tenth of the continuous lines of the counter CPB during the first phases of the pulses C ₁ and their time interval T _A are in a stable state (1 or 2 ^m ).
In the present exemplary embodiment, T _c Um is a disturbance with a certainty of a useful 6 ms and T _A 100 μβ; the pulses C ₁ last 10 μδ, signal pulse or an actual signal jump and their spacing is 100 μβ, the pulses φ; If it takes to be able to distinguish 60, it is sufficient to have a number r 1 μβ, and their distance is 100 μβ. of samples that are 2 ^m - 1 larger, i.e. the

In the first phases (1, 11, 21 to 81) each number of the disturbed samples can be taken,

Group (F i g. 2), the received signals are so around a stable setting of the first phases in the

analyzed that disturbances that allow the impulses of one or another stable state.

Telephony criteria are superimposed, are eliminated; 65 The digital filter carries out a statistical evaluation

the device thus works like an interference eliminator and is capable of generating a useful signal with the same

filter. However, since the analysis can be distinguished from an interfering signal by means of logical assurance

drive takes place, you can use the bits in the first like devices that respond to the integral of the signals.

5 6

to speak. The number of revolving meters used is considered, provided that the correct one is adhered to

memory determines the number of samples, the voltage within the specified tolerances

for troubleshooting in addition to the error signals generated that are later used as dialing, end of digits,

detection are required. End-of-election and start-of-conversation pulses are used

In the present example, two will be 5 for this. The dialing pulses are in the corresponding four circulating memories of the counter CPB, in the corresponding seven phases to the circulating memories gePhasen of the digital filter z. B. sends the circular memory with, in order to be stored there in sequence, delay lines L ₁ tJhd'L ,, used. the while the last two above-mentioned these circular memories therefore assume the state 1 in the first signals in the third phases through the register R _fs phases when the line A end-ίο are sent to the circular memories to which is validly connected to earth , and to register the counter connection status,
stand 4, when the line A is finally connected to the battery voltage when registering the dialed digits. If z. B. corresponds to the corresponding phases during the Im voltage on line A from earth to pulse counting a digit in a phase and a bit in battery _{voltage, this results in the 15 of the delay line L 5} . The end-of-digits signal counter readings, which are shown below with statuses, clears this bit and saves it in register R _ls . The output of this register saves this rem interest in the successive sampling bits in the following microsecond again in L ₅ and samples the following values: 4-3-2-1-1 as shown in FIG. 3, (a) prepares the circulating memory in the following phase. Assume that on μ for receiving the next digit before.
the second sampling a disturbance occurs in which the voltage is equal to the battery voltage or greater in the following the structure of the logic circuit, so that the states of the first phase RK on the basis of FIG. 5 to 9 explained. For the sake of simplicity, the values 4-3-4-3-2-1-1, as in Fig. 3, (b) , the functional description is set to. "5 processes of the ten phases of the first group untf"

The transition 3-4 is caused by the disturbance. the phases that fulfill the task of a watch,

After the disturbance has subsided, the circulating memory is limited. .-

however, the counting backwards continues until the The outputs U _x , U ₁ , U _t , U _{1 of} the circular memory

State 1 is reached. As soon as the state 1 reaches L ₁ . L ₁ , L ₃ and L _A are via one in FIG. 5 shown

is. an earth signal is output, and the span-30 set binary-decimal decoder circuit with. the

The transition from battery to earth is connected as a logic circuit KK. The Andes

Real transition viewed, the binary signals pending for the transmission of a terminals IZ ₁ , T7, to U _v TJ ₄

Remote speaking criterion is valid. are determined by the AND gates AND _{1 n} . AND. ,,,

The digital filter works at transitions from earth to AND _xtD into decimal _{signals D 1} , D ₂ to D _18.

Similar to battery and differentiates at the same time. These decimal signals become the logical ones

if fed between an interference signal and a real circuit RK. T7, is the complement

Voltage jump. Isolated disturbances that are relatively different from U ₁ .

far from a real voltage jump Tn of phase 1, the digital filter is through a

are switched off with certainty because an arrangement is implemented which must count up. if

single sampling, the line Λ is on battery voltage on a voltage change 40 (/ 1 = 1).

the trunk indicates not as a useful signal and which stops when the circulating memory of the meter

jump can be viewed. reach state 4 (D _x = 1). The same

In order to be able to decide whether a voltage order must count backwards when line A

Change as transition or useful signal jump to earth voltage (A = 0), and stop when

can be sought, the as an auxiliary circulating 45 the circulating memory is the state 1 (D ₁ = 1)

memory working delay line L ₅ . that are rich.

the logic circuit RK is connected. The arrangement operates according to the following

be interposed. More precisely, in logical functions:

the circulating memory with the line L ₅ every time _ _ _ ^

then 1 bit stored if the digital filter 50 L .. - [U _x A ■ U ₁ A) M _{A: l} , (1)

reaches steady state 4 (battery), and the S = OA. (2) bit is removed every time the digital filter

reaches stable state 1 (earth). Really- The writing and clearing of the bits in the

speed is it an addition or auxiliary circulating memory L ₅ is through the following

Subtraction of a bit from the memory L ₅ . which determines one logical equation:

real voltage jump on line A an- ο = in χ U (/) (3)

indicates. £ s' 4 1 5 '? I · \'

The timing signal, which begins during the second phase, when a bit signal is sent to the register R _ls , starts whenever a real one is determined by the following equation:

Signal jump on line A to earth instead of- 60 c = m ^ + TI? 1 U \

finds. And for this purpose the register R, _s ^{n K} * ^{Ls ü} »^^ '«' ™

interposed. In this register, the S _ff becomes very general that of the register

Writing of a bit during the period of R _ls denotes the input signal which is

a microsecond allocated to a phase. dependence on the signals from which it generates

and this bit appears at the output for the whole of 65, and of the logical operations of these

Duration and only for the duration of the following phase. Signals can take on different values.

The signal that comes from the register R _ts for the following The chronometer implemented in phase 2 switches phase is used as the start signal for a chronometer at every second sampling pulse M _A , stops

at count value 16, then switches back to 0 and starts this count anew each time a voltage jump to earth has taken place on line A. Because the chronometer can only count upwards, the counting signals C _pt coincide with the counting signals of the direction S ₂ . The switching back of the chronometer to * 0 and the subsequent start of counting are determined by a reset signal R _{t of} the counter CPB . This reset signal must take into account the bits that can from register R _{ts in} order to be able to assess whether the voltage jump on line A to earth is a useful signal or a disturbance.

The logical functions that the arrangement performs in phase 2 are:

^C P2 ⁼ Si =

R ₁ = R / s A ~ M _B <Pj ,.

Mβ corresponds to two signals M _a .

In Fig. 6 shows the circuits that make the Realize equations (1) to (6) above.

To implement equation (1), the signal D _{1 is} fed via an inverter I _1R and the signal Ά to the two inputs of an AND gate AND _lR , the output of which is connected to an input of an OR gate OR _{t R.} The signal D ₄ via an inverter / _{2 R} and the signal A are fed to the two inputs of an AND gate AND _{t R;} the output of this AND gate is connected to the second input of the OR gate OR _1R . The output signal of the OR gate OR _lR is fed to a first input of an AND gate AND _sR , at whose second and third input the signals M _A and <p are applied. This AND gate supplies the signal C _pv which is fed to an output C "of the logic circuit via an OR gate OR _Cp.

Equation (2) is implemented by an AND gate AND _{4 R} , the two inputs of which are supplied with the scanning signals φ _ι and the output signal of the AND gate AND _1R. The output of the AND gate AND _1R is connected to an output S of the logic circuit RK via an OR gate OR ₅ .

The equation (3) for storing in the auxiliary circulating memory L ₅ is implemented by an AND gate AND _tR , an OR gate OR _{t R} and an AND gate AND _1R . The AND gate AND _{8 R} is supplied with the signal D ₁ , which comes from the decoder circuit shown in FIG. 5, and a signal U _s from the output of the auxiliary circulating memory L _5. The OR gate OR _{t R} is fed by the output signal of the AND gate AND _eR and the signal D _4. The output signal of the OR gate OR _{2 R is applied to} the inputs of the AND gate AND _1R and the sampling signal φ _ν the output signal of the AND gate AND _1R passes through an OR gate OjR, _r . to the input of the auxiliary circulating tank L ₅ .

The equation (4) for storing in the register R _ls is implemented by an exclusive OR gate OE and an AND gate AND _{8 R.} The input signal and the output signal from L ₅ are applied to the two inputs of the gate OE . The output of the gate OE is connected to the first input of the AND gate AND _hR , the second input of which is supplied with the scanning signal φ _1. The output of the AND gate AND _{8 R} is via an OR gate

OR _{4 R} connected to the input of the register R _ts .

The equation (S) for the count and direction of counting of the pulse chronometer is implemented by an AND gate AND _{5 R} , whose inputs the signals M _B , ^ _x and D _{18 are} fed and whose output via the OR gate OR _Cp the output Cp and via the OR gate OR ₈ to the

ίο output ^ of the logic circuit RK is connected.

The equation (6) for switching the chronometer back to zero and for starting the chronometer is implemented by an AND gate AND _{9 R} , at whose inputs the output signal of the register R _ls , the sampling signal φ _ν, the signal M _B and the status signal Ά the trunk. The output of this AND gate is via an OR gate OR _R with the output R of the logical

ao circuit RK connected.

The OR gates OR _{3 R} or OA _{4 R} connected to the input of the auxiliary circulating memory L ₅ and the input of the register R _(i ) have the task of providing these facilities for the logic circuit RK in all phases in which they are required The gates OR _CP , OR ₅ and OR _R have the task of connecting the respective outputs for the various phases with the outputs CP, S and R of the logic circuit RK are reserved for the clock used to determine the time, which will be discussed later.

In phase 3, the arrangement works as a memory for the connection state in which it contains all possible Assigns conversation states to one of the phase states provided for this purpose. This can for example, can be done in the following way:

D ₁ = exchange line free;

D ₂ = assignment of the exchange connection; this is determined on the basis of a transition of the voltage on the line C of the relevant exchange line to earth. The transition from D ₁ to D ₂ sets the register R _ls to initiate the registration of the dialed digits;

D ₃ = end of election; the end of the election is determined on the basis of the setting of the register R _fs in phase 2;

D ₄ = start of conversation; the beginning of the conversation is determined on the basis of the fact that the voltage on line A changes to earth voltage for at least 130 ms (A = O);

D ₁ = free trunk line; this state corresponds to a free exchange line and is recognized by the absence of the earth voltage on line C.

The counting up of the phase counter in this particular phase depends on the presence of the signals on the trunks and on the counts in the chronometer phase.

In addition to the state of wire A of the exchange line, the state of wire C is also of interest in order to be able to determine whether the exchange line is busy or free.

009 626/66

9 10

The advancing of the counter is determined by the signal J ^ is the output signal of a function: chers, which shifts the signal S _c by two or more phases _ _c _ ^ _n , o -xrn-LP 7ni. A storage in the auxiliary circulating memory L ₅ ^L P 3 - ^Ä 3 - "Ps l ^{c υ} ι " + " ^K fs ^{A c υ} 2 + ^K fs Λ U ₃ ). Takes place when a bit from the register R, _s arrives

(7) 5 Storage must be carried out in all relevant phases of the

Dialing digit registration must be guaranteed.

In this equation, the first term in The equations for storing in the auxiliary circulation

the bracket on the occupancy status of the office memory L ₅ and for storage in the register R, _s ,

management, the second term at the end of the election and the one that takes place in phase 3:

third term at the beginning of the conversation. ίο ω

The bits in the circular memories are deleted, S _{L 5} = (R, _s + 7 ?, _s i / ₅ ) ^) Ψι · (13)

when the trunk becomes free again. The logical »= ♦

The equation for this deletion is: S = <p Z! D (14)

#s = ( ^D 2 + ^D s + ^D i) ^c 9V (8) _{1J $} pig equation (14) ensures that the digits

At the end of the election and, in the event that it becomes vacant, registration only begins if the relevant

the trunk to indicate the beginning of the call is busy and is used for the

the chronometer must register the first digit new information. The digits are in

on the connection status through the register R, _s the successive phases in sequence

deliver. Correspondingly, Rgs »o is registered in the register and the transition from registration

a bit is saved when the chronometer records a digit on the registration of the next digit

on wire A a transition to earth, which has to be a bit more in register R _,? get saved. the

than 130 ms is determined. The save storage in this register is done after the first

of the bit in the register R _ls is carried out according to the following number by the digit end signal and by the Bik

Equation: »5 determined in the auxiliary circulating accumulator L ₅ . The associated ^

c \ λ t \ -χ (n \ equation is:

SfS = (P ₂ M ₈ D _n A. ( ⁹ ) ίο

In phases 4 to 10, during which the ge $ is ~ Rifls ^ L Φι ·

selected digits 'are registered, digits-' ~

received signals and end-of-digit signals that were registered in the 30 Here R, _{c is} the output signal of a memory, second phase, and signals that shift the signal S _fc by 2 or more phases, relate to the occupancy of the trunk line, such as Die Registered digits are deleted when the deletion command of the trunk line registered in phase 3 becomes available, for which a special digit. The digit signal that comes from phase 2 is provided in a memory register in which, when free, when the chronometer has saved the number 35 of the trunk line and when the number of scans (between 3 and 8) has been counted, it is cleared when phase 1 returns will. The equals on wire A, an actual voltage for storage and deletion, read: jump to battery voltage has taken place. ς = η (λ f, \ This signal is determined by the following logical '"^''· * · ^ function: 4 ° R _r = φ _χ . (17)

8 ■

S _c = (p, M _B AR _fs 2 D _1. (IQ) The deletion affects all registered digits and

^{i = 3} therefore takes place in all phases which the digits

The first four factors affect pre-registration; the following applies

presence of an actual voltage transition 45 logical equation:

according to battery voltage in phase 2 safe, and the 10

Sum term ensures that the samples in ^ 4 to 10 ^{= F} r 2 9Ί · · (***)

the allotted time periods fall. , = *

The end of digits signal is available when the

Chronometer a transition to battery voltage 5 ° In Fig. 7, the circuits are shown, which for

detects that lasts longer than 130 ms. In the ent- realization of equations (7), (8), (9), (14) and

speaking logical function (16). The equation (7) is given by a

c _ _M λ ρ »(λλ \ OR gate OR _{5 R} realized, its three inputs

* tc - <P2 ^M BAL> _n (11} _the output signal of an AND gate AND _10R , the

_{5 R.}

_the output signal of an AND gate AND _10R , the last two factors ensure that the 55 forms the first term of the logical sum, the necessary time segment is passed through. The output signal of an AND gate AND _{12 R} , which forms the registration of the dialing digits alternately in the second term of the sum, and the output _{corresponding} phases when the digit signal of an AND gate AND 13R, the third signal and the signal from the auxiliary circulating memory L ₅ term forms, are supplied. The inputs of the are present at the same time. ^6o AND gate AND _{10 R} are the decoder signal D ₁

The equation for the actuation of the phase and the signal C supplied, which reads a voltage counter: 'indicates transition on the wire C to earth. The

ω inputs of the AND gate AND _12R are the ^ signal

^ pi bi »10 ^{= 1} ^ i to 10 ^{= ß} [f _ä ^ φι · (12) D ₂ from the decoder, the signal ü, which is a voltage

■ »■ - ■ - * 65 indicates transition to earth on core C , the

Here the samples appear for the phases 4 signal Ά, which shows a voltage transition to earth to 10, and it is taken into account that these phases on the wire / i indicate, and the output signal of all must be served. Register R _ls supplied. At the inputs of the AND

11 12

Gate AND _{13 R} are the signals ?, D ₃ and the OR gates OR _Cp and OR _S with the outputs

Output signal of the register R _ls . The output of the C ″ and 5 of the logic circuit RK is coupled.

OR gate OR _{b R} is connected to an input of an AND The first input of AND gate AND _21R is via

Gate AND _{n R} connected to the other a memory circuit R _c with the output of the

Input the scanning signal ψ ₃ is. The output of AND gate AND DIE 5 _{H 20} connected at which the CLOSE

This AND gate is via the OR gate OR _Cp remote signal occurs; the second input is at the exit

and OR ₅ with the outputs C _p and 5 of the logical _{output of the OR gate OA 8 R} connected to the

Circuit RK connected. '¥ ■■ - *' collects scanning signals ψ _χ to φ ₁₀ , and the third input

Equation (8) is passed through an OR gate to the output of the auxiliary circulating memory

OR _{6 R} realized, to whose inputs the signals D ₂ , io L _{5 are} connected.

D ₃ and D ₄ lie and the output of which is connected to an input. Equation (13) for storing in the auxiliary gear of an ^ AND gate AND _{uR is} connected. Circulating memory L ₅ is realized by an AND gate A second input of this AND gate is the AND _{25 R} , whose two inputs are supplied with the output signal C, which relates to the wire C, output signals of the OR gate OA _{8 R} and one and The scanning signal 15 of the OR gate OR _{9 R is} applied to a third input. A first one <p ₃ . The output R _{3 of} the AND gate AND _liR is the output of the OR gate OR _{9 R} is connected to the output via the OR gate OR _R to the output R of the register R _ls , and a second logic circuit RK is connected. gang is to the output of an AND gate AND., _{4 R}

The equation (9) for storing in the register is attached.

R _ls during phase 2 is through an AND gate *> A first input of the AND gate A ND _UR is

AND _isR implemented, the output of which is connected to the output of the OR via an inverter circuit

Gate OA _{4 Ä} connected to the input of the register R, _s ver Register R _ts , a second input is on

is bound. The inputs of the AND gate Λ ND _lsK the output of the auxiliary flow memory L ₅ .

are the scanning signal ψ ₂ , the scanning signal MB of the closed.

Chronometer, the signal ~ Ä and the signal D _n to- »5 Equation (15) for storage in the register

guided. . R _ls except when registering the digits

Equation (14) is realized by an AND gate, the first is realized by an AND gate AND _{22 R} AND _11R , the first input of which is the Ab-, the first input of which is the digit end key signal <p ₃ and the second input of the output signal are supplied from the AND gate A ND _{n R} via a memory _{output signal of} the AND gate AND loR. 30 circuit R _{fc is} supplied; a second input. The output of the AND gate AND _11R is coupled to the sampling signals from the output of the OR register R _ls , as shown in FIG. 8 is shown. Gatters OA _{8 R} supplied. The output of the AND

The equation (16) for storing in the register gate A ND _2. , _R is via the OR gate OA _{4 R}

S _r is implemented by an AND gate AND _16R , connected to the input of the register /? ^. at

the signal D ₁ from the decoder and the scanning signal 35 of the registration of the first digit

¹ P _{3 are} fed., On the other hand in the register R _{/ s} by the AND-

The register F _R is deleted by the gate AND _11R (Fig. 7) incoming signal, as

Sampling signal φ _ν that occurs in the first phase. That has already been mentioned.

Output signal of the register F ^, which is used for deletion. Equation (18) relating to the deletion of digits

is used for the registered dialing digits, the one in Fig. 8 40 is implemented by an AND gate AND _23R , des-

circuit arrangement shown supplied. sen first input that from the deletion register F ^

In Fig. 8 the circuits for implementation ((Fig. 7) are fed; the second input is given by equations (10), (11), (12), (13), (15) and (18) from the OR -Gate OR _8R collected display, probe signals fed in. The output of the AND gate

The equation (10) is implemented by an AND gate 45 AND ₂₃₁₁ is coupled via the OR gate OR _R to the AND _lsR , AND _2oR and an OR gate OA ₇ ^ output R of the logic circuit RK. The inputs of the AND gate AND _{mR for the counting of} the conversation time are the signals of is the scanning signal φ ₂ , the scanning signal M _{B of} the clock, which synchronizes the whole arrangement, chronometer and the state of the office by means of the phase counter CPB, the register R _ls and line related signal A supplied. The output 5 ° of the decoding circuit of the AND gate AND _{18 R} shown in FIG. 5 is connected to a first objection. The accuracy of the clock formed in this way escaped the AND gate AND _{20 R} connected. The speaks of the accuracy of the crystal oscillator, which _{controls the inputs of the OR gate OA 7 R} are the signals Tatktgeber.

D ₃ to D _s supplied by the decoder, and the output The clock works in phases 91 to 100. Since the

this OR gate is at the second input 55 bits of each phase at regular time intervals

of the AND gate AND _{20 R} connected. The third input output of the circulating storage can arrive, one can

gang receives a signal from register R, _s after a z. B. the sampling signals of phase 91 as a pattern for

Bit at the input of the central OR gate OA ₄ , the delivery of the counting signal C _p to the counter CPB

which take the AND gate shown in FIG. The counter CPB can in phase 91 as

AND _{11R is} connected, has arrived. 60 in any other phase the number N ₁ <£ 2 _m

Count the equation pertaining to the end-of-digit signal, where m (e.g. 4) is the number of parallel

(11) is implemented by an AND gate AND _{19 R} , which is a circulating memory. If the state N _{1 is} reached, so

whose first input, the output signal of the AND, the decoding circuit clears the for this state

Gate 18 R and its second input takes the signal in this phase bits and writes them in

D _n are supplied by the decoder. 63 the register R _ls , the output of which in the following

The equation (12) for the counting in the Regi phase supplies a counting signal C _p for the counter CPB ,

In phase 92 occurs after / v ^ signals in the

AND gate AND _iiR implemented, the output of which receives a count signal via phase 91. If in appropriate

If the counter has once reached the state N _t ^ 2 " in phase 92, the bits are deleted in the same way and written into register R _ts , which supplies a counting signal for the following phase. In this way, the end time scanning signals are counted in sequence with the corresponding numbers N ₁ N ₁ N ₁ , N _t N ^ i _{v and so on in the various phases.} "&"'':

In the present embodiment of the invention, the sampling signal has a period of 100 µs, and therefore ten thousandths of a second are counted in the 91st phase. The decoding circuit for state 10 clears the corresponding bits in the circular memories in this phase and generates a counting signal for phase 92 through register R _ls , which corresponds to thousandths of a second. In a similar way, the process is repeated for the following phases. In phase 96, the tens of seconds or phase 98, which correspond to tens of minutes, the decoding circuit clears the bits after state 6 (and not state 10 as is otherwise) is reached.

That part of the logic circuit RK which works together with the counter CPB is shown in FIG. 9 only for phases 91 and 92 for the sake of simplicity. The signal T ₉₁ , which has a duration of 1 με and a period of 100 | * s, is _{fed directly to an input Cp 91 of} the OR gate OR _Cp and an input S _{91 of} the OR gate OR _S so that the counter CPB increments one digit in phase 91 each time a pulse r _9i arrives. The cancellation signal for the bits in phase 91 appears when a signal at the output D _{19 of} the decoding circuit and a pulse ψ _{9ϊ are} present. The occurrence of this cancellation signal is determined by the following logical equation:

The logic function represented by this equation is implemented by an AND gate AND _aR , one input of which is the signal T ₉₁ and the second input of which is the signal D ₁ . are supplied. The output of this AND gate is coupled through the OR gate OR _R R to the output of the logic circuit RK and through the OR gate OR to the register _iR R _{t $.}

The counting of the thousandths of a second takes place in phase 92. So that one pulse can be counted in phase 92 for every ten pulses in phase 91, the signal for this phase must be supplied by register R _ls and by the scanning signal <r _9i. The corresponding logical equation is:

"," - J _9t -. <r _es «fs · {-Μ)

This equation is implemented by an AND gate AND _31R , the first input of which is the signal <p _9S and the second input of which is the output signal of the register R ₁₅ . The output of this AND gate is connected to the output C " via the OR gate OR _Cp and to the output S via the OR gate OR _S.

The clearing of the bits in phase 92 is given by the following logical equation:

Ru = D _u q- _n R, _t - (21)

This equation is implemented by an AND gate AND _isR , the first input of which is connected to the The output of the AND gate AND _ilR and its second input are connected to the output D _{10 of} the decoding circuit. The output of the AND gate AND _nR is via the OR gate OR _R with the

S output R of the logic circuit RK and via the OR gate OR _iR connected to register R _ls . The circuits described are repeated

in a corresponding manner for the following phases with the exception of phases 96 and 98, the tens

ίο correspond to seconds or minutes, there the bits must be cleared in these phases when the count value 6 and not when the count value 10 is reached. The 'through the 4 bits of the different Binary numbers represented in phases are in sequence

> s after from phase 100 to phase 91 the tens of hours, hours, tens of minutes, minutes, etc. up to ten thousandths of a second, as in FIG. 2 is shown. The same arrangement consisting of the four gates P ₁ , _{P 1} , P ₃ and P ₄ (Fig. 1)

so and for the transmission of the dialing digit and the telephone criteria from the circulating memories of the counter CPB to the output register /? I /, this register can also use digits that correspond to the times (hours, minutes, seconds) and in phases 10ft

as saved up to 95. this makes possible a direct transmission of the exact duration of a certain process on the tested connection path to the output device; you can get the exact Clock also for controlling external Ge use rate, e.g. B. by 20 μβ lasting pulses for receive the signals of the international telex telegraph code.

As mentioned, the phase counter and its interconnections with the register R ₁ , from Receiving mechanism for the dialing digits and used by the clock for completely different purposes, so that a substantial simplification and cheaper results. A particular advantage arises from the fact that the precise work the clock is a sign of the exact functioning of all devices, so there is constant control available for the functioning of the facility.

Claims (6)

Patent claims: 1. Circuit arrangement for a cyclically operating electronic reception, evaluation and Registration device for traffic measurement for several trunk lines in a telephone exchange, with time division multiplex devices for alternating connection of the trunk line to be tested, with a logic circuit that starts with connected to the output of the time division multiplex devices is and information to a phase counter supplies, which in turn supplies the evaluated data via a series of gates to an output register, the logic circuit dem Phase counter time counting control commands of the Duration of the telephone criteria supplies to the Dialing digits concern pulses from pulses from other telephone operations, such as information with regard to the connection status and its duration, to be able to distinguish, thereby 65. indicates that the _{circular memories (L 1} to L ₄ ) of the phase counter (CPB) contain a number ρ bits which are divided into groups (10) and in successive time segments (Phases) are arranged, each exchange line (A ₁ , C,) a group (iC; IC to 9C) is assigned that during the first phase (q ₁ , <p _lv q> 2l to T ₉₁ ) each of an exchange line assigned group (IC to 9C) a bit is stored that indicates whether a signal occurring on the relevant trunk line is a useful signal ₄ , that bits are registered in the second phase that indicate the duration of the scanned pulses, based on which duration The meaning of the impulses can be determined that in the third phase bits are registered that indicate the connection status (trunk free, trunk busy, end of dialing), etc.), and that in the other phases of these groups (IC to 9C) the selection digits of the telephone system, connected to the trunk. 2. Circuit arrangement according to claim 1, characterized in that to distinguish between glitches and telephone »o criteria in the first phase of each group assigned to an exchange line for each sample of the signal of the exchange line through the logic circuit (RK) the count (C _p ) and the sign of the count (S; addition or subtraction) for the counter (CPB) is controlled depending on the voltage value (battery or earth) of the sample for an upward or downward count, the upward counting being terminated when the counter counts the number 2 ^{m has} reached (m = number of circulating memories of the phase counter that contain the bits that control the sampled signals), while the downward counting is ended when the counters reach the value 1, whereby these count values are also retained as long as the state of the trunk lines does not change, that also changes the voltage of the trunk line for a number of samples greater than 2 ^m - 1 is registered in phase 1 of each group as a real voltage jump (useful signal), and that the perception of a real voltage jump starts a chronometer, which is used to differentiate the length of the pulses forming the telephone criteria to be tested. 3. Circuit arrangement according to claim 2, characterized in that the counting signal C _P1 for the first phase of each group of the phase counter (CPB) by the logic function the signal that indicates the counting direction (sign) through the function ⁵⁵ the signal for storage in a shift register for the start of the chronometer in the event of a real transition of the trunk state on earth by function is shown, where T _{1 is} the scanning signal of the first phase, M _{A is} the scanning signal of the trunk line, A is the signal that indicates the voltage state of the trunk line (battery or earth), the signals D ₁ , D. to D ₁₆ recoded to a decimal code Output signal of the phase counter, U ₆ the signal coming from an auxiliary circulating memory (L ₅ ), S _L? the signal entering an auxiliary circulating memory and through the function S ₁₅ = (D ₄ + ZJ ₁ U ₅ ) Ip ₁ is represented mean. 4. Circuit arrangement according to claim 1, characterized in that the duration of the telephone criteria pulses of the trunk sampling pulses is measured by a signal which is that represented by the bits of the second phase Counting up counts, this signal by the following logic function = S ₂ = Μ _Β φ ₂ Ό _ίβ is expressed and <p _{2 is} the phase 2 scanning signal, M _{B is} the signal that arrives every two scanning signals of the trunk lines, and D _{lt is} the signal indicating the presence of a bit in all circular memories of the counter corresponding to phase 2 and the count of the bits in said phase stops that the resetting to 0 and the subsequent start of the counter is controlled by a complete transition of the voltage of wire A to earth by a signal that the logic function R ₂ = Rf _S Ä ~ M _B <p ₂ where R _{ls is} the signal of the following phase which corresponds to a complete transition of the signal ~ Ä to ground, that the signals related to the selection digits by the logic function S _c = <p ₂ M _B AR _ls j? D ₁ and that the final digit signals S _lc and final selection signals S _{/ s are} sent after the chronometer has registered a voltage transition of the exchange line to battery in the first case and a voltage transition to earth which last longer than 130} is in the second case, which Signals through the functions Sn - q> ₂ M _B D _xl A , being represented. 5. Circuit arrangement according to claim 1, characterized in that the registration of the Selection digits in the last seven phases of each group when the occupancy signal arrives Trunking begins in phase 3 and on arrival of the digit signals from the second phase begins, the advancement of the phase counter being controlled by a signal that the equation Iu W'4 to IO ~ ° 4 to 10 ~~ ⁿ c ^u z 2Li Ti corresponds, where <?, the scanning signals of phases 4 to 10, R _c the digit signal stored in the second phase and U _s the at the output of the 009 626 60 Auxiliary circulating memory is, which results from the delay of the signal according to the function results, where R _{ls is} the signal * which indicates the registration of the occupancy in the third phase, and U _{5 is} the output signal of the auxiliary circulating memory, and that the digits are deleted by a signal that has the following function 4 to 10 ΨΙ> where F _{r is} a signal stored in the third phase and corresponds to the state of the free trunk. 6. Circuit arrangement according to one of the preceding »o previous claims, characterized in that in the phases of the last group (0) by the logic circuit (RK) and by the phase counter (CPB) the times relating to the operations of the telephone traffic are registered, as where in the first phase the scanning signals that follow one another in ten thousandths of a second are counted, in the second phase a signal for ten signals and thus thousandths of a second are counted in the first phase, hundredths of a second in the third phase, tenths of a second in the fourth phase, etc. up to the tenth phase in which tens of hours are counted, e.g. in the phases in which the time counting takes place from phase 91 to phase 100, the sampling signals φ ₉₁ counted, which have a period of ten thousandths of a second, the counting is cleared when the counter has the state 10 according to the function ρ P J ~% ^Λ 9ΐ ° fs "Pgi ^ io reached, at the same time the same signal is sent to the register of the following phase (R _sl ) so that a pulse can be registered in phase 92 if the pulses stored in phase 91 are deleted, the counting signal for phase 92 by the function P 92 92 T9 ' ¹ fs is expressed and this function is taken into account the signal Rf ₃ coming from the register of the following phase (R, _s ) and similarly the signals for the registration of larger time units are repeated in the following phases. For this purpose 3 sheets of drawings