DE1537636C - Binary clock signal-controlled switching arrangement in MOS circuit technology - Google Patents

Description

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ratio to the circuit capacitor, the charge is shown in the schematic drawings.

application of the circuit capacitor to the parasitic embodiments.

tary capacity distributed. Then the cargo is on the fi g. 1 shows a preferred embodiment of FIG

Circuit capacitor not as big as possible, invention with a charging capacitor and a

and the voltage on the Gatt electrode is not 5 control signal;

by the full value of the control signal voltage er F i g. 2 shows a second embodiment of FIG

increases. Invention;

In the MOS driver, the voltage at the F i g. 3 shows a further embodiment of FIG

Gatt electrode at least one specific Schwel- invention with a device for generating a

value be more negative than the one at the source ίο control signal, and

or emitter electrode to connect the transistor. 4 refers to curves that the working switching. If the capacitor voltage plus the manner of the embodiment of FIG. 3 describe. Voltage of the control signal above the minimum voltage In F i g. 1 shows an output transistor 1 which goes beyond, the output transistor is fully connected to an emitter electrode 2, which is connected to the output switches, and the output is connected to the voltage of 15, and a collector electrode 6 of one Source set. However, if the parasitic capacitance comprises transistor 5, the source electrode 7 If charge flows out of the capacitor, then the transistor 5 with earth and the gate electrode 8 are sufficient the combined voltage is not off, the tran- is connected to the input. At other Aussistor to fully switch on as desired. In this guide the emitter electrode 7 can with In the event the output voltage may be less than 20 connected to a certain voltage level Supply voltage. to be The collector electrode 3 of the transistor 1

When the charge drains from the capacitor, it is connected to the operating voltage source - V , the source can momentarily be connected to earth -Electrode 10 and one equip. If the output is connected to a capacitive loading 25 gate electrode 11, which is connected to - V. The load is connected while the capacitor emitter electrode 12 is connected to the gate electrode 4 of the again and before the source span transistor 1 is connected. Another transistor 13 reaches the L value voltage, the output does not include a collector electrode 14, which changes noticeably with the. Without a capacitive load, Gatt electrode 4 is connected to the emitter electrode, the output can be two threshold values more positive 30 15, which is connected to earth and the Gatt electrode. For one and the other type of charge 16 connected to the input. The input, the output change is not essential, and the signal can be either an L or O signal, maximum negative voltage can be quickly restored. The capacitor C is connected to the signal source 17 and can be established. the gate electrode 4 of the output transistor 1

Although only MOS devices with negative 35 bound. The gate electrode 4 is also used to describe the off-voltages, and devices (emitter electrode 12) of the transistor 9 that work with positive voltages can exactly be connected. The capacitor C ₁ , shown in phantom, can be used well without departing from the scope of the invention consisting of the parasitic capacitance of the device. A negative voltage level was during operation and if the input signal has the value L as "!," - state and has a zero level as 40 or 0, transistors 5 and 13 become conductive, non-conductive state ("O" state). A change is switched and the output and gate electrodes are however possible without departing from the scope of the invention of the transistor 1 being connected to a level. which approximates the earth potential. It is a

Another aim of the invention is to provide a low-voltage drop MOS transistor in transistors 5 and 13, which has a capacitor and a 45, and as a result, the output control signal can be used to change the output voltage and gate voltages slightly from a zero level to increase the current of the driver circuit without deviating. The transistor 9 remains to increase during this supply voltage, which is also switched on for the period mentioned because its gate voltage output is more than a threshold value more negative than the source constant for relatively long periods of time and the one relatively constant voltage that is on the voltage of the 4th voltage output and a proportionately located
has little spread. When the input signal becomes a 0 or X signal,

This object is achieved by the invention in that the transistors 5 and 13 become non-conductive, the gate electrode of this one output transistor is also switched, and the gate electrode 4 is connected through one side of a capacitor, the 55 low resistance of which of the transistor 9 is connected to - V unite the side with the one attached to another electrode. The signal from the source 17 becomes "0" and th voltage, e.g. B. via another transistor, connects the capacitor C to ground potential. Which is coupled and at about their height, capacitor C and capacitor C ₁ charge while the other side of the capacitor charges a signal to the voltage -V - \ - Vt , which is received at the emitter from a signal voltage device, such as electrode 12 of transistor 9 appears. As soon as that the capacitor has been charged according to the difference capacitor C, the source chip of both voltages is charged, and after voltage of the transistor 9 is equal to a threshold value, the charging of the capacitor has taken place, which is greater than the voltage of the gate electrode, and the signal over a voltage has the output transistor is switched nonconductive, voltage to the voltage at the further electrode 65. After the capacitor is charged, that of the transistor of said stage is increased. Signal Φ from source 17 has the value L or 0. On

Further features and advantages of the invention- part of the charge on the capacitor C flows into the

result from the description below of capacitor C ₁ , that is, it only receives a partial

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voltage. The exact amount of the charge depends on the actual _C1 compared to C small, C ₁ to the ratio of the sizes of C ₁ and C as well as on the voltage of the signal queue plus its originally size of the signal Φ. If C ₁ compared to C small borrowed charge - V - \ - V _t charged. As a result, the effect on circuit operation is minimal, hence the relationship: .. ·. ·. ■
ie it only takes a small charge to reach 5 _ Φ
to increase the voltage across C ₁ to ground potential. ~ C ~ '
However, if C _{1 is} not small compared to C then *
it may be that the value of Φ and C is set and since C _{1 is} small, a relatively large one may have to be, so that after the charge has been distributed, a desired initial level io can be achieved _{with a lower charge between C and C 1} ,
is produced. However, when C _{1 is} relatively large, it is more

As indicated, the voltage increase on the load is required to bring C ₁ to a desired one

Gatt electrode 4 to bring the level proportional to the capacitance value. The voltage V0 can therefore

of the capacitor C, the capacitance of C ₁ and the being unsuitable to have a sufficient charge for C ₁ and C

Value of the signal ??. When creating a voltage boost 15, the gate voltage to the desired

from ZlF to gate 4 is desired, the Kon value must be increased by -2V _t ; that is, since the Gatt elec-

capacitor C in accordance with the following trode 47 carries the voltage - V + Vt before the

Equation to be chosen:. Signal Φ is true, the voltage of the emitter electrode 45 can only rise to -V + 2Vt. Therefore must

Q α γ ^{20 um} ^ ^e emitter electrode 45 towards the value of - V

C = 1 (1) bring the increase in voltage to the gate

VΦ - Δ V electrode must be at least -2V _t .

If Φ is true, then C _{1 can take} charge of C

where AV is the increase in the voltage at C ₁ , and thereby bring about the necessary voltage increase in the redistribution of the charges on the 25 increase at gate 47 anyway. In certain capacitors C and C ₁ , when the signal Φ is used, an output can even be set and νΦ represents the L value of the signal Φ. Voltage increase by less than one step off If Δ V equals 2 V _t , the output transistor will be sufficient, and the ratio of the capacitances C switched to - V. Without the capacitor C and that and C ₁ to each other is less critical.
Signal Φ would be the output signal - V + 2 V ₁ . 3 ° The value of the capacitor C, which is necessary

The control signal must be to L after the will to achieve the required increase by

Capacitor C is charged to the voltage that determines the following equation:
occurs at the electrode 12. On the other hand increases the

Voltage increase at gate 4 the output voltage q _ 2C ₁ -Vt

not. In other words, if the control signal before 35 γφ - 2Vt
the specified time is applied, the output

set to - V plus a threshold, where ΥΦ is the voltage of the signal source if

with a faster response, but which the signal has the value L. When the capacitor C

Desired increase in voltage does not occur. or C ₁ discharges sufficiently to keep the output

In Fig. 2 is a second embodiment of a 40 voltage change, the signal source is not true, shown driver circuit that uses a control signal Φ and a recharge of the capacitors on it and has an output transistor 40, whose previous voltage level is possible again.
Emitter electrode 41 to the output and via In F i g. 3, the invention is shown in one embodiment with a transistor 42 connected to ground and its shape shown with low gain. Here the gate electrode 43 with the collector electrode of a 45 driver has an output stage which consists of the tran transistor 44 and the emitter electrode 45 of a transistor 20 and 23. The output transistor 20 is connected to transistor 46. The capacitor C is connected with its collector electrode 21 to the operating with the gate electrode 47 of the transistor 46 and to voltage - F, and its emitter electrode is connected to a clock signal source 50. The gate electrode 22 is connected to the output and the collector electrode 25 trode 47 is also connected to the emitter electrode 48 of a 5 ° of the transistor 23. The transistor 23 has transistor 49 connected. an emitter electrode 24 connected to ground, and a

In operation, the signal source 50 connects a side gate electrode 26 which is connected to the output of one of the capacitor C to ground. The capacitor C is connected to the first inverter stage. The first inverter and capacitor C ₁ charge to the voltage stage comprises transistors 34 and 28. The input that appears on electrode 48, ie, on the 55 signal from polyphase gate 31, transistor voltage -V + V _t . The transistor 49 was reversed conductive 28 of the first inverter stage,
switched because the voltage at its gate electrode The transistor 34 of the first inverter is between a threshold value was more negative than the voltage of the operating voltage source - V and the electrode 27 at its emitter electrode. Then the signal Φ of the transistor 28 is switched on. Faithful to the Gatt electrode 33. The charge on the capacitor C is shared 60 of the transistor 34 with an input signal ver in the ratio of their capacitance values to the condensers, which is designated as Φ ₂ . The electrode 29 capacitors C and C ₁ on. Assuming that the capacitance of the transistor 28 is connected to ground, and the fact C ₁ is small compared to C, the voltage gate electrode 30 of the transistor 28 is increased with that at gate 47 by the signal voltage ΥΦ. The output of the gate stage 31 is connected, which a binary transistor 46 is fully conductive, and the emitter 65 signal L or 0 supplies. In the embodiment according to electrode 45, the operating voltage - V a F i g. 3 have set the signals Φ _χ and Φ ₂ by at least. The output of transistor 40 then has a threshold value more negative than -V. As the value -V + Vt . explained below, this enables charging

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of the capacitor C to the operating voltage - V. Then Φ ₁ becomes »0« and Φ ₂ »L«. If the If the signals only had the value - V would be true to circuit 37, transistor 28 will not capacitor charge to - V + Vt . conductive and the transistors 18 and 23 are conductive. In this embodiment, the output is switched on. The output signal becomes "0" and the Kon gate stage 31 is set to a negative value when 5 capacitor C is discharged through the transistor 18, the input signal Φ _{1 is} true. It is set back to the assumption that the circuit 37 is not true, value 0, if the circuit 37 remains true, the transistor 28 is switched on, and the transistor 28 is switched on and the input signal Φ _{2 has} the value L. If transistors 18 and 23 remain nonconductive, i.e. circuit 37 is true to the same time as transistor 35 is also switched on, Φ ₂ , Φ _{1 has} the value 0, and the gate output is io because Φ _{2 is} "L" , and the voltage - V is connected to a ground. The input of the gate of the side of the capacitor through transistor 35 verTransistor 38 provides the OR function of the signals tied. If C ₁ is small compared to C or if Φ ₁ and Φ ₂ represent. C ₁ does not have sufficient capacitance to generate a span To prevent emitter electrode 32 of the 15 threshold value, the output signal transistor 39 is connected. The transistor 39 and the on - fan lifted. As I said, if C ₁ in the ratio transistor 18 form a second inverter stage, which is larger than C , more charge flows from C to C ₁ , input signal to transistor 28 a second time and the voltage increase on the gate is less, vice versa. A signal that matches the original logic die in FIG. The curves shown in Fig. 4 represent the operating state of the polyphase gate output (input ao of the circuit discussed above. When to the transistor 28), occurs at the collector electrode Φ ₁ »Ζ.« Is (curve a) or has a negative value is of the transistor 18 on. the output of the voltage amplifier stage "0" The other side of the capacitor C is connected to one (curve c), and the output signal of the polyphase voltage amplifier stage, which from the gate 31 is "L" (curve d). In addition, it consists of transistors 35 and 36. The transistor 36 35 output signal of the first inverter "0" (curve e). The is controlled by the input signal Φ ₁ and the second inverter and the driver outputs lead the transistor 35 by an input signal Φ ₂ . If Φ _χ signal »L« (are conductive) at a potential that is »0«, the output signal of the amplifier stage is »L«. is less than - V (curves / and g). Subsequently, although the gate 33 of the transistor 34 is shown to be true to the if Φ ₂ (curve b), the voltage input signal Φ _{2 is} shown, it could be 3 ° true to the amplifier stage and, if assumed, also be connected to the supply voltage. One will be that circuit 37 is not faithful if such a connection would remain faithful to additional power. The first inverter need. The gate of transistor 39 is output with Φ _λ is not true, and the output signal is bound, so that capacitor C can be set to - V on the second inverter stage is proportional to the loading when Φ _{1 is} "Ζ,". It could also be directly more negative (point 52 of the curve /) and connected to the supply line, but the capacitor would then only be charged to -V + Vt, depending on the ratio of the capacitances. and C ₁ raised. For this particular embodiment, the parasitic capacitance C ₁ is dashed between form, C ₁ has a capacitance value such that gate 19 and earth are shown. Voltage at gate 19 (AV, curve /) by two thresholds. In operation, if Φ _{χ is} »L«, the output signal is 40 lenwerte appears. The Treiberausgangsder first inverter stage "0", and the transistor 18 of the voltage (curve g) is thus in - V increases. Without a second inverter stage, it is switched to be non-conductive. The increase would make the output voltage -V + Vt transistor 36 conductive, and be one side.

of the capacitor is connected to earth potential. The other side of the capacitor is recharged via the capacitor when the charge of the con-transistor 39 is connected to - V and thus the capacitors C and C _{1 have} flowed off and Φ ₁ »L« is charged, the capacitor to - V. If the full charge is present, the output voltage changes in this case, the transistor 39 will only be switched off by a small amount, as shown in the curve, unless there is a leakage current from C and C ₁ , arrow 51 shown is. If the load is not capacitive which also on - are charged V occurs. 50, the output becomes - V + V _t .

1 sheet of drawings

Claims (4)

ι 2 responds to the binary character L of the input signal,. to connect one side of the capacitor to the potential corresponding to the claims: binary sign 0 and to discharge the capacitor, whereby 1. Binary operating clock signal-controlled switching 5 the gate electrode (4) of the MOS transistor stage (1) Arrangement in MOS circuit technology with a Po pair corresponding to the binary sign 0 Output transistors connected in series, potential connected and the voltage at the output is changed with a common output connected in parallel. and with a third transistor that acts as a resistor with one of the output transistors in series io is switched, thereby marked net that the Gatt electrode (4,47,19) has this one ^:
Output transistor (1, 46, 20) with one side of a
Capacitor (C) is connected, one side of which with the 15 applied to a further electrode. The invention relates to a binary operating clock voltage (-V), for example, via a further transignal-controlled switching arrangement in the MOS switching transistor (9, 49, 39) and via its technology with a pair in series switched off-height, while the other side of the congang transistor with a common, parallel-connected capacitor has a signal (Φ, Φ _χ ) from a signal voltage output and with a third transistor, the voltage device (17, 50, 35, 36 ) receives, so that 20 is connected as a resistor with one of the output transistors in the capacitor according to the difference in series. both voltages is charged and, after such arrangements are known, so describes the charging of the capacitor has taken place, e.g. U.S. Patent 3,250,917 is the principal one the signal has a voltage that allows the arrangement of two transistors in series in the MOS- ' output voltage (2, 45, 22) to voltage (—V) 25 Circuit technology. In principle, the series at the other electrode (3, 21) of the transistor circuit of two MOS field effect transistors known, (1, 46, 20) of said level increased. one of which is connected as a resistor (see the USA. 2. Switching arrangement according to claim 1, characterized in patent 3 215 861, the Siemens magazine from characterized in that the collector (10) and the July 1966, pp. 570 and 571 and the French patent Gatt electrode (11) of the further transistor (9, 49) 30 font 1 462 815). with the first potential (- V) and its emitter are also known such circuits in which Electrode (12) connected to the capacitor, two transistors are controlled together is to have a relatively low impedance (cf. "Electronics" of November 30, 1964, p. 58). between the said one side of the capacitor In certain fields of application that require and to introduce the first potential ( −V) while using an arrangement according to the application, briefly the capacitor (C) is based on the difference called MOS drivers, require a ratio- charges between said potentials, and moderately constant output voltage by one to introduce a relatively high Im output transistor during a relatively long time Pedance between the said one side of the condensation periods must be maintained. The charge on sators (C) and the first potential (-K) after 4 ° the feedback capacitor and another the capacitor (C) on the difference between the capacitor had previously had the tendency to reduce the output has been charged to the two potentials. to let the voltage drop. To the capacity again 3. Switching arrangement according to claim 1, which is connected to charging and the "feedback" effect from a source of input signals, it was necessary to have the output of its the binary characters L and 0, thereby generating 45 »/. Level to, for example, a "0" level to indicate that the second switch in series. MOS transistor (44) one with the source of input It is desirable to have one according to the application Gatt electrode connected to the output signals, one with an arrangement of an increased voltage and a current dem to achieve said output connected first electrode output without the.ZuIeitungsspannung and a further elec- trode feeling the binary sign 0 is increased and a relatively constant austrode having the Gatt electrode on the gear level during a relatively long time input signal responds in order to maintain the output elec- tricity. trode to the binary value 0 if the object of the invention is to provide a MOS driver Input signal L ' , and that further to provide a third one having an output which during and a fourth MOS transistor (40, 42) remains relatively constant in long periods of time. the clock circuit are provided, with the first (40) constant voltage output being of these MOS transistors reaches one with the said separated capacitor, which is placed between the Output connected gate electrode (43) and the gate electrode of the output transistor and the a second (42) of the push-pull transistors is connected to the control signal source. Initially the Source of input signals connected Gatt- 60 capacitor to a voltage level through a Having electrode. Switching device charged between the 4. Switching arrangement according to claim 2, which is switched on with a capacitor and a voltage level. a source of input signals, the parasitic or effective capacitance of the driver, which has the binary characters L and 0, thereby charging at the same time. Then it is indicated that a second MOS transistor 65 control signal is applied to the voltage on the (13) between the one side of the capacitor (C) gate electrode of an output transistor in the ratio and a potential is connected that corresponds to the binary nis to increase the charge on the capacitor, value corresponds to 0 and its gate electrode (16) to. If the parasitic capacitance is not small in comparison