DE1537193B2 - Method for the compressed storage of a binary video data sequence - Google Patents

Description

The invention relates to a method for the compressed storage of the binary video data sequence for a image scanned in the line raster in which at

2s of a sequence of the same bits a the scope and the The compressed word characterizing the polarity of this sequence is stored. Binary data sequences often point Redundancies on, and it is often desirable to reduce these redundancies, so the relevant Compress data sequence. In the case of a video stream from a television broadcast of an image such as this "Usually occurs in commercial television broadcasting, there is redundancy, but not as many as a video data sequence that arises when scanning a technical drawing, because the latter often has wide white areas. To compress such a data sequence one has the Video data is subjected to a so-called longitudinal compressive encryption. To this The purpose was to check the individual bits that arose during the scan for transitions, whereby a transition a change from a zero bit to a one bit or a change from a one bit to a zero bit. A counter counts the number of bits between two successive transitions. Instead of this sequence of identical bits is then coded for compression. The number and polarity of this sequence are stored.

This principle of linear compression, i.e. a compression according to the immediate Sequence of data is applied to binary in U.S. Patents 3,213,268 and 3,185,824 Data sequence that is tapped from a large number of multiplexed buttons and in the US-PS 32 89 169 to a binary data sequence that is to be stored in a core memory.

In the case of a binary video data sequence for an image scanned in the line raster, there are not only redundancies to be expected in the immediate succession of the individual data bits - i.e. in the temporal one Sequence of the successive, for example horizontal, scan lines, but also vertically to it. Pictures, especially technical drawings, show redundancies to the same extent on a statistical average horizontal direction as in the vertical direction.

Redundancies in the horizontal direction can, if this is the scan line direction, due to the known methods are compressed, but not those perpendicular to the scanning lines, so in the example

vertically, redundancies present.

The object of the invention is to design a method of the type mentioned in such a way that at The lowest possible circuit complexity, in particular with regard to the memory, one possible extensive compression can be achieved.

The invention is characterized in that the successive bits of the video data within the individual scanning lines in successive divisions, each comprising the same number of bits, are examined for transitions relevant department with all subsequent same of this line is stored as a horizontally compressed word in a first storage, and that this first storage is stored word-by-word and column-wise in relation to the scanning grid in a second storage, whereby similar successive words of a column section in one the information content and the Number of repetitions characterizing vertically-compressed word are stored. While in the known method r could only be compressed in the horizontal direction, according to the invention it is first compressed in the horizontal direction and in the course of the re-storage in the vertical direction, so that both horizontal and vertical redundancies are detected.

From US-PS 3192 315 a method is known that two-dimensionally - that is, in the scan line direction and vertical to it - is applicable to a video data sequence, but this known method is used not for compression, but for the image contrast by suppressing the high frequencies to belittle. This prior publication does not provide any suggestions for the inventive solution.

The first storage provided according to the invention is practically only an intermediate storage, and therefore it only requires a relatively small storage capacity in relation to the entire image content.

With reference to an embodiment is still shown that it is quite possible to perform the first p storage with a storage capacity that is smaller than required for the compressed contents of an image. The second storage can be a final storage if the finally compressed data is not to be transmitted and further processed immediately. But even in the case of long-term storage, a simple memory is sufficient for the second storage in relation to the one required in the known method, because the second storage only requires less storage capacity due to the double compression and for the same reason also a lower recording speed of the memory is required.

The first storage is expedient in that the first storage of all words - the detailed and the compressed - are appended in the same way connection bits that indicate the word character - detailed or compressed - and the sign of the compressed bits. The connection bits are of course not required for uncompressed words if the spatial or temporal arrangement of these words within the video data sequence is clearly expressed by their arrangement in the first storage or by an address register. The further processing makes it useful that the words of the first storage are all of the same length, and for their production it is easier to design them with the same length of information part, which is why connection bits are also carried along as blanks for the detailed words that are not compressed will.

A further development of the invention is characterized in that the information bits are horizontally compressed word the number of repeated divisions for which the relevant horizontally compressed Word stands, to be reproduced in binary form, and that for repetitions that exceed the maximum number that can be expressed with the information bits, a new word for the first memory is written.

The restoration should take place in columns. This is preferably done by adding the words first Stores corresponding to the beginning of a scan line form one column, the second words in each Memory line of the first storage form the second column and so on. Restored in these columns one after the other will.

This processing in accordance with the original lines or grid structure is not absolutely necessary to return spatially in the storages. However, such a spatial arrangement is recommended because of the clarity of the circuit within the memory. A corresponding further training the invention is characterized in that the first storage takes place in a spatial line structure, in which the words from the bits of a scanning line are written down in a line of memory that the Memory lines arranged one below the other in the same spatial order as the associated scanning lines and that the words of a memory line are in the spatial order of the associated departments are enrolled.

For the column-like re-storage, it may be necessary to recognize which words the belong to the beginning of a scanning line for the first time. An arrangement is recommended for such cases of the invention, which is characterized in that the connection bits of a word of the first storage also indicate whether the word concerned is at the beginning of a scan line or not. This information are possibly no longer needed in the second storage, and therefore the If necessary, allow the relevant bits to fail when restoring.

While with horizontal compression the compressed sequences could only have two different information contents, namely either positive or negative or one or zero and also only had to be specified how many one bits or zero bits are compressed or how many sections of such bits are compressed, the vertical compression on whole words that have a more complex information content. This can be taken into account in various ways by designing the words in the second storage . Preferably, because the circuitry is easy to carry out, this is done according to the invention by adding the same number of counting bits to the words of the first storage during the re-storing, which counting bits indicate how often a word of the first storage is expressed by the relevant word of the second storage . This can then e.g. B. can be done simply in such a way that the information

part of the words of the second storage is identical with the information part of the associated word of the first storage plus at least that Terminal bits that identify the sign and number of the compressed bits. You need with one in such a case only the words of the first storage are queried in sequence and identical in the second Transferring the storage and adding the counting bits at the same time. If the first Storage identities result, they are counted in the counting bits and stored in the second storage for the identical words of the first storage once the word with the enumerated counting bits. In interest It recommends a simple circuit of the memory for a subsequent decrypting readout that the second storage is retained while maintaining the spatial column structure of the first storage he follows.

The same number of digit positions of the counting bits can be found for all words of the second storage provide. However, this number must not be too large, otherwise the words of the second storage would be too long. It is true that only low numbers can be printed out with a few counting bits, but you can get by with it, if only a number of identical words from a column of the first during a cycle of restoring Storage is considered, which is represented by the count bits of a word of the second storage can be expressed in binary form.

The invention will now be explained in more detail with reference to the drawing. In the drawing shows

1 shows a circuit in an overview block diagram to carry out the inventive method,

F i g. 2 in the block diagram those parts from FIG. 1 which are involved in the two-dimensional compression are involved in a little more detail,

Fi g.3 a pulse diagram for FIG. 2,

F i g. 4 shows the parts of the horizontal data compression from FIG. 2 shown in more detail in the block diagram,

F i g. 5 shows the parts for vertical data compression from FIG. 2 shown in more detail in the block diagram,

F i g. 6 shows a preferred spatial arrangement of the individual words in a perspective illustration in various stores and

F i g. 7 in tabular form based on a data example that differ with vertical and horizontal compression resulting words.

F i g. 1 shows an image 1 to be transmitted or scanned, which is either arranged in a stationary manner or is moved in the direction of arrow 2 and scanned by a scanner 3. The signal voltage at the output of the scanner 3 has either a high or a low level, depending on whether information is present or not. This output signal, which contains the video data, is present on line 4 and is labeled A. The video data reach a two-dimensional data compressor 5, in which they are checked horizontally and vertically for redundancies. The redundancies that existed in the horizontal or vertical direction in the image 1 are compressed in the data compressor, and the compressed data are output on the output line 6 and can either be transmitted via the line 8 or fed to a storage facility via the line 7.

2 shows the two-dimensional data compressor 5 in somewhat greater detail in the block diagram. The video data A first arrive in a horizontal compressor 100, specifically in this compressor 100 in a longitudinal encryptor 9, in which the data are compressed in the horizontal direction according to known methods.

In the downstream ßl buffer 10, the data from the longitudinal encryptor 9 are stored so that they can be queried for vertical redundancies of the scanned original image 1. The original image 1 therefore only needs to be scanned in one direction for the two-dimensional data compression provided here. The reading of the ßl buffer 10 takes place in sections corresponding to the sections of adjacent horizontal lines, as they were in the original Figure 1. If one reads out the ßl buffer 10 and disregards the physical position of the data, this corresponds to reading out a pseudo-image of the original image 1, which has a pseudo-character because the horizontal details are removed and the arrangement of the data in the ßl buffer 10 is controlled from the outside by a control unit 12 with the interposition of a B 1 memory address register 11. The operating frequency of the control device 12 is denoted by / i.

The horizontally compressed data are read out from the ßl register and enter a vertical compressor 200. The data is extracted from the ßl register 11 in divisions of 10 bits each read out. Each division comprises an 8-bit word and various connection bits, which are described in more detail below explained. The departments exist if there are no redundancies in the original image were, from detailed words and if there are horizontal redundancies in the original picture 1 were, from compressed words.

The data reach the register 13 in columns and in sections and from there to the comparator 14, in which successive words from the horizontal compressor are compared for redundancies. After this comparison, words that are detailed when there is no vertical redundancy, but are compressed when there is vertical redundancy, enter the vertical compression register 15. Further connection bits are used to indicate the number of horizontal picture lines over which word redundancy extends . A control unit 16 controls the vertical compression with an operating frequency k which is smaller than / i.

The video data A are thus compressed in the horizontal compressor 100 in the horizontal direction. The horizontally compressed data then pass into the vertical compressor 200, with mutually corresponding divisions of adjacent scan lines of the original image 1 being compared with one another in order to determine whether or not there are vertical redundancies, that is to say redundancies in the vertical direction. On the output line 6 of the vertical compression register 15 there are then two-dimensionally compressed data which can either be transmitted over the line 8 or stored over the line 7 in a B 2 buffer. The storage cycle of the B 2 buffer 18 can be significantly slower than that of the B 1 buffer 10 (cf. k < / i). The β2 buffer 18 can, for example, be a memory with a magnetizable storage tape or a magnetizable storage disk. Such buffers do not save at a very high speed. On the other hand, the ratio between production costs and storage capacity is very favorable. The ßl buffer 10 must

on the other hand, have a high storage speed. However, it does not require a very large storage capacity, so that this BI buffer 10 does not require very high costs either. In practice the storage capacity will be of the ßl buffer 10 by the characteristic Data of the image 1 is determined, in particular by the optimal word length of the longitudinal encryption.

In Fig. 3, under L, a signal for the rudder control is indicated, which is at a high level when scanning is taking place. A denotes the video data which occur at the output of the scanner 3 and which have already been mentioned in the text relating to FIG. 1 mentioned. The high level is also known as the white level and corresponds to a binary 1; the low level or black level, on the other hand, is a binary 0. B denotes a signal for line control, the beginning of which indicates the start of scanning of a specific line. Clock pulses of a continuously operated clock generator are denoted by C. Those clock pulses are designated by D which coincide with the line control pulses B and are also called spacing pulses in the following. E transition signals are designated, which are sampled by the clock pulses and display the transitions from 1 to 0 and 0 to 1 in the video stream A. Under X , the video data from line A are given again in digital notation.

On the basis of Fi g. Figures 4a and 4b will now detail a preferred embodiment of the horizontal compressor 100 from FIG. 2 explained.

In this exemplary embodiment, comparison means are provided on the input side, the neighboring bits of the Compare input data and generate an output signal if consecutive Bits are different. The comparator means includes a generator for generating a transition signal and a bistable means that according to this transition signal is unswitched.

Selection means are also provided which examine successive compartments of the data bits fed in, each of these compartments comprising an arbitrary minimum bit length. In the exemplary embodiment shown, a shift register 102 is provided as the selection means. In addition, control means are provided to control the reading out and switching back of the selection means. These control means include an 8-stage counter 108 with an associated decoder 128 which counts the minimum number of bits in a division. In addition, gate means are provided which serve to separate out the content of the selection means.

The horizontal compressor counts the number of divisions of the input data that are identical. In the illustrated embodiment, a counter 106 is provided for this purpose. Decoding means and gates are also provided for this counter.

Finally, the Bi buffer is provided in which the words are stored in accordance with a pseudo-image of the original image 1. This storage is formed from the content of the selection means and the horizontal compression means, in this case the counter 106 . The content of the selection means is a detailed word if the data fed in is in transition within the minimum length of a section. The content of the horizontal compression means, on the other hand, consists of compressed words. In addition, a connection bit circuit is provided which generates various bits which are used to describe the words fed into the storage means or to identify them in more detail. These connecting bits identify whether or not a word is at the beginning of a horizontal line, whether the word is a detailed word or a compressed word, and whether or not the compressed word contains ones or zeros. These connection bit circuits also generate control signals which are fed into a ßl memory address register (cf. reference number 11 from FIG. 2) and control the feeding and reading of the data for the memory means.

In the exemplary embodiment shown, the video data A reach the horizontal compressor 100, in which horizontal redundancies from the original image 1 are reduced. Means are provided in the horizontal compressor to convert the transition signals E from FIG. 3 to generate. There is also a shift register 102 for the uncompressed data according to line X of FIG. 3 provided. When a transition occurs within a data division, a detailed word containing the bits actually sampled is fed into a data register 104 before entering the β1 buffer. In the exemplary embodiment shown, the minimum number of bits, that is to say the smallest division over which a comparison is made, is 8 bits. This number is arbitrary. It can be smaller or larger, depending on how many redundancies are present in the original image 1. If the neighboring bits of a horizontal scan do not vary, ie if there are either only white or only black bits in a division comprising at least 8 bits, then the number of 8-bit words of the same type is counted in the counter 106, which is a 27 counter . The size of the counter 106 is variable; it can be determined in accordance with any redundancies that may exist.

An 8-stage register is designated by 108, which via sampling clock pulses D from FIG. 3, i.e. it is switched forward during a line division. The size of the register 108 is determined by the size of the detailed word, which here can comprise 8 bits. The 8-stage register 108 counts 8 bits and then generates a pulse. This pulse is counted in counter 106, which in this way counts the number of identical detailed words. In the present case, the number of those identical 8-bit words that can be counted in the counter 106 is 255, corresponding to 2040 bits in the video data. In other words, a compressed word is formed which indicates the number of similar data bits and also indicates whether these bits are ones or zeros.

This compressed word reaches the B 1 buffer 10 from the counter 106 via the data register 104.

In addition to the 8-bit detailed or compressed word, 3 bits are appended to each word in the data register 104. These 3 bits in data register 104 indicate:

a) the beginning of a line scan (bit position 110),

b) whether a word is a compressed word (1) or a detailed word (0) (bit position 112),

c) whether white (1) or black (0) is contained in the compressed word (bit position 114).

It is not necessary to use a bit to indicate the beginning of a scan line if the bits are placed in the 51 buffer 10 so that the beginning of the line results from the position of the associated word. The storage in the ßl buffer 10 takes place here in this way. that they are based on a pseudo-image of the

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original picture 1 is placed. The scanning of this pseudo-image then corresponds to a second scanning of the original image 1, and the vertical redundancies of the document or original image 1 reduced. This is done in such a way that corresponding divisions of horizontal lines with each other can be compared and the vertical compression is derived from it. It is therefore according to the invention only one scan of the original image 1 required.

The function of the horizontal compression will now be described in a little more detail. The video data A pass from the scanner 3 into a differentiator 116 and from there to one input of an OR circuit 118. The video data A also pass to an inverter 120 and from there to another differentiator 122 and to the second input of the aforementioned OR circuit 118. The output of OR circuit 118 is the transition signal E from FIG. 3, which is the forward switching signal of a transition toggle circuit 7 * 1 . The flip-flop 7 "I produces a positive output when there is a transition in the video data and no output when there is no transition in the video data.

The clock pulses C are generated by a continuously running clock generator 124 and are rounded off with the line control signals B from the scanner 3 in the AND circuit 126. The output of this AND circuit 126 are the sampling clock pulses D. The sampling clock pulses D get into an AND circuit 127, together with the video signals A, so that at the output of the AND circuit 127 uncompressed data according to line X from FIG the 8-position shift register 102 are fed. The 8-stage register 108 is switched forward via the sampling clock pulses D. The 8-stage register 108 counts 8 bits and an indication is triggered in the decoder 128 when 8 bits are counted. The counter 106 counts the 8-bit divisions (i.e. the detailed words) which are equal among themselves. Each time the decoder 128 generates an output signal, the count of the counter 106 advances one unit.

If z. B. only black level is scanned, then zero bits get into the shift register 102. If, however, white level is scanned, one bits get into the shift register 102. If the original image 1 contains details in the area just scanned, so there is a transition within a division of 8 bits results, then both one bits and zero bits are present in the shift register 102.

In this assumed case, the output of the flip-flop Ti is also positive, and it is thus indicated that a transition in the video data A has taken place. This positive signal goes to an AND gate 130. When the shift register 108 is decrypted, there is an output on the line 132 , which goes to the AND circuit 130 and there triggers an output for the delay 134 , which is sent to the AND Gate combination 136 arrives. This forwards the 8-bit detailed word from the shift register 102 and the OR combination 173 . The delay of the delay 134 is small and allows the last, that is to say the 8th bit, which is counted in the shift register 108 , to be processed in the decoder 128 before the content of the shift register 102 is read out. The size of this delay is a function of the timing of the clock pulses C.

If there are greater horizontal redundancies over a specific horizontal line, identical bits (that is to say either ones or zeros) get into the shift register 102. In such a case, there is no output of the flip-flop 7 * 1. Since there is no output of the flip-flop T1, the AND gates 136 do not separate out the content of the shift register 102 either. The 8-level register 108 continues to count up to 8 bits. As soon as it has reached this count, there is a preparatory input signal for the AND gate 138. Since the flip-flop Ti has no output - meaning no positive output - an output signal is then produced at the AND gate 138 , which is fed into the counter 106. Whenever the decoder 128 generates an output signal based on the count of the 8-stage register 108 , a pulse is passed into the counter 106 with the trigger circuit Ti in this position. The counter 106 therefore counts the 8-bit compartments in which no transition takes place . if

until 2040 bits no transition has taken place, the content of the counter 106 reaches the data register 104 via the gates 140 or the OR combination 173. To open the gates 140 , the output of the counter 106 reaches the decoder 142, which, as soon as the counter 106 has reached the counter position of 255, an output signal is generated which is sent to an OR circuit 144 . The counter 106 acts on an OR circuit 146, the output of which is connected to another input of the OR circuit 144 . The flip-flop Ti , when switched forward, is switched back by each output of the decoder 128 via line 148 and delay element 150. The 8-stage register 108 is output each time a full 8-bit count is reached of the AND circuit 138 or via the line 152 and with the interposition of the OR circuit 137 switched back to zero. The 8-step register 108 is switched back with the sampling clock pulse D.

Each 8-bit compressed comprehensive or detailed word that gets into the data register 104 are appended 104 three special bits in the data register, the significance was already indicated above.

Circuit 154 generates a 1-bit at the beginning of a scan line, among other functions. For this purpose, the flip-flop 72 is supplied with the line control pulses B at its forward switching input. If the flip-flop 7 * 2 is switched forward, a positive output is produced, which is rounded off in an AND circuit 156 with the sampling clock pulses £>. The output of the AND circuit 156 reaches the first position 110 of the register 104 via the line 158 and generates a 1-bit there when a new scanning line is to begin.

The second stage 112 of the register 104 is connected via the line 160 to the output of the AND circuit 138 , so that a 1-bit is generated in the stage 112 if it is a compressed word, on the other hand an O-bit is generated if it is a detailed word. The output of AND circuit 138 is rounded in AND circuit 162 with the video data on line 134. If this video data A has a high level or white level, corresponding to a “1”, then such a 1-bit is written into the third position 114 of the data register 104 . If, on the other hand, the video data A is at a low level, then no "1" reaches the register stage 114, so that it remains at zero.

It is not necessary to provide a bit to identify the beginning of a scanning line if the bits are fed into the β1 buffer 10 in such a way that the beginning of the line can be seen from their position. However, it is important that the words which are fed into the buffer register B 1 are arranged so that they represent a pseudo-picture of the original picture 1. In such a case, the content of the B 1 buffer 10 can be read out in the sense of a second scan of the image 1, and the vertical redundancies can be compressed in the process.

The corresponding memory arrangement in B 1 buffer 10 is shown below in FIG. 4 specified. The first word (a detailed word or a compressed word) of a scan line is fed into the first leftmost buffer line. The next word of the same scan line is fed into the same buffer line to the right of the first word. In this way the words in the first scan line are arranged side by side in the first buffer line. The first word of the second horizontal scan line is in the second buffer line below the first word of the first horizontal . Scanning line arranged. The second word of the second ' horizontal scanning line is to the right of the first word in the second buffer line below the corresponding word of the first horizontal scanning line and so on. The words that are written in this way in the B 1 buffer register are read out by corresponding Parts of adjacent scanning lines are compared for vertical redundancies.

The circuit 154, which has already been mentioned, generates various control signals for the address register 166. This circuit contains AND circuits 168 and 170 as well as an inverter 172. The side control signals L are fed into this circuit combination and signals / and / are derived therefrom, where / the negative to / is. The signal / indicates the beginning of a page and, via the flip-flop 7 * 2, selects the bit that is fed into bit position 110 at the beginning of the page. Either signal / or signal J is high when the start switch is closed. The signal / switches the address register 166 to a start position corresponding to a new page. The signal / indicates the end of the original image 1 and switches the address register 166 and is contained in the data register word as the 12th bit, although this is not shown in the schematic. The signal / reaches the OR circuit 174, which is also acted upon by the sampling clock pulses D delayed in the delay 176. This delay is necessary because the OR circuit 174 is used to switch back the flip-flop T2 . The delay of the delay circuit 176 is just large enough that the flip-flop T2 can remain in its forward-switched state for a sufficiently long time.

As shown in the drawing, the signals /, /, G, H and K get into the address register 166. The signal G is the output signal of the OR circuit 144, which opens the gates 140 when the contents of the counter 106 are in the OR -Combination 173 or in the data register 104 should arrive. The signal H opens the AND gate combination 136 when the bits of the detailed word from the shift register 102 are to get into the data register 104 . The signal K is the output signal of the UN D circuit 156. It should be pointed out that a new line is always started with the signals / and K.

The descrambler 178 is a certain number of stored scan lines and triggers the transfer of the content of the oil buffer 10 into an output register 202 (referred to in Figure 5), and indeed during a switching cycle of the B 1 buffer 10. In the illustrated and here In the example discussed, divisions assigned to one another of 7 adjacent horizontal scanning lines are compared with one another if a

ίο Signal M is present at the output of decoder 178 . How this is done in detail will now be described below.

The already mentioned output register 202 temporarily stores the content of the B 1 buffer 10. the

'5 words will be transferred word by word from the SSL buffer 10 to the output register 202, and such that the mutually corresponding sections of adjacent horizontal scan lines are associated with the words, sequentially reach the output register 202nd This type of reading out of the B 1 buffer 10 corresponds to a vertical scan of the original image 1. However, this vertical scan attacks an imaginary image, namely that in the β1 buffer 10, which is already compressed in the horizontal direction.

With 208 a data collector is referred to, which temporarily stores the words in the order in which they come from the output register 202. In the exemplary embodiment shown, these two registers 202 and 208 each store a single word at a time. But they can also be equipped with a higher storage capacity. Circuits are provided which generate a key pulse each time a word has been read into the output register 202 from the β1 buffer 10.

The words which are present in the output register 202 and in the data collector 208 are compared with one another in a comparator 210. This comparison is triggered by the aforementioned test pulse (TST). The comparator 210 generates an output signal if and only if the two words compared are identical.

A counting register is designated by 222, which counts the successive identities which are determined in the comparator 210 . For this purpose, the output of the comparator 210 is connected to the counting register 222 .

Control means are also provided which separate out the contents of the output register 202 of the comparator 210 and of the counting register 222 . These control means have circuits which respond to the output of the comparator 210 ; they also have special circuits for the output register 202, the data collector 208 and the comparator 210 . With 224 a decryptor is referred to, which decrypts the count of the counting register 222.

Designated at 204 is a vertical compression register which temporarily stores the output of the data collector and that of the counting register 222.

The desired double-compressed data are the outputs combined in this way.

These twice compressed data can either be transmitted immediately or they can be stored in the B 2 buffer 18.
As already noted, the memory content of the B 1 buffer 10 is arranged in the manner of a pseudo-image of the originally scanned image 1. Because of this particular arrangement it is possible to take this picture

to search the β 1 memory for vertical redundancies of the original image 1. The vertical compressor 200, shown in detail in FIG. 5 compares corresponding divisions of adjacent horizontal scan lines for redundancies. As with the horizontal compressor 100, longitudinal encryption is also used here. If thereafter corresponding divisions of adjacent horizontal lines are not the same, detailed words go directly into the vertical compression register 204 as 10-bit words. Only the information content of the words is compared. The bits which indicate the beginning of the line (corresponding to bit position 110 in register 104) are not read out of the β 1 buffer 10. The control units 12 and 16 from FIG. 2 keep track of the individual words to be compared, so that it is not necessary to leave this bit from bit position 110 in the words to be compared. The output register 202 is therefore connected to the B 1 buffer 10 via 10 lines. If the twice compressed data is to be stored in the B 2 buffer 18, an extra bit is added to precisely locate the words. If, on the other hand, the doubly compressed data is to be transmitted immediately, a code word can instead be placed on the transmission line which indicates the beginning of a message.

If words corresponding to corresponding divisions of a horizontal scan line are equal, then the number of times this redundancy is repeated is counted. In such a case a compressed Word indicating the amount of this redundancy is fed into the vertical compression register 204. Additional 3-bit positions of the vertical compression register 204 are used to indicate the number of words that are identical in the vertical direction. In the illustrated embodiment, each other corresponding divisions of up to 7 adjacent scanning lines are compared with each other. the Count 7 is arbitrary here. It can be chosen larger or smaller, depending on the redundancies can be expected in the vertical direction.

In detail, the vertical compression is carried out as follows. The corresponding parts of adjacent horizontal lines are read out of the B \ buffer 10 and get word for word into the output register 202. These words each comprise 10 bits, the first bit, which indicates the beginning of the line, not being transmitted. The second word from the B 1 buffer 10 reaches the output register 202, while the first word from the B 1 buffer 10 already reaches the data collector 208 via the gate combination 206. Since no comparison has yet been made, there is also no output on comparator 210, and a positive signal is present at the output of inverter 212. This positive output signal of inverter 212 is rounded in AND circuit 214 with the test signal on line 216. The output of the AND circuit 214 is one input of an OR circuit 218, the output of which opens the gate combination 206 and the gate combination 220.

During this time, the word in data collector 208 is compared with the word in output register 202 by comparator 210. If the words are not identical, there is no output on comparator 210, thus there is a positive output on inverter 212. This, combined with the test signal on the line 216, samples the OR ^: circuit 218, the output of which, as already noted, causes the transfer of the first word from the B 1 buffer 10 as a detailed word to the vertical compression register 204.

If, on the other hand, there is agreement from the comparisons, then the number of times this is counted Match, namely an identical match, occurs. This count can be shown at the Embodiment record up to 7 comparisons.

ίο The associated counting register 222 is positive Applied to signals that occur at the output of the comparator 210 when an identity has been determined. If the counting register 222 has counted to 7, then the downstream decoder 224 generates a Output signal that arrives at the other input of the OR circuit 218 and via this OR circuit 218 the gate combination 226 scans, through which the counter position of the counter register 222 in the first three Bit positions 228, 230, 232 of the vertical compression register 204 reached. These three bit positions indicate how many words of corresponding divisions are in adjacent horizontal scanning lines in the The scope of the counting options of the counting register 227 are identical. If there is no identity, there is one positive pulse at the output of inverter 212, which triggers an output pulse OR circuit 218 and this output pulse causes the word in data collector 208 to be placed in the vertical compression register 204 reached. This output signal of the OR circuit 218 is also applied via the delay 234 . the count register 222 is returned and switches it back to zero. The delay of the delay 234 serves to ensure that the count of the counting register 222 can be read out beforehand.

The test signal on line 216, which triggers the comparator to compare neighboring words, is generated in circuit 236. The output signal of the decoder 178 from FIG. 4 is rounded off with a write signal for the B 1 buffer 10 in the AND circuit 238. The output of this AND circuit 238 is rounded off with a write signal for the B2 buffer 18 in the AND circuit 240 and, after it has been delayed by one clock cycle in the delay 242, appears as a test signal on the line 216. The output of AND circuit 238 is also applied to address register 166 of FIG. 4 to increment this address register 166 vertically in increments of up to 7 steps.

In FIG. 5, the data that has been compressed twice comes from the vertical compression register 204 as 13-bit words in the ß2 buffer 18. When shown In the exemplary embodiment, there is an output signal at the OR circuit 218, if either no comparison has taken place or a comparison sequence has ended.

This relevant output pulse of the OR circuit 218 also reaches the line 246, and the Delay 248, to the ß2 memory address register 250 and is used there as a write signal to the words from the vertical compression register 204 to the /? 2 buffer 18. The delay of the Delay 248 takes approximately 2 to 3 microseconds and allows the data to be read in before the Memory address register 250 is advanced.

It should be noted that the words in the S2 buffer 18 are compressed twice for the data of the Document or image 1 are, and are transmitted or decrypted by the B2 buffer 18 to restore the original image 1

len. If the data according to FIG. 5 are stored in a β2 buffer 18, then the storage cycle of this β2 buffer can be significantly smaller than the β1 buffer 10. Because of the slow storage sequence, the β2 buffer can be a disk or drum storage. The data compressed twice is smaller in size than the data compressed only once. The result is that the B 2 buffer 18 usually waits for data from the B 1 buffer 10, which is why the B 1 buffer 10 can be equipped with a very small storage capacity. All in all, the invention can be carried out with memories for the B 1 buffer and the B 2 buffer, which together result in lower costs than with uncompressed storage of the video data.

6 shows the arrangement of the words in the buffers 10 and 18. The horizontally encrypted data from the data register 104 arrive in the B 1 buffer 10 as they were placed in the data register 104. The in F i g. 6 stored words W1, W2, W3 ... JV60 are words which originate from a horizontal scanning line of the original image 1. They can be either detailed words or condensed words, depending on whether there were horizontal * redundancies or not. In this example a horizontal scan line consists of 60 words, although this number is of course variable.

The second line of the memory level of the β1 buffer 10 shown in FIG. 6 contains the words W61, W62 ... W120. This line contains words from the second horizontal scan line. The words are fed into the memory level until the level in question is filled. If this is the case, then the storage continues in the second level of the memory and so on. In all cases the first word of a horizontal scanning line is stored in the first word position of a memory line. This applies to the words Wi, W6i, W121, W 181, VV241 etc. The words W2, W% 2, W \ 22 etc. are the words of the relevant horizontal scanning line that follow the first words.

In order to recognize vertical redundancies, these words are read out vertically from the B 1 buffer. This is done in such a way that the word Wl is compared with the word W 61, with the word W 121, with the word W181,;) and so on. The corresponding sampling of the AI buffer 10 takes place in accordance with the arrows S1, S2, S3 shown. After all the words in the first word position of the horizontal lines have been scanned and compared, the second words are scanned , i.e. words W2, W 62, W122, etc. This vertical scanning process continues over all vertical columns of the β1 buffer 10.

The words sampled from the B 1 buffer in this way go to the vertical compressor 200 where they are compared. They are then either stored in the B2 buffer 18 or transferred. When stored, they are stored in the form of 13 bit words with the first 3 bits indicating the number of lines over which the words in question are identical, up to a maximum of 7. These words are then stored as words WY, VV "2, etc., which can be either detailed words or compressed words. W'2 is the second word indicating the redundancies of the first vertical column of the β1 buffer 10. The corresponding scan continues until the last word Wn of the first vertical scan of the ßl buffer 10. The encrypted words from the second vertical scan of the B 1 buffer 10 are denoted by W (n + 1), W (n + 2) etc.

The arrangement of the data in detail in the buffers can also differ from that in FIG. 6 can be made. It is only essential that the arrangement is made in such a way that the vertical redundancies can be obtained when reading out the β1 buffer 10, as described. Of course, the control units must be adapted to the selected memory location with regard to the addressing of the buffers. The size of the buffers, in particular the B 1 buffer 10, is largely determined by the type of the original image 1.

It should also be noted that the invention can be used to replace entire lines of words to compare with each other. Finally, the invention is also applicable to various Compare original documents with each other. In the latter case, an appended bit is added used to indicate the start of a new scan for a new document.

Data compression in two directions will now be explained again using data examples. F i g. 7a shows uncompressed data for this purpose. F i g. 7b from the data according to FIG. 7a resulting words stored in B 1 buffer 10 and FIG. 7c the words stored in the β2 memory 18, which in turn result therefrom.

In Figure 7a, bits are only in the first four horizontal scan lines indicated. This is only for graphic reasons, and it goes without saying that the scanning extends over far more lines as a rule. F i g. 7a also shows only a part of the bits recorded in each scan line.

In the exemplary embodiment described above, adjacent bit divisions are compared with one another, a division comprising at least 8 bits, corresponding to a detailed word, and a maximum of 2040 bits. These departments are labeled Fl, F2 ... Fn. If a transition occurs within a division of 8 bits, then those 8 bits are fed directly into data register 104 as a detailed word. If, on the other hand, there is redundancy for more than 8 bits, then horizontal compression takes place. The compressed word which is then written into the data register 104 indicates the size of the redundancy (up to 2040 bits in this exemplary embodiment).

As already in the text on FIG. 4, the uncompressed data of the first horizontal line enter the shift register 102. In this case, the first 8 bits of scanning line 1 receive at least one transition within the 8-bit division. Because of this transition, the trigger circuit Ti produces a positive output. This positive output signal reaches the AND gate 130. The 8-stage register 108 is switched forward by a sampling clock pulse D. The 8-stage register 108 counts the number of bits that are fed into the shift register 102 and as soon as the count has run up to 8, the decoder 128 gives a corresponding output signal, by means of which the AND gate 130 is opened. The output signal of the AND gate 130 is delayed in the delay 134 and opens the gate combination 136 as signal H. The same signal H switches the shift register 102 back after the entire

. 509 551/146

Content is outsourced. These first 8 bits of the first 8 scanning lines thus reach the data register 104.

Since this is the beginning of a horizontal scanning line, there is a positive signal on line 158, which reaches bit position 110 of data register 104 as a 1 bit. This positive signal on line 158 is generated by flip-flop T2, as has already been explained above.

The first 8 bits of the first horizontal scanning line are now available as a detailed word in the data register * ° 104. As a result, a zero bit is fed into bit position 112 of data register 104. Since a transition took place within division Fi , there is a negative output on flip-flop T1. As a result, AND gate 138 could not be opened and there was also no output on line 160 via which bit position 112 could have been switched to 1.

The bits of the division F1 together with the three connection bits in the bit positions 110, 112, 114 form the word IV1. The connection bits, which here occupy the first three digit positions of the word Wl, indicate here that it is the beginning of a new scanning line and that it is a detailed word. Since this is a detailed word, the third bit position 114 is not required and is therefore loaded with zero. The following words are denoted by W2, W3 ... Wn ... W2n etc. The first word in the data register 104 is now in the ΗΊ buffer 10. FIG. 7b shows the distribution of the words in the B 1 buffer 10. As can be seen, the word Wi is accommodated in the first word position of the first memory line.

The next 8 bits that go into shift register 102 are those of division F2 from FIG. 7a. These 8 bits go directly into the data register 104 because there is a transition within these 8 bits. the Terminal bits in bit positions 110, 112 indicate that this is not a start of a scan line and that it is a detailed word. Since it is a detailed word, it is also in the third position 114 is a zero.

The word resulting therefrom is fed into the second word position W2 of the first memory line of the B 1 buffer 10.

In the illustrated embodiment, the next 2040 bits of the first horizontal scan line are all "1". The division F3 is therefore 2040 bits long. These bits enter the shift register 102 one after the other. However, there is no positive output of the flip-flop T1 because there is no transition. The result is that the AND circuit 130 also generates an output signal and that the signal H does not appear and the gate combination 136 remains blocked.

The 8-level register 108 now counts cyclically to 8, and it is created at the output of the AND circuit 138 each time an output if no count of 8 has been reached. This output reaches counter 106 as a pulse, which is therefore incremented by one count every time the 8-stage counter counts 8 has reached. In this way, a count accumulates in the counter 106, the groups comprising the 8 bits of bits counts as long as there is no transition. In the present case, the counter 106 counts all the way through is up to 8 binary digits up to 255 and this corresponds to 8 · 255 = 2040 bits.

The output of the counter 106 is continuously decrypted, and when the counter reaches the counter position 2040, the decoder 142 generates an output pulse which is applied to the OR gate 144. The output G of the OR gate 144 then opens the gate combination 144 so that the content of the counter 106 can reach the data register 104. The counter 106 also acts on the OR circuit 146, which acts on another input of the OR circuit 144. Since 2040 bits are now identical, the gate combination 140 is opened after the decoder has reached the binary count 2 ° + 2 ¹ + ... + 2 ⁷ = 255. If, however, a transition takes place before the 2040 bits are enumerated, there is a positive output at the flip-flop T1, which samples an input of the OR circuit 146 and triggers an output pulse of the OR circuit 146, which in turn is via the OR circuit 144 the door combination 140 opens. As can be seen, the gate combination 140 is opened either when the decoder 142 has counted to the maximum count 255 or when a transition in the video data A occurs.

The flip-flop T1 is, if it is switched forward, always switched back when the Decoder 128 generates an output signal. This output signal is via line 148 and the Delay 150 passed to the down-switching input of the flip-flop T1. This delay is less than one bit period. It is necessary so that the toggle switch Tl on lines 133 and 139 a can emit complete bit signal.

As before, three connection bits are required. The first of these bits indicates that division F3 is the beginning of a line. As a result, there is a zero in bit position 110. The third division was compressed, as a result of which a one is fed into bit position 112. This one is generated in that, after the decipherer has reached the count 255, there is an output at the decipherer 128, to be precise at the same time as a signal on the line 139. These two signals are rounded in the AND circuit 138. The result is that there is a positive pulse on line 160, which is written into bit position 112 as a 1 bit.

In the present case, the compressed word indicates that there are consecutive ones. For this reason, a one must be fed into bit position 114. The positive signal on line 160 is rounded with the video signal A on line 164 in AND circuit 162, and this results in a positive signal on line 163, which is fed into bit position 114 as a 1-bit.

The word compressed in this way is now fed into the B 1 buffer 10 in the third word position IV3 of the first line.

In this way, the data of the first horizontal scanning line in the divisions Fl, F2 ... Fn are fed into the word positions IVl, W2 ... Wn. The scanning now begins with the second horizontal scanning line of image 1. FIG. 7a shows bits which occur, for example, in the second scanning line as video data. The departments are labeled F (n + 1), F (n + 2) ... F (2nj.

It should be noted that the first two compartments F (n + 1), F (n + 2) contain details because a transition takes place in the relevant compartments. Following these two sections, however, there are again 2040 one-bits without a transition. The bits of the first division F (n + 1) first pass into the shift register 102 in the same way

as stated above. Since these bits contain details, they go from there directly to data register 104. Since the first division is the beginning of a line, bit position 110 contains 1. The other two bit positions 112 and 114 , however, remain at zero.

Since the second division F (n + 2) also contains details, the bits from the shift register 102 also go directly to the data register 104. In this case, however, there is no 1 in the bit position 110 because the * ° division F (n + 2 ) is not at the beginning of the line. Since the bits are not redundant, there is a zero in bit position 112, and since it is consequently a detailed word, bit position 114 is not needed and also contains a zero.

The 2040 bits that now follow are all "1", they arrive one after the other in the shift register 102 and are shifted through there. Because of the redundancies present, however, there is no output at the flip-flop Π, and the counter 106 counts to 255. The decoder 128 counts to 8 and acts on the AND gate 138. After all 2040 bits have entered the shift register 102 , the decrypted counter setting of the counter 106 has an output at the OR circuit 144, whereby the gate combination 140 is opened so that the content of the counter 196 can reach the data register 104. In the present case, no 1 is required in bit position 110 because division F (n + 3) is not at the beginning of a scanning line. However, since this division is represented by a compressed word, a 1 gets into bit position 112, in the same way as already explained in connection with division F1. Since all bits are “1”, a 1 also gets into bit position 114, also in the same way as already explained in connection with section F3. This 11-bit compressed word then arrives as word W (n + 3) in the third word position of the second line of the β 1 buffer 10. The other words, corresponding to the divisions of the second horizontal scanning line, are then placed in the other word positions of the second Memory line of the Bi buffer 10 fed. After all the video data of the second scanning line have been stored in encrypted form in this way, scanning of the third line begins.

In the first division F (2n + 1) of the third line there is again a transition, so that the relevant bits get directly from the shift register 102 into the data register 104 . As before, bit position 110 is set to 1 to indicate the beginning of the line. The word in the data register 104 reaches the first word position of the third line of the B 1 buffer 10, to be precise as word W {2n + 1).

The second division F (2n + 2) of the third scan line contains no transition. There is therefore no output signal at the trigger circuit Ti when these bits reach the shift register 102. If this count is counted out in the 8-stage register 108, however, there is a switch-back signal for the flip-flop Ti . This switch-back signal switches the flip-flop Ti so that a positive output on the line 133 reaches the AND gate 130 and also the OR gate 146 . The output of the OR gate 146 then switches the gate combination 140 to the gate combination 140 as a signal G via the OR gate 144. Since there was no transition in division F (2n + 2) , there are two inputs to AND gate 138 and counter 106 is incremented. When the gate combination 140 is open, the content of the counter 106 reaches the data register 104 as a compressed word.

No 1 bit gets into bit position 110 because division F (2n + 2) is not the beginning of a line. However, a 1 bit is fed into bit position 112 to indicate that it is a compressed word. Bit position 114 is fed a zero to indicate that the compressed word represents zero bits.

This compressed word arrives in the second word position of the third memory line of the oil buffer 10 as word W {2n + 2).

The fourth horizontal scan line initially has a total of 16 zeros. These redundancies are counted in the counter 106 as before, and the count resulting therefrom is fed into the data register 104 as a compressed word. This compressed word arrives with the associated connection bits as word W (3n + 1) in the first position of the fourth memory line. The subsequent words of the fourth scanning line are fed into the remaining positions of the fourth memory line of the B 1 buffer 10.

The storage according to FIG. 7b shows a pseudo-image of the original image 1 due to its arrangement. The image is only a pseudo-image, because the storage of the data in the B 1 buffer is arbitrary, with the only restriction that the readout of the Data is done according to corresponding departments of adjacent lines of the original document. The β 1 buffer is scanned word by word, as in the text of FIG. 6 explained. First, the words in the first column are compared with one another in order to determine vertical redundancies in this column. Once this has happened, the words in the second column of this buffer are compared with one another in a second scan in order to determine the vertical redundancies in this column. Once this is done, the third column of the B 2 buffer is searched for vertical redundancies in that column and this process continues until the entire storage of the B 1 buffer is scanned and searched for vertical redundancies.

In the selected example, the readout of the B 1 buffer begins as soon as 7 horizontal scanning lines have been completely scanned. A transmission cycle for the transmission of data to the f? 1-buffer in the 2-buffer is triggered by the output signal M of the decoder 178 .

The vertical compressor compares corresponding divisions of adjacent scan lines for vertical redundancies. If the words of corresponding divisions of the horizontal scanning line are not the same, detailed words go directly to the vertical compression register 204. On the other hand, if words in the B 1 buffer 10 correspond to the corresponding divisions of the horizontal lines are the same, then these redundancies or redundancies are used. these identities counted. In such a case , a compressed word indicative of the size of this redundancy goes into the vertical compression register.

According to FIG. 5, the word W 1 arrives in the first word position of the first memory line of the B 1 buffer in the output register 202. A test signal is generated on the line 216 and aa arrives at the AND circuit 214. Since no comparison is made, you at

the comparator 210 has no output signal. The result is a positive output signal at the inverter 212, which in turn results in a positive signal on the line 213, whereby the gate combination 206 is opened so that the content (here the word WX) from the output register 202 reaches the data collector 208 .

After the first word Wi has been transferred to the data collector 208, the second word W (n + 1) reaches the output register 202. A test signal now occurs again on the line 216, which applies to the comparator 216. Since the word W \ is identical to the word W (n + 1), an output signal is produced at the output of the comparator 210 on the line 215, which is applied to the counting register 222. In contrast, there is no positive output signal at inverter 212. The decoder 224 then opens the gate combinations 206 and 220 via the OR circuit 218. The words that were in the output register 202 and in the data collector 208 are thereby switched on.

Another word W {2n + \) is now incorporated into the output register 202 and compared with the preceding word W (n + 1), which is already in the data collector 208. These two words are not the same, and thus there is no output signal at the comparator 210, but there is an output signal at the inverter 212, which opens the gate combinations 206 and 222 via the OR circuit 218.

The output signal of the OR circuit 218 also opens the gate combination 226, so that the counter contents of the counting register 220 reach the vertical compression register 204, namely in the bit position 228, 230, 232. However, since only two words, namely the words Wi and W (n + 1) were identical, only a 1-bit gets into the bit position 230. The compressed word in the vertical compression register 204 that results therefrom therefore stands for the first two words of the first column of the B 1 buffer 10.

The counting register 222, which can only count up to 7, as already mentioned above, is switched back by an output signal of the OR circuit 218 with the interposition of the delay 234. The size of the delay is approximately one microsecond. Since the next word W (2n + 1) is not identical to the two preceding words in this column, there is no identity and no output on

Comparator 210. However, there is an output at the OR circuit 218, which the gate combination 206 and 220 opens. In this way, the content of the data collector 208 reaches the vertical compression register 204.

Since no identity was determined, the second word W (2n + 1) arrives as a detailed word W'2 in the second word position of the first line of the B 2 buffer 18.

In the first word position of the first line of the

ίο 2- B buffer is the word W '1, which is a compressed word, indicating that the words W and W (n + 1) are identical. Since the fourth word in the first column W (3n + 1) is not identical to the preceding word W (2n + 1), this fourth word arrives as a detailed word W'3 in the third word position of the first line of the 52 buffer . After seven words in the first vertical column of the B 1 buffer have been scanned in this way, the words in the second column of the B 1 buffer are scanned and examined for vertical redundancies.

According to FIG. 7, there are no identities under the words W2, W (n + 2) and W (2n + 2) in the second column. For this reason, these words are all fed into the first three word positions of the second line of the 52 buffer 18 as detailed words, namely W '(n + 1), W' (n + 2) and W '(n + 3). After the second column of the B 1 buffer is scanned, the third column is scanned. Since the word W3 is identical to the word W (n + 3), this identity is determined in the comparator 210 and a compressed word W '(2n + 1) is written in the first word position of the third line of the B2 buffer . This scanning of the B 1 buffer continues over all vertical columns, the redundancies being reduced by comparison, as described. In the exemplary embodiment shown, 7 words in a column are always compared with one another, although this comparison, in a modification of the exemplary embodiment shown, can also extend to a different number of words.

After horizontal lines are scanned in the present example 7 and therefore 7 memory lines of the B 1 buffer are dumped 10, the reading of the B takes one buffer while simultaneously can be scanned of 7 horizontal scanning lines of a new group, and the resulting words into the B ! Buffer 10 can be fed.

In addition 5 sheets of drawings

Claims (9)

Patent claims: 1. A method for the compressed storage of the binary video data sequence for an image scanned in the line raster, in which, instead of a sequence of identical bits, a compressed word characterizing the scope and polarity of this sequence is stored, characterized in that the successive bits of the video data (A) within the individual scanning lines in successive divisions (F), each comprising the same number of bits, are examined for transitions (0-1; 1-0) that in the case of a transition the relevant division as a detailed word, in the case of no transition the relevant department with all subsequent same of this line is stored as a horizontally compressed word in a first storage, and that this first storage is stored word-by-word and column-wise in relation to the scanning grid in a second storage, with similar successive words of a column section in one of the information content d vertically-compressed word indicative of the number of repetitions are stored. 2. The method according to claim 1, characterized in that in the first storage all Words - the detailed and the compressed - are appended in the same way connection bits, which the word character - detailed or compressed and the sign of the compressed bits Show. 3. The method according to claim 1 and / or 2, characterized in that the information bits one horizontally compressed word the number of repeated divisions for which the relevant horizontally compressed word stands, in binary form, and that for repetitions that are the maximum exceed the number expressible with the information bits, a new word for the first memory is written. 4. The method according to one or more of the preceding claims, characterized in, that the first storage takes place in a spatial line structure in which the words from the bits of a scan line are written down in a memory line that the memory lines in the the same spatial order as the associated scanning lines are arranged one below the other and that the words of a memory line in the spatial order of the associated departments are enrolled. 5. The method according to one or more of the preceding claims, characterized in, that the connection bits of a word of the first storage also indicate whether the relevant Word or not at the beginning of a scan line. 6. The method according to one or more of the preceding claims, characterized in, that in the restoring the words of the first storage each have the same number of Counting bits is added, which counting bits indicate how often a word of the first storage by the relevant word of the second storage is expressed. 7. The method according to claims, characterized in, that the information part of the words of the second storage is identical to the information part of the associated word of the first Storage plus at least those connection bits, the sign and number of the compressed Identify bits. 8. The method according to one or more of the preceding claims, characterized in, that the second storage while maintaining the spatial column structure of the first storage he follows. 9. The method according to one or more of the preceding claims, characterized in, that in a cycle of restoring only a number of identical words from a column of the first storage is considered, which is determined by the count bits of a word of the second Storage can be expressed in binary form.