DE1499173C - Sorting circuit for sorting information provided with addresses - Google Patents

Description

The invention is based on a sorting circuit for sorting information data provided with addresses depending on their respective address under transmission from an input memory into an output memory with a reading device that automatically scans the input memory, a buffer that accepts addresses read out from the input memory, one of the addresses in the buffer with the addresses in the input memory comparing comparator and a register, the one read into the output memory depending on the comparison result Address, its associated data, as well as all following data with the same address entered according to patent 1 449 535.

It is well known that electronic data processing devices, calculating machines and accounting machines are involved data often provided with addresses in chronological and thus unordered order in a memory. They must therefore be appropriately sorted before processing, which is done with the sorting circuit succeeds according to the main patent in an expedient manner.

This sorting circuit has a simple structure and works quickly and automatically. Moreover, it is for them various data carriers and codes can be used. The result of the sorting process is in the output memory (in contrast to the input memory) all different addresses only once before, followed by all associated data.

However, the relatively simple structure of the sorting circuit according to the main patent does not allow simultaneous with the summary of all data under their respective address in the output memory the Arrange addresses yourself in increasing or decreasing order. So that the sorting circuit between the already transferred from the input memory to the output memory and those still to be transferred Can differentiate between data, it is also necessary

lent the circuit the data already transmitted provides associated addresses in the input memory with a mark.

The invention is now based on the object of providing the sorting circuit according to the main patent improve that after completion of the sorting process, the addresses in the output memory in, for example increasing sequence, d. H. sorted by increasing numbers, with simultaneous summary all data belonging to a specific address are available at this address.

The German patent specification 594 333 already discloses a method and a system for field-wise Transfer of the hole information from an original strip to a double strip known. Here contains but the original strip (or generally the data carrier) only contains numerical data without addresses that are in such a way are transferred to the double stripe (or generally the output memory) that they finally are arranged according to increasing or decreasing values. A sort of in any code on any address stored as an original storage medium for increasing numbers or decreasing address values with simultaneous summary of all at any point in the original memory, however, the data contained in each case under the same address does not succeed.

Furthermore, from the Swiss patent specification 363 185 a sorting method and a sorting device known that proceed from information provided with addresses on a data carrier. the Addresses are subsequently provided with identifying numbers, whereupon the information, d. H. the data, depending on these address codes from a main memory into a Number of sorting memories are transferred, from where they are transferred back to the main memory, sorted will. As a result, the data are processed depending on their respective address and the Addresses themselves in a predetermined, e.g. B. sorted in ascending or descending order; disadvantageous What is important, however, is that the addresses are initially assigned address codes that control the sorting process must be provided, which is a separate process step and special equipment requires. Another disadvantage can be seen in the fact that just as many sorting stores are required are how different data are available.

On the other hand, the object is achieved with the invention in that the scanning element for the address marking in the input memory both with AND gates of the first inputs of comparators and an AND element as well as with the marking element of the output memory and with the negated input an AND gate is connected and that the scanning elements for the information marks in the Input memory via AND elements each with a storage level of the intermediate memory and via AND elements with the corresponding marking organs of the output memory, as well as via AND gates with the first inputs of the first comparator and via AND gates to the first inputs of the second comparator and an AND gate are connected, and that the second inputs of the first Comparator each individually directly with the assigned stages of the buffer and the second Inputs of the second comparator are each individually connected to the same stages via AND gates, which are unlocked as a whole by the output signal of the AND gate, each time the Input memory is completely scanned, and that an AND gate with its first input via a Line with the output of the first comparator and with its second input via a line with the output of the second comparator is connected to the lines on which a signal then occurs, if the address just read from the input memory (in binary code) is less than the last one in Address stored in the intermediate memory and greater than the last one written into the output memory The address is and the output signal of the AND element is the deletion of the last one stored in the buffer Controls the address and its replacement by the last address read from the input memory, and that if there is a match between the last one read from the input memory and the last one In the address written in the output memory, the second comparator sends a signal via a further line outputs that the transfer of the data belonging to this address from the input memory to the Output memory controls via the AND element, the input memory from beginning to end in a so-called read cycle is read out, and that in the following read cycle on the one hand in the input memory the next higher address than the one last written in the output memory is searched and this is then stored in the buffer and the AND element then uses this address for registration to the output memory and for storage at the second inputs of the second comparator releases, and on the other hand at the same time with each occurrence of the last written into the output memory Address the data associated with this address at various points in the input memory are transferred to the output memory and this process continues until all addresses and their associated data is transferred from the input memory to the output memory.

This ensures that the data in the output memory after the automatic sorting process in a clear form, namely sorted according to increasing addresses, for example. At the same time, this design of the sorting circuit has the advantage that an address marking in the Input memory is superfluous, whereby on the one hand the additional track in the Input memory can be omitted and on the other hand this is not changed by the sorting process.

The sorting circuit according to the invention is also characterized by extraordinary adaptability to a wide variety of memory types and codes.

In the drawing, the sorting circuit according to the invention is shown on the basis of an example selected Embodiment illustrated schematically. It is arbitrarily assumed that the input memory and the output memory is punched tape and in particular the input memory is an endless punched tape is.

F i g. 1 is a block diagram of a preferred embodiment of the sort circuit;

Fig.2 shows a possible embodiment of the Comparator 600 according to FIG. 1.

In Fig. 1 are for those of FIG. 2 of the main patent the same reference numerals are used for corresponding circuit parts.

i 499 173

5 6

In detail, the input memory of the input device 600 is formed by six AND elements 321 to 326, whose perforated strips 200 and the output memory of the respective second input at the output of the AND fork hole strip 300. The input perforated strip 200 is element 270, and finally with that differs from that of the main patent only the first entry of the AND gates 271 to 276 verbund by omitting the marking track; it has 5 den, the respective second input of which is then seven tracks, of which only the six output of the AND element 270 is connected.
The comparators 650 and 600 have the task of being occupied and comparing the seventh track, called address recognition in each case the addresses of the input hole strip 200 to track, to identify an address, in the first comparator 650 with contains the binary digit "one". The input hole strip of the address stored in the buffer memory 500 is scanned by a reading device 20 with seven scanning devices in the second comparator 600 with the last address transmitted to the devices 21 to 27, the output hole strip 300 being transmitted to the scanning device. 27 is assigned to the address recognition track. If between the address of the input hole strip is provided by the further transport of the input hole strip 200 and this to the output hole strip 300 via ^ a motor 128. The address carried by a corresponding motor 15, which is also in the comparator 600

138 transported outfeed hole strips 300 runs unsaved, identity exists, the latter overflows The line 601 sends a signal to a strip punch 30 with seven punch punches 31. This signal is through through 37, which by a main electromagnet is an AND gate 603 with negation of the second input

139 is operated. The motor 138 and the electric lock when a signal on the line 207 bias 139 are idle in sync with the motor 128; H. as long as the one on the output meter Interposition of an AND gate 140 energized, strip transmitted address identical address the blocking conditions of which is still explained below under the reading device 20 in order to be able to recover and taking the necessary delays to avoid fetching on the output strip 300. ( between punching and advancement must be taken into account.

the. 25 the AND gate 603 becomes permeable, since now no Si

The line 201 to 206 of the six first, subsequently on the line 207 is present, and that on

In short, scanning elements 21 to 26 of line 601, known as "buttons", present an address identity signal

of the reading element 20 are each switched on and unlocked the AND element 140, through which the

Electromagnet 139 of the strip punch 30 and the

to the six first inputs of a first comparison ₃₀ motor 138 of the output strip 300 are energized synchronously with chers 650 for binary numbers with six digits under _the motor 128. If now the next interconnection of six AND gates read out address 211 to 216 from the input punched strip 200, the respective second input of which is a larger binary number than the last address transmitted on the output via the line 207 to the pushbutton 27 punched strip, i.e. greater than is closed; ₃ 5 _d j _e j _m Comparator 600 stored address is put on six inputs of an AND gate 270 to the comparator 600 via the line 602 to the entsieben inputs, its seventh input speaking input of the AND gate 520 is a seven If on the line 207 is located; gnal on. If at the same time the same address of the input, “. ... ". ,. ,,. "" Eabelochstreifens 200 a smaller binary number than that at six inputs of a buffer 500; 4O address stored _{in intermediate memory 500}

! ^o u ^SeC i f _n ^s _i t ^{e rSt} - ^nga f ^{e a Ζ Γ} ™ ^VergIe1 ', the comparator sets 650 to the second input

chers 600 for binary numbers with six digits under _the u ^. ^^ 520 over the line 652 a signal!

Interposition of six AND gates _{that the resetting of the six} bistable toggle

221 to 226, the respective second input _{circuits 50} i _{to 506} and then their setting , <■ \

again on line 207, and _{45 in correspondence with that of the} reading device ^ 4

read with the interposition of six AND 20 on the input hole strip 200

Outlines 281 to 286 with negation of the second address.

Input whose negated input at the comparator for binary numbers, which the above for

output of the AND element 270 is, at six elec- the comparators 600 and 650 provided functions

solenoids to set the punching 31 meet 50 NEN are known. For example, FIG. 2

to 36 of the strip punch 30, which are simultaneously with an embodiment of the comparator 600. This

the outputs of six AND gates 271 to contains a first memory register 61, which is made up of

276 are connected. six bistable flip-flops 611 to 616, in which the six binary digits each _:

The buffer 500 consists of a register 55 of the successive, on the input hole!

ster with six bistable flip-flops 501 to 506, fen 200 read by buttons 21 to 26 and from i

whose "one" position corresponding inputs on the button 27 identified addresses stored j

lines 201 to 206 are interposed, and a second storage register of the same type |

of AND gates 511 to 516, whose respective 62, which in turn consists of six bistable toggle switch \

ger second input is composed of a delay element 521 60 lines 621 to 626, in which the

connected to the output of an AND gate 520 six binary digits of the current for the

is, which also with the reset inputs of the same transmission to the output hole strip 300

chen bistable flip-flops 501 to 506 and have been stored with the selected address. This !

a starting terminal 522 is connected. The outputs are set in the appropriate state

"One" of the bistable multivibrators 501 to 506 65 via AND gates 221 to 226 on the one hand and AND

are on the other hand via the lines 401 to 406 with the six members 321 to 326, with of course j

second inputs of the first comparator 650, furthermore of course the resetting of the bistable multivibrators;

with the six second inputs of the second comparator 600 through a common, the input

position preceding reset signal can take place, as was done previously for the buffer 500 has already been specified, or by some other known measure. The working principle of this comparator is that the number stored in the memory register 61 is then greater than that in the The number stored in memory register 62 is the same digit of the binary number if they correspond to one another associated bistable flip-flops of both storage registers, starting from the highest Place at which these corresponding bistable multivibrators have different states, the bistable flip-flop circuit of the storage register 61 assumes the "one" state and the corresponding one The bistable flip-flop circuit of the storage register 62 assumes the "zero" state. The exit "Eins" of the bistable flip-flop 616 of the memory register 61, which corresponds to the greatest binary value, and the output "zero" of the corresponding flip-flop 626 of the storage register 62 are therefore connected via an AND gate 6161 to an input of an OR gate 63, the output of which is on line 602. The outputs "one" on the one hand and "zero" on the other hand of the bistable multivibrators 616 and 626 are connected to the two inputs of an OR element 6164 via AND elements 6162 and 6160 connected. It thus occurs at the output of the OR gate 6164 a signal when the two flip-flops 616 and 626 are in the same state. This output signal is unlocked AND elements 6153 and 6156, which are in series with AND element 6151 and OR element 6154, of which the former emits a signal when the bistable flip-flop 615 is in the "one" state and the flip-flop 625 is in the "zero" state and the second of which is a signal delivers when these two bistable multivibrators have the same state. The output of the AND gate 6153 is via the OR gate 63 on the line 602, and the output of the AND gate 6156 is connected to one of the inputs of the AND gates 6143 and 6146, and to their second inputs are connected to the outputs of the logic elements, which are used to compare the states of the bistable flip-flops 614 and 624 are used. This circuit structure is repeated as often as the one to be compared Storage register stages, each stage on the one hand delivering a signal on line 602, when the corresponding bistable multivibrators are in the next higher binary value are assigned, are in the same state and the bistable multivibrator of the storage register 61 of the relevant stage in the "one" state and the corresponding bistable multivibrator of the storage register 62 are in the "zero" state; on the other hand, each stage supplies an unlock signal to corresponding logic gates the stage assigned to the next lower binary value if the bistable multivibrators of one's own level are in the same state. The output signal of the AND gate 6116, this indicates that all corresponding levels of the two storage registers are in the same State, d. This means that the numbers stored in the two memory registers are identical, is on line 601.

The operation of the sorting circuit is as follows: Before the start of the scanning of the input hole strip 200 this is arranged in such a way that its first address is below the reading member 20. Will the Circuit put into operation, a signal is sent via devices not shown on the one hand to the Terminal 522 of buffer 500 is applied in order to reset the bistable multivibrators 501 to 506 and after a short delay caused by the delay element 521, the switching on of the To cause AND gates 511 to 516, whereupon the first address of the input hole strip 200 in the bistable Flip-flops 501 to 506 is stored. On the other hand, the mentioned signal will also to a reset input, not shown, of the storage register 62 in the second comparator 600. On the first complete pass of the input hole strip 200, i. H. in the first cycle, at to which all addresses on the input punched strip are greater than "zero", the delivers second comparator 600 constantly on line 602 a signal and each of the successive addresses of the input hole strip 200 is in the first comparator 650 with the last one in the buffer 500 stored address compared. Every time ■ when the reading element 20 on the input hole strip 200 scanned address lower than the address stored in the buffer 500 is, the first comparator 650 supplies a signal on the line 652, which passes through the AND gate 520, the bistable flip-flops 501 to 506 resets to "zero" and then the AND gates 511 to 516 unlocked, whereupon the bistable flip-flops 501 to 506 via lines 201 to 206 die received by the buttons 21 to 26 emitted signals. After scanning the last address of the input strip 200 is thus the lowest address stored in the buffer memory 500 Address, d. H. the one with the lowest number, which is located on this input hole strip. The Signal "end of strip" is a special address in which all seven lanes of the original strip 200 are the binary digits Contain "one" and cause a signal to appear at the output of AND gate 270, which results in has,

that the lines 201 to 206 of the electromagnets to control the punching 31 to 37 of the strip punch 30 separated by blocking the AND gates 281 to 286 with negation input will;

that the AND gates 271 to 276, via which the electromagnets of the punching holes 31 to 36 are energized or de-energized, depending on whether the bistable flip-flops 501 to 506 are in the "one" or "zero" state, are unlocked;

that the AND gate 140 is unlocked, which controls the main electromagnet 139 of the Punch 30 and the output hole strip 300 driving motor 138 releases, and

that the AND gates 321 to 326 are unlocked via which the in the buffer 500 stored address is transferred to the memory register 62 of the comparator 600.

In the following scanning cycle of the input hole strip 200, the two processes become simultaneous continued, namely on the one hand the storage of all data of the input hole strip 200 which the

transferred address are assigned to the output punched tape 300, on the other hand, the search for the smallest address after it.

The storage of the data assigned to the last address stored on the output hole strip 300 is controlled by the second comparator 600 , which emits a signal via the line 601 whenever there is an identity between the addresses stored in its registers 61 and 62 , ie between the last one the address scanned by the reading element 20, the input hole strip 200 and the last address stored on the output hole strip 300. Since the electromagnets of the punch 31 to 36 are excited or not via the lines 201 to 206 depending on whether the binary digits read by the buttons 21 to 26 are "one" or "zero", the signal appearing on the line 601 triggers the Excitation of the main electromagnet 139 of the strip punch 30 and the advance of the output

punched tape 300 synchronously by the motor 138 with the progression of the input hole strip 200 under the premise that there is no signal on line 207, which the repetition of the storage avoids a resolved address on the output tape 300, if it recurs on the input paper tape 200 .

The search for the smallest address after the evaluated address takes place as in the previous one, with the difference that the AND gate 520 is only unlocked if the presence of a signal on the line 602 indicates that the address scanned on the input hole strip 200 is greater than the address evaluated address is.

Thus, the addresses of the input hole strip 200 are registered one by one in ascending order after each scanning cycle on the output hole strip 300 together with their associated data.

1 sheet of drawings

Claims (1)

Claim: Sorting circuit for sorting information data provided with addresses depending on their respective address with transfer from an input memory to an output memory with a reading device that automatically scans the input memory, a buffer that accepts addresses read from the input memory, and a buffer that compares the addresses in the buffer with the addresses in the input memory Comparator and a registration element which, depending on the comparison result, enters a read address, its associated data and all subsequent data with the same address into the output memory, according to Patent 1449 535, characterized in that the scanning element (27) for the address marking in the input memory (200) both with AND elements (211 to 216, 221 to 226) of the first inputs of comparators (650, 600) and an AND element (270) as well as with the marking element (37) of the output memory (300) and with the negated one Input of an AND-glie d (603) is connected and that the scanning elements (21 to 26) for the information markings in the input memory (200) via AND elements (511 to 516) each with a storage stage (501 to 506) of the intermediate memory (500) and via AND Elements (281 to 286) with the corresponding marking elements (31 to 36) of the output memory (300) and via AND elements (211 to 216) with the first inputs of the first comparator (650) and via AND elements (221 to 226) are connected to the first inputs of the second comparator (600) and an AND element (270) and that the second inputs of the first comparator (650) each individually directly to the associated stages (501 to 506) of the buffer (500) and the second inputs of the second comparator (600) are each individually connected to the same stages (501 to 506) via AND gates (321 to 326), which are unlocked as a whole by the output signal of the AND gate (270) , each time the input memory (200) complete ig is scanned, and that an AND element (520) with its first input via a line (652) to the output of the first comparator (650) and with its second input via a line (602) to the output of the second comparator ( 600) is connected, on which lines (652, 602) a signal occurs when the address (in binary code) just read out from the input memory is less than the last address stored in the buffer memory (500) and greater than the last address in the output memory (300) is written address and the output signal of the AND element (520) controls the deletion of the last address stored in the buffer (500) and its replacement by the last address read out from the input memory (200) , and if there is a match between the last The second comparator (600 ), which is read out from the input memory (200) and the last address written in the output memory (300) , sends a signal a via a further line (601) It controls the transfer of the data belonging to this address from the input memory (200) to the output memory (300) via the AND element (603) , the input memory (200) being read from beginning to end in a so-called read cycle, and that in the following read cycle, on the one hand, the next higher address than the one last written in the output memory (300) is searched for in the input memory (200) and this is then stored in the buffer (500) and the AND element (270) then sends this address to the Output memory (300) and for storage at the second inputs of the second comparator (650) and, on the other hand, at the same time each time the address last written into the output memory (300) occurs at different locations in the input memory (200), the data associated with this address is transferred to the output memory (300) and this process continues until all addresses and their associated Data are transferred from the input memory (200) to the output memory (300) .