DE1487956B2 - PROCEDURE AND CIRCUIT ARRANGEMENT FOR REMOTE SIGNALING, IN PARTICULAR TELEPHONE SWITCHING SYSTEMS WITH ROUTING - Google Patents

Description

The invention relates to a method for controlling the overflow in telecommunications, in particular Telephone exchanges with routing in which the conversion of call control criteria in directional codes in a buffer containing the corresponding assignments happens, with a first outgoing one determined by directional information when busy Bundle one after the other more directional information to set up detour connections are formed.

It is known in telecommunications switching technology that routing in larger networks is dependent to be carried out by one of the code assigned to the message to be conveyed. Because of the diversity the options that are often available,

To transmit a message from one point to another is known to involve entering a code Directional information to be supplied depending on the traffic status of the outgoing trunk group form. Among the ways in which a message can be transmitted between two points are then of course differences in their value. Doing so will be the path that has a direct connection between both points allows to be the cheapest, while others that have one or several intermediate stations run, so-called detour connections, will be less favorable. Stand accordingly, a switching center has several routes to a destination available, so the conversion device taking into account the free-busy status of the outgoing lines, the cheapest Route determined, d. In other words, if the cheaper route is occupied, it becomes the next cheaper route passed over.

Known conversion devices of this type work according to the shutdown control principle. Included a cut-off relay is assigned to each outgoing bundle of an office, which indicates the direction of the bundle either releases or causes another bundle-dependent statement in the case of busy. the Outputs of the correcting devices performing the code number decoding are in this case via contacts this switch-off relay optionally connected with different directions.

In communications networks with automatic switching devices, it is a particular problem to work completely freely with regard to this routing, ie to be able to specify overflows in any order. The problem becomes particularly urgent when working with a free distribution of key figures. To explain the possible sequence in such a communication network, reference is made to FIG. 1, in which switching centers indicated by circles are present in two different network levels. In order to get from a point X to a target point Zl, there are the possibilities that are indicated with A, C, D and E. In order to get from the office X to a destination Z2, there are the options that are designated with B, C, D and E. Now, for example, a sequence A, C, D and E can be specified for a message to be sent from X to Zl, which the corrector must then adhere to when entering the code Zl. For a message to be transmitted from X to Z2, for example, the sequence B, E, D, C can be specified, which must then also be adhered to when entering the code number Z2. It is easy to see that in addition to the orders given as examples, a whole range of other orders are possible for a switch. The routing that has been common up to now, with which the overflows are controlled with the aid of cut-off relays, works too slowly to be able to exploit the advantages offered by a multitude of detour options. In addition, because of the considerable effort involved, such a routing is not only confusing but also does not allow rapid changes to the overflow distribution. For these reasons, this type of overflow control is not suitable when routing has to work quickly and freely.

The invention is based on the object of the overflows in the busy case of outgoing bundles to control in such a way that the output of a direction information, the bundle check and the indication of an overflow, if necessary, very quickly is processed, with any assignment between the key figures and the overflow addresses is possible and all possible overflow consequences in a simple Way are adjustable.

According to the invention, this is achieved in that the conversion, known per se, in a first The area of the cache is where the content of the based on the assignment in the first area found memory word as address information for a second and third area of the buffer is used, the memory word addressed in the second area as well as the direction information for the first outgoing bundle as well as address information for an overflow word in the first Area and the memory word addressed in the third area provides information about the occupied status of the contains outgoing bundle in question and that with at least one free line in the outgoing in question Bundle of this the directional information is passed on to the second area while in the case of a completely occupied outgoing trunk group, the overflow word is activated in the first area will.

If the test in the third memory area shows that there is still a line free in the outgoing first bundle is, the direction information is offered to the requesting register as a convenient route information. Yields however, the check that all lines in this direction are busy is also checked in the second Storage area of the buffer store information stored as an address for the next overflow word used in the first memory area to target the intermediate memory again. So that is again the second and third memory areas can be controlled, so that the occupancy status of the first Overflow path and the address that may be required for a further overflow stands. According to one, through the number of possible directions within a given order certain overflows, all outgoing bundles in question are activated when they are busy of the last memory word instead of directional information a busy criterion and as Address for further overflows, e.g. any number, output.

The principle of permissive overflow is explained below with reference to the tables given in FIGS. 2a and 2b. It has been assumed that there are three trunk groups, namely A , B and C, for which a total of 15 different sequences for routing can be established. In FIG. 2 a the 15 possible sequences are listed in detail.

Each of the three directions can be combined with five different overflow sequences. Accordingly, five words in the buffer are sufficient for this example to combine each with a different overflow address , for example in direction A.

In Fig. 2b, these combinations are also in table form together with a control address for the first memory area, which is supplied from the identification point, and an overflow address for the first memory area formed in the second memory area is shown. It should be used for

It can be assumed that when entering a certain code, for example 2853, the route sequence B, C, A should be adhered to. The output of the code point 2853 is connected to the address input 5 of the first memory area in the intermediate memory, whereby the direction information for direction B is output from there and the bundle status of B is checked. At the same time, this information is also used to control the second area in the buffer. The address for word 12 in the first area is contained there as the overflow address. If all lines in bundle B are busy, the overflow address for direction information C is indicated. In the second memory area, the overflow address for word 13 in the first memory area is thus formed at the same time. If the bundle in direction C is also occupied, the first memory area is controlled again, now with the overflow address 13, whereby the direction information A is output and the bundle in direction A is checked. If no free output is found here either, the next address 16 in the second memory area sends a busy signal to the requesting register.

If one proceeds according to the invention, there is not only the possibility of achieving multiple overflows, but also with the help of the stored overflow addresses all to one within a very short time Check the marked paths leading to the destination, whereby no spaces are required. Also is the allocation of addresses is purely arbitrary, so that any words that have become free can be used by others at any time Overflows can be used, which has the advantage that not all conceivable combinations of several bundles have to be programmed, since with the help of free words a program extension without Change in the existing part of the program is possible.

A particularly advantageous arrangement for implementation of the method arises when an electronic memory, for example a magnetic core memory is used. Such a circuit arrangement is shown in FIG. 3 has been shown. Further details of the invention are explained with the aid of this figure.

The corrector shown in FIG. 3 contains the code conversion device K, which is divided into two stages, namely KAB and KCD , in accordance with a requirement that four-digit codes (A, B, C, D) are available. The lines arriving from the requesting registers are routed to the key figure inputs KE of these correcting devices. The code number offered is decoded in such a way that the first corrector KAB is controlled by the first and second input coordinates and the second corrector KCD is controlled by the third and fourth input coordinates. An output of the corrector circuits is excited by two input coordinates. Since such corrector circuits are known per se, they will not be discussed in more detail. The intermediate storage itself consists of a first intermediate storage area WA and WB with the magnetic cores KAI to KA20 and KBl to KB20, a second intermediate storage part R with the magnetic cores KR 1 to KR15 and a third intermediate storage area B with the magnetic cores KBl to KBlOO. As we will explain later, is determined by the magnetic cores KAI to KB20 that to be controlled in the overflow word, by the magnetic cores KRl to KR15 the desired direction statement and by the magnetic cores KBL to KBlOO the bundle core of being tested bundle. The outputs of the key figure conversion devices , which were designated with AlBl to AOBO and ClDl to CODO, are connected to one another via jumper lines, which in turn are connected in this way by the magnetic cores KAI to

ίο KB20 of the first buffer area are carried out so that the start and overflow addresses for the program are formed. This method will be referred to below as potential coincidence. If, for example, the code number 1001 is offered by a register, the output A1BO in the license plate converter KAB and the output COD1 in the license plate converter KCD are energized. In this case, a current only flows through the jumper wire connecting these two outputs. The individual jumper wires are decoupled by special decoupling diodes, only one of which is shown. To carry out a second potential coincidence method of this type, further control switching means MA and MB are present, which on the input side are connected to the cores KAI to .020 of the first buffer part via sense amplifiers VAl to VA20 , that is to say can be controlled by the latter. The outputs WAl to WA20 of the first and the outputs WBl to WB20 of the second control switching means are in turn connected with jumper wires, which are now guided both through the coils of the cores KAI to KB20 of the first, KRl to KT15 the second and Bl to Bloo of the third staging area . Each of these wires routed between MA and MB thus represents a word of the buffer memory. The stored information is defined as a result of the routing by the cores of the first memory area WA-WB, the second memory area R and the third memory area B. In the first memory area the word to be controlled in overflow is given, in the second memory area the desired directional information and in the third memory area the bundle core of the bundle to be checked. Just like the cores of the first memory area, the cores KjRI to KR 15 of the second memory area jR are assigned sense amplifiers, which are designated VR1 to VR15 and which act on pulse relays Rl to RlS that are available for the output of direct current criteria to the requesting registers . All cores of the third memory area B are assigned a common sense amplifier VB , which acts on a device BU storing the direction result. The query of the buffer memory and the display of control switching means MA and MB is done by timing pulses Tl and which are taken from a clock generator which is denoted by TG, Ύ2.

To explain the function of a corrector constructed according to the invention with buffers, it is assumed that all cores of the buffer are deleted in the idle state and that the pulse relays A1 to RIS are in the idle state. If, for example, the code number 1001 is offered by a register (not shown), then in the first code number corrector KAB the output AlBO in the second code corrector KCD is replaced by the last two coordinates of the code number

i 487 956

the output CODl is marked. In the example described here, the jumper wire connecting these two outputs is led through the cores KA2 and KBl of the first buffer area WA-WB , whereby the start address for the route search is defined in the buffer. After the storage, the clock generator TG is caused to emit the first clock pulse 71, by means of which the address core field, that is to say the first memory area WA-WB, is queried. Since the cores KA2 and KBl are set in this case, the corresponding inputs of the control switching means MA and MB are set via the sense amplifiers VA2 and VBl. When the second clock pulse 72 arrives, the outputs WAI and WB1 are accordingly set in the last-mentioned control switching means . Via the memory area WA-WB connecting these outputs and the second memory area /? and the jumper wire routed to the third storage area B of the buffer store now flows a current. As a result, the address for the next overflow word is written into the first memory area of the buffer memory. At the same time, the corresponding direction result is thereby also written into the cores KR1, KR2 and KR 15 in the second memory area R. Since the jumper wire is also routed through the core KB3 of the third memory area B , the bundle assigned to this direction is queried at the same time. The principle of the bundle check works in such a way that only when the bundle is free does a read signal reach the memory device BU via the read amplifier VB assigned to all cores of the third memory area. Assuming that this has happened, a release signal will also be sent to the pulse relays Rl to R15 on the second occurrence of the clock Tl, by which the set directional cores are now queried. The pulse relays of the output, which received a read pulse from this when the result cores KR 1 to KR15 occurred during the occurrence of the clock pulse Tl , are started. At the same time, the clock generator TG is stopped and the revaluation is marked as finished.

In the event that when the clock pulse TL occurs for the first time there is no bundle free message in the memory BU , the directional field R is queried by the second occurrence of the clock pulse Tl without the pulse relays Rl to R15 being started. In this case, the overflow address stored in the cores KAI and KB20 is transferred to the devices MA and MB via the sense amplifiers VAl and VB20 , so that when the next clock pulse 72 occurs, the outputs WAl and WB20 are marked and the address for the next overflow word is in the Cores KA2 and KB2 is enrolled. Simultaneously with this, set the A-usgänge WAl WB20 connecting jumper wire and the second storage area R of the core KR2 and in the third storage area B of the core over the KBL. There, in the manner already described the bundle core is queried for this direction, whereupon decided in the next cycle Tl, whether the result of the direction field can be issued or whether a new overflow word must be controlled.

It is evident that the number of overflows sequentially queried in this way corresponds to each the case occurring in practice is adaptable.

After querying the last bundle in a sequence, if this also has no free line, a busy message is issued.

Directional information is usually not only made up of the digits leading to a voter setting is necessary, but also further information, for example for the work program contains, all of this information, which belongs together for a specific bundle, must because of the

ίο possible overflows multiple times in the buffer be stored. In the case of large correctors, it is therefore advantageous to have a separate directional field for the statements to be provided. This is done by an extension within the scope of the invention dad ..:

¹ S account is taken of the fact that the jumper fields for ..ue start addresses and for the overflow addresses are arranged separately in the buffer. An arrangement corresponding to this extension is shown in FIG. 4 shown. The code number entered is decoded, as shown in FIG. 3, with the help of the potential coincidence principle. In contrast to the one shown in FIG. 3 is the arrangement shown, but here is the code assignment to; Start address and the overflow addresses are routed in separate core fields. Like λόγ, however, this first memory area is WA-WB. the individual cores are designated with KAI to KB20. However, a separate clock input 71 is now available for both shunting fields. In order to avoid the difficulties that arise in larger offices, which, as already described, arise from the fact that the information that belongs together for a bundle is more extensive, according to this expansion, the intermediate storage part available for the statements of the direction information is available as a separate direction routing field, which is in the Figure, however, is still denoted by R. A particularly advantageous embodiment is obtained when there is an additional memory labeled Z, in which only the address of the direction to be controlled is stored in coded form. In the example shown in FIG. 4, the individual cores of this intermediate storage part Z are denoted by ZAl to ZAn and ZSl to ZBn . The storage of the address of the direction specified by the code number and the overflow address is done in the manner already described via the two devices MA and MB, whose outputs WAl to WA20 and WBl to WB20 with the help of jumper wires over the cores both of the first memory area and over those of the additional memory Z are performed. In addition, each core of the memory Z is assigned read amplifiers ZVAl to ZVBn, which in turn are routed to control switching means MZA and MZB assigned to the memory area R. The outputs of these control devices ZWAl to ZWAn and ZWBl to ZWBn are also connected via jumper wires , which in turn are routed both via the cores KRl to KRn of the memory area R and via the cores of the memory area B. Both the evaluation of the address of the direction to be controlled in coded form in the memory Z and the evaluation of the direction address in the memory area R as well as the bundle testing of the bundle cores assigned to this direction in the memory area B is done in the manner already described using the potential coincidence method. For this purpose, the

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Clocks ΓΙ and Tl alternately applied to the corresponding inputs, whereby an overflow word is queried in the memory area WA-WB , the direction address in memory Z and the direction information in memory area R in the manner already described. If a line is free, the bundle core B assigned to this direction address is reported and the sense amplifier VB of the bundle interrogation sends a positive test result to the memory BU, causing the pulse relays Rl to Rn, which are marked by set cores, to output a result will. At the same time, the clock generator, by which the clocks Tl and Tl are generated, is stopped.

If, on the other hand, the test shows that there is no free line, the pulse relays Rl to Rn are not released, nor is the clock generator switched off. In the first storage area then the saved in the previous case overflow address is output using the potential coincidence check by the clock Tl and the process is repeated with this information.

This advantageous expansion of the circuit arrangement according to the invention allows changes to be made only having to make one point of the statements in a bundle. Because the coded Representation of the direction number in the additional memory Z happens, the effort is with a change less than if the direction information itself were stored.

That on the basis of FIG. Procedures shown in FIGS. 3 and 4 the code number evaluation through partial decoding and direct control of a code number wire, whereby The coding of the key figure was achieved via potential coincidence, however, is not the only one Possibility of a key figure evaluation. The method according to the invention can also be used advantageously apply to a key figure evaluation according to the search procedure. The key figures are suitable Routing stored in a core field. When a key figure occurs, a search is carried out started, in the course of which the key figures saved in the core field with the key figure entered be compared. If the comparison is positive, the result saved by the code wire is also saved read out and used as a searched assignment.

A basic circuit diagram for such a key figure evaluation according to the search method is shown in FIG. 5 for four-digit codes. The respective numbers I to IV are assigned core fields with the cores KIl to KlO to KlVl to XIVO. In addition, there is a core field WA- WB with cores KAI to KB 20 that also stores the result. The jumper wires arranged between the outputs of two clock distributors, which are for example shift registers and are designated TA and TB , lead over all cores All to KB20. The result stored in the cores KA and KB is only given to the outputs WAl to WB20 via the sense amplifiers VAl to FB20 if the comparison of the entered code number with the stored code number is positive. These outputs are, for example, the inputs of the control switching means MA and MB in FIGS. 3 and 4.

Another possibility for implementing the method according to the invention is shown in FIG. 6, as is the circuit arrangement in FIG. 4 also offers that of FIG. 6 options for reducing the maneuvering effort. As can be seen from FIG. 4, the direction address which is supplied by the memory Z consists of zv / ei information ZA and ZB, of which an element of the subsequent memory device MZA and MZB was marked. The direction selector field was then set from there. In a two-stage direction selector field, all combinations for a binary encrypted code, for example, can be wired in the wires ZA. The coding can also be carried out for all combinations of a second code, for example binary encrypted, by wiring the wires ZB . The circuit arrangement of FIG. 6 is based on these considerations. For example, the combinations of the first selection level can be wired in the wires ZA. It is also shown here that the bundle cores and the decoupling diodes can be hard-wired so that the only routing that has to be carried out is to generate special statements. For this purpose there is a further memory area KS with the cores KS1 to KSn , via which the outputs of the hard-wired combination-forming core fields LA and LB are routed.

The mode of operation of the circuit arrangement indicated in FIG. 6 is in principle the same as that that described in the previous arrangements.

For this purpose 2 sheets of drawings

Claims (9)

Patent claims: 1. A method for controlling the overflow in telecommunications, in particular telephone exchanges with routing, in which the conversion of connection control criteria into directional codes takes place in a buffer containing the corresponding assignments, with further directional information for the establishment in succession when a first outgoing bundle determined by directional information is busy are formed by detour connections, characterized in that the per se known revaluation takes place in a first area (WA, WB) of the buffer that the content of the memory word found on the basis of the assignment in the first area (WA, WB) as address information for a second and the third area (R, B) of the buffer is used, the memory word addressed in the second area (R) serving both the direction information for the first outgoing bundle and address information for an overflow word in the first area (WA, WB) and the memory word addressed in the third area (B) contains information about the busy status of the outgoing trunk in question and that if at least one line is free in the outgoing trunk in question, the direction information is transferred to it from the second area, while in the case of a fully occupied outgoing trunk, the overflow word is controlled in the first area (WA, WB). 2. Circuit arrangement for carrying out the method according to claim 1, characterized in that the intermediate memory is a magnetic core memory, the first memory area (WA-WB) of which connects the outputs (AlBl to CODO) of known conversion devices (KAB, KCD) Jumper wires can be controlled that further control switching means (MA, MB) are available, the inputs of which can be controlled via the read amplifiers (VAl to VB20) assigned to the cores (KAI to KB20) of the first memory area in accordance with the word controlled in the first memory area (WA, WB) of the intermediate memory and whose outputs (WAl to WB20) are routed to the cores of the first, second and third areas of the buffer in such a way that they contain the next overflow word in the first memory area (WA, WB) and the memory word of the first in the second memory area (R) Form corresponding direction information in the memory area, while in the third memory area (B) a bundle test du can be performed, the result of which is stored in a bundle test result memory (BU) . 3. Circuit arrangement according to claim 2, characterized in that the number of in the first Storage area of overflow words that can be formed is arbitrary. 4. Circuit arrangement according to claim 2, characterized in that for querying the intermediate memory and the control switching means (MA, MB) and the bundle test result memory (BU) a clock generator (TG) is present, which sends a first interrogation clock (Π) to all cores of the first and second memory area and a second interrogation clock (Γ2) to all inputs of the control switching means (MA, MB) as well as to the bundle test results memory (BU) supplies. 5. Circuit arrangement according to claims 2 to 4, characterized in that an evaluation switching means , preferably a pulse relay (Rl to R15) is connected to each core (KRl to KR 15) of the second memory area (R) via sense amplifiers (VRl to VR15) and that the evaluation switching means (jRl to i? 15 ) can be controlled via the switching means (BU) storing the bundle test result. 6. Circuit arrangement according to claim 5, characterized in that in the case of at least one free line in the bundle controlled by the directional code, the clock generator (TG) is switched off. 7. Circuit arrangement according to claims 2 to 6, characterized in that between the memory area ( WA-WB) storing the overflow address and the memory area (R) specifying the directional information, there is a further memory (Z), in which the by the code number or the overflow address dependent direction address is stored and that the setting of the cores (ZAl to ZAn and ZBl to ZBn) of this memory is done with the help of the routing of the memory area forming the overflow address (WA-WB). 8. Circuit arrangement according to claim 7, characterized in that second memory switching means (MZA, MZB) are present, the sense amplifiers (ZVAl to ZVBn) associated with the input side of the cores of the aforementioned memory (Z) are connected and their wired outputs (ZWAl to ZWAn and ZWBl to ZWBn) form a jumper field for the cores (KRl to KRn) of the direction memory area (R) and the memory area (B) for the bundle test. 9. Circuit arrangement according to claim 8, characterized in that each one direction a bundle is permanently assigned to the address combination specified.