DE1449528C - Circuit arrangement for generating a Ubetttagsetgebmsses in a. Parallel adder - Google Patents

Description

1 2

The invention relates to a circuit arrangement _ The main disadvantage of this known circuit

for the parallel generation of one from several bits (C <) arrangement is that one has to deal with their structure existing transfer result (C) according to which too many components are required. From the equations

Function (10 to 36) of the mentioned publication shows

5 that the number of AND and OR gates is very high

C ₁ = K ₀ · R ₁ · R ₂ ... Aj-! 8 ^{becomes r} ° ß as the number of expressions increases.

You have to ζ. Β. seven logical products of an OR

+ K ₁ * R ₂ * R ₃ ... Ri-x +. ·. + Kt-X Operate to produce the result W ₃ .

in a parallel adder, where Rt is the result of the io. In another known circuit arrangement, exclusive-OR operation of those operands of the above-mentioned type (arithmetic operation in bits (Au Bi) is "for which the carry bit d is generated by Digital Computers, RK Richards, Ph .D., Will, Kt is the result of the AND operation of the D. van Nostrand Company, Inc., 1955, p. 113 and the end bits At and the addend bits Bt and K ₀ a 114) will be the number for the simultaneous carry bit , which is fed to the adder from the next lower 15 of a certain expression of the half-sum he parallel adder stage, and where this testifies by attaching the carry number from the previous sign "+" the inclusive OR function and the going stages to AND elements, and to be precise with the sign »·« mean the AND connection. together with the half-sums, so that the AND-

The operation of data processing systems depends on the link every time a binary one is generated from the execution of a large number of logical operations, a carry occurs on a bit that is determined by the berations. The requirements for such systems sought expression by means of nothing but binary ones in general, special emphasis on large zuverdistrennt is.

The disadvantage of this known circuit arrangement

Power consumption with simultaneous large processing lies in the fact that the transmission signal

processing speed. The going expression must be generated before the

From the standpoint of reliability, magne- number stands for simultaneous carry for an electronic component in the reputation of being able to obtain significant advantages pressure. The carryover from that to other electronic components to one printout will have to half the sum of the next. In fact, magnetic construction terms have added up and at the same time placed on the AND elements as consistently more reliable than semiconductor elements of the next term, so one element has proven to have dropout digits which carry over if required. considerably lower than that of semiconductor elements. Although this system works faster than the series beds. Serious disadvantages, the one so far with the addition, it is relatively slow. The well-known turn of magnetic components in computers. Circuit arrangement also required one were connected, were that such systems 35 relatively very large number of circuits, all low computing speed and behaves. Another disadvantage is that the known circuitry had high power consumption. processing arrangement not with magnetic components ■ It is known that the addition can be implemented in computers. Magnetic components are the most frequently occurring arithmetic operations and must be operated in cycles, because they are the basis for the other arithmetic operations, 4 ° steep and reset by clock pulses, i.e. subtraction, multiplication and division, depending on the one. So you have to work synchronously with them. The represents. On the other hand, the speed of the addition process, known circuit arrangement sends that which directly influences the carry signals for the other operations at high speed from a time required, is generally passed through the unit to the other. The transfer is not limited by the time that the generated »transfers« take 45 cycle times (asynchronous process),
necessary to go through the adding stages. In order to realize this, however, diodes and magnetic core systems are required for the transmission speed of transistor circuits. Magnetic components of each specific operation by means of clock pulses are, as already mentioned, essentially synchronized. borrowed more reliable and cheaper than transistors and

Binary parallel adders that have a number 50 diodes are known.

generate for the simultaneous carry and this The object underlying the invention is

The number for the half-sum of the end of the eye and the addend is in it, in the case of a parallel adder, the above

add. Here, however, the number for the type mentioned is the simultaneous carryover with a

to generate simultaneous transfer different from the invention minimum of components in such a way that

object generated. 55 also an easy implementation of the carry-over calculation

A known circuit arrangement of this type is possible with magnetic cores.

published in »Digital Computer Design Fundamen- This task is, according to the invention,

tals ”, pp. 390 and 391 by Yaohan C h u, McGraw-solves that a first number of AND gates is provided

Hill Book Company, Inc., 1962. From the equations, each is attached to its input terminals

(10 to 36) on p. 390 of this publication, 60 bits go to the addend and one bit to the augend receives,

shows that the number for the simultaneous carry that the output terminals of the parallel exclusive »

from the expressions X and Y of the addend and the OR element of the parallel adder and the AND

Eye ends can be generated. However, as the limbs with a second number AND gates comparable

P. 391 of the publication, are bound, with one of these latter AND

the functions for the number for the simultaneous 65 terms for each term of the equation

Carry too long to be used - _ _yp _ '

nen if the number of bits in the practical c <- A ₀ · K ₁ · « _a ... K _i - ₁

Range from 20 to 60 bits. + K _x · R, · R _t ... Ri- _t + .. '. + ΑΊ-ι

provided and with its input terminals with the Except for those stages of the parallel adder and connected to the output of those AND gates is their corresponding bits in the expression concerned are included, and that the outputs of each of the second number of AND gates for each equation with the clamps of an inclusive-OR gate are connected, each of these inclusive-OR values the corresponding bit of the carry result for the parallel adder at its output terminal supplies.

Further developments of the invention are characterized in the subclaims.

In this circuit arrangement, fewer components are required than in a circuit arrangement that tries to determine the number for the simultaneous Carry out directly from the bits of the auger and the addend, without first creating the logical one Form product.

The circuit arrangement characterized in claim 2 provides a matrix for the formation the number for the simultaneous transfer by means of an AND link and an inclusive OR link. This matrix uses magnetic elements and in particular magnetic cores in a particularly favorable manner Way to get the result with fewer components.

It is essential for the development characterized in claim 3 that a register for a double Purpose is used, namely first as a buffer register to store the half sums for their Use in the formation of the number for the simultaneous carryover and secondly to carry out the inclusive OR link, which is used to achieve the Number is required for simultaneous carryover. The double use of this register reduces again the number of components required to determine the number for simultaneous carry.

In the further development characterized in claim 4, some further registers are given, which are shown in the circuit arrangement can be used to form the number for the simultaneous shorten transfer time required.

The characterized in claim 5, it is possible with simple means in which Matrix to achieve an exclusive-OR link. The output information is via the inquiry ladder fed to a bipolar amplifier.

Embodiments of the invention are given below explained in more detail with reference to the drawings.

F i g. 1 shows a magnetic core and the associated control lines as a basic unit, as it is used in the exemplary embodiments;

F i g. Fig. 2 is a schematic representation of a parallel binary addition process known as Method I is designated;

Fig. 3 shows in block form the structure of an in Consistency with method I composite arithmetic unit;

F i g. 4 is a schematic circuit diagram for g in the F i. Method 2 and 3 shown;

F i g. 5 shows the addition of two binary numbers according to method I;

6 is a graphical illustration of the multiplication process in accordance with Method I;

F i g. Fig. 7 shows another structure of the components for a method H arithmetic unit;

F i g. 8 illustrates the addition process of Method II; ·

F i g. 9 shows the multiplication according to method II; Fig. 10 illustrates a third variation of the Structure of an arithmetic unit according to method III;

Fig. 11 is a diagram of the addition process according to Method III;

Fig. 12 shows the binary multiplication by means of the method III corresponding variation of the ίο magnetic logic technology.

The in Fig. The basic magnetic component shown in FIG. 1 has the shape of a circular cylinder. The magnetic core of FIG. 1 and all cores mentioned below are intended to be essentially one have rectangular hysteresis loop characteristics. Cores with these properties can be very can be switched quickly from one of two possible magnetization states to the other by a magnetizing force which is exerted by associated electrical windings. Besides that these nuclei can remain in their last assumed magnetic state, even after the force that produced this state has ceased to work. One in the magnetic Information of opposite polarity to be stored elements is arbitrary in binary notation marked with "L" "and" 0 "or" switched "and" switched back ".

The resolution of complex logic by such magnetic elements requires a "zero decoding function", in other words, each magnetic element becomes a. "Core Zero Decoder".

The usual coincidence decoder or the AND circuit satisfies the following logical expression A ₁ A ₂ A ₃ ... Αη-χΑη-

According to the logic rule according to DeMorgan's theorem CD - C + D, in Boolean notation the line over a symbol denotes a NOT function, the plus sign denotes the inclusive OR function and the arrangement of symbols directly next to one another or separated from one another by a point or a multiplication sign the AND function. The line above a group of symbols means that the NOT function applies to the entire expression under the line.

By repeatedly applying DeMorgan's theorem, it is possible to convert the above logical expression for a coincidence decoder into a form which is suitable for use in an anti-coincidence device, ie

B ₁ + B ₁ + B ₃ + ... + B _n , where B ₁ = I.

The use of a magnetic core in the anti-coincidence mode is shown in FIG. 1 shown. Each of the SHIFT, DOWN SHIFT, and OBSTACLE conductors can be selected from one of the FIGS. 1 power source, not shown, are pulsed. It is assumed that the core 10 is originally

is in the DOWNSHIFT state. At time T ₁ , the SWITCH line and also all HINDE-RUNGS lines for which the corresponding input variables are "true", ie B ₁ = I, are energized. Each of the energized lines carries current of sufficient amplitude to switch the core. Under these conditions , the core is switched to the "switched" or "!." State, if and only if none of the OBSTACLE lines

is excited. This means that the following logical expression is fulfilled:

B ₁ + B ₂ + B ₃ + ... + B _n = B ₁ B ₂ B ₃ .. .Ή _η = 1.

At a later time T ₂ BACK CONTROL line is energized. If now the core z. Z. T ₁ had been switched, it is now switched to the "downshifted" or "O" state. Switching the core induces a signal voltage in the SENSE line.

The SHIFT, SHIFT DOWN, OBSTACLE and SENSE lines go through either the magnetic cores through or past them, depending on the logical operation being performed shall be. It goes without saying that these lines only act on or are only used by those cores Affects nuclei through which they pass.

The term core null decoder denotes aptly the magnetic component described above, if this is more logical to carry out Operations is used. This is true because once the magnetic component for its circuit from one retentive state to its opposite retentive state the absence of Requires current pulses on all variable obstructing lines, and secondly, the device itself behaves like an AND circuit when its input variables be reversed.

The same SENSE line can be threaded through several core null decoders and is operative as an OR circuit or mixer for the output signals derived from the cores. To this Way, a group of cores and a single measurement can be used to create a logical Realize equation of the following form:

5 = A ₁ A _x A ₉ ... An + B ₁ B ₁ Bt ... B _n

.-... "· ■ ^:. ■■■■■■ '■ · + ..- + C ₁ C _x C ₃ ... Cn.

An important feature of this magnetic logic technique is the extensive fan-in and fan-out option it offers. So z. B. an input OBSTRUCTION line or an output SENSE line without further threaded through several hundred core zero decoders in series. On the other hand you can through a single core null decoder, approximately one hundred OBLEMENT or SENSE lines or a combination of these lines. The result is that proportionate simple AND and OR circuits are available, which one by at least an order of magnitude can process a larger number of input variables than usual. Same relative Extension applies to the »fan-outo configuration.

Several SENSE lines can pass through one and the same core zero decoder to to generate a word as often as a core switches to the switched state and back to its switched back state State is switched, as is the case with a fixed memory.

To better understand the binary addition with simultaneous carryover to derive the addition formulas should be considered in detail now, ίο from the truth table for a single-digit full-adder is obtained Boolean expressions for the sum and the carry for this stage, ie Si and

S _t = AtBiCi + A ₁ BtCt + ItBtCi + AtBtCt (1) + AtBtC ₁ + A ₁ BtCt + A ₁ BtCt (2)

Here At and Bi are the / -th expressions of the summands, while Ci is the carry into the Me adder. Equations (1) and (2) can be reduced to the most favorable form for this discussion by simple logical operations. "+" Here means "including-OR" and "©" here means "exclusively-OR"

_a5 St = Αι® Bi®Ct \ (3)

Ci ₊₁ = (At ® B ₁ ) Ci ® AiBi (4a)

Ci ₊₁ = (At © Bi) C ₁ + AtBt (4b)

Two new variables Rt and Kt may be defined as follows:

Ri = At® Bt (S)

Ki = AtBi (6)

The equations (3), (4a) and (4b) can now be rewritten as follows:

St = Ri® Ci (7)

Ci ₊₁ = ÄiCj © ä: <(8 a)

C ₊₁ = RiCi + Ki (8b)

40 When choosing the limits to be determined for the summand expressions, the problems of both subtraction and addition must be taken into account.

With the limits given below, it is possible to "mathematically" introduce a carry into the lowest stage of the adder using the expressions A ₀ and B ₀ , which were specially introduced for this purpose:

50 = Bi = O for 1 φ 0.1, 2, ... , - η (9) = Bt for 1 = 0 (10)

By iteratively solving equation (8 a) one obtains a group of independent equations with only one logic level (single logic-level equations) for the carry expressions:

C ₁ = K ₀

Cj = K ₀ R ₁ ® K ₁

Cj = K ₀ R ₁ R _x @ K ₁ R _x @ K _x Ct = K ₀ R ₁ R _x ... Äi-i θ K ₁ R _x R ₃ ... /?, -, ©

♦ ■

•. ■

(Ha)

C _{n + 1} - K ₀ R ₁ R ₂ ... R _n © K ₁ R ₂ R ₃ ... R _n C \) ... © K _n -, Ä „(ι) K _n

F 3hl a group of simultaneous equations is obtained by the iterative solution of equation (8b), whose ■ general form is the following:

d = K ₀ R ₁ R ₂ ... Äi-x + K ₁ R ₂ R ₃ ... Ri-x + ... + Ki-x (lib)

After that it is now relatively easy to find the set of equations identified in equation (Ha) to convert to an equivalent expression in binary matrix notation:

C ₁ - 1 c. * Rx C ₃ RxR ₂ C, R ₁ R ₂ * * c » R ₁ R ₂ Cn + t R ₁ R ₂

Rn-x

Equation (12) can also be represented in abbreviated form as:

O Rn-χ O O O O 1 Marg O O O O R ₂ 1 O O O R ₂ R ₃ * 3 1 O O * ■ • * * * R ₂ R ₃ ■ .. * *, 1 O RnR. * Marg 1

K ₁ K ₂

K _n

Here the vectors are like single-row or single-column Matrices are dealt with while the matrix is multiplication and addition in the usual way be performed.

This matrix notation is very useful because 30 (6) and (7) are listed: the addition equations in this form and the

Mode of operation of the arithmetic to be described later Unity correspond directly. To complete the group, the following are equivalents Matrix expressions for equations (5), d '

Il Αχ - B ₁ A ₂ B ₂ R ₃ A ₃ B ₃ * Θ * * * * ΛΒ-1 A _n -X Βη-χ Marg A _n B _n

or ] = [/ 1 ₍₁ ] ®. [^ ₁ J for / -1, 2,

and

K ₀ A ₀ Κχ Αχ K ₂ A ₂ * * ♦ * Kn-i To — χ K _n A _n

1 1 1

B ₀ B ₁ B ₂

B _n

and similarly for the sum

Sx ----- A ₁ C ^ C ₁ S ₂ R ₁ C ₂ S ₃ R ₃ C ₃ * ♦ * * ♦ S _n Marg C _n Sn I ι O \ »I U.

or [> V ,, '■■■■ j - \ r _u J fo _r ·

1.2,

The last equation to be introduced here is the one to determine the integer Size (integer magnitude) of a binary number given in its vector representation or vice versa:

Γ .V ₁₁ 1

¹ for / = 1,2, ... η, η + 1
(20)

In deriving the addition equations, an alternative form for the transfer equations was developed which uses an inclusive-OR sign between the decoder expressions. While the exclusive-OR form (Ha) is to be preferred for the conversion to the matrix notation, the inclusive-OR form (lib) makes it easier to imagine the components required for the circuit implementation of the technology. As can be easily checked, only one decoder expression in (Ha) or (Hb) can ever be satisfied as a consequence of the special definition for Ri and Ki :

RiKi = 0 '(21)

Therefore, both the inclusive-or and the exclusive-or signs would produce the same result to lead.

So far the equations for true parallel addition have been derived. To these equations to be able to convert into circuits and perform the necessary arithmetic operation, find two special groups of memory-like registers use. These groups are described below Called data or matrix register. Arithmetic operations are performed as soon as data are transferred in parallel between registers belonging to the two groups. Every register performs a single logical operation as soon as there is information on its input channels, however only if it is in the set state. The results of this operation are shown in stored in the register until a reset command is received from the control logic. At this time the elements of the register are emptied and the information becomes available for the input channels of registers made available in the other group.

The one carried out during a transfer period particular operation depends on which registers are being set or reset at the same time. The way in which a register is wired also determines the function it performs. It is possible to have a complete and rather complicated code with relatively few develop separate registers and transmission channels. Commands are controlled as a series Transfers carried out between these registers.

Before actually considering the algorithm of parallel addition, it seems advisable to explain what is meant by data and matrix registers.

The data registers are roughly analogous to the flip-flop register gate circuits, as found in conventional arithmetic units. Only a few can manage the individual levels of this register Record input variable. They are thus in sharp contrast to the components of the hollow register, which are designed to accommodate a large number of inputs. Execute the data registers only relatively simple operations with corresponding printouts of two parallel information channels, which are arbitrarily designated as A and B channels. Such operations can e.g. B. the logical AND, exclusive OR or the identity function. Information can be obtained from a period of many clock pulses can be stored undisturbed in data registers. If the Information is emptied from these registers, the registers provide output signals which prevent current drivers trigger, which in turn provide the input signals for the matrix register. The inputs to the data registers come from the sense amplifiers on the output side of the matrix register and thus close a ring for the transmission of information between the data and matrix registers.

Matrix registers are not limited to the simple handling of a single vector or to an operation limited between corresponding elements of two vectors, as is the case with the data registers

ao is. The matrix registers can accept many KEM zero decoders use and can perform complex logical operations according to the invention that can be expressed in the form of a logical level. A logical level is defined. as an AND

a5 Operation followed by a logical OR operation. - The lines for the input variables of the matrix registers come from the data registers. In Fig. Figure 2 is, in block form, a fully parallel approach made possible by the present invention binary addition shown. The blocks symbolize either data or matrix registers, and the transmission lines represent the flow of data between the registers. Those within the blocks equations indicate the operation or operations performed by the block in question information stored in it. The function performed by each of the various registers is the following:

DÄ data register = exclusive OR between the corresponding bits of two information input channels. The equivalent matrix notation for this Operation represents equation (15)..

D / sT data register = a logical AND between the corresponding bits of two information input channels. In this case the equivalent arises Matrix notation in equation (17).

MA 1 matrix register = receives and buffers the information present on the input transmission channel from the Z) A register after receiving a SWITCH command from the control logic. The notation for this operation is simple

MB 1 matrix register = receives, decodes and buffers the information from the DR and DAT data registers on the two transmission channels during the switched period. When the MÄ1 register is switched back, these decoder cores are emptied and their outputs are mixed by sense lines as required.

The resulting simultaneous carry vector is passed to the data registers over the "B" transfer channel. The equivalent matrix notation for this operation is given in equations (12) or (13). The most important building element of this. Register group and the key element of the arithmetic operation is the MBl-

R is: cr. _{d R.} the register for the simultaneous

The matrix equation (12) for the Concurrent carry expressions considered. Any non-zero member in the matrix

can be represented by one of the right ones & -Hinder lines crisscrossed · core zero decodicrcr. It is recalled in this connection that coincidence decoders invert input signals require. 325 such cores are necessary for 24 input variables. The matrix multiplication process is now made by pulling the / G-i blocking line through all of the Structure in the / -tea column of the matrix corresponding cores completed. Separate sensing lines, which correspond to the simultaneous carry expressions penetrate the core corresponding to the Outline in each individual row of the matrix. An inclusive-OR operation is performed at the outputs of the cores for each row performed as equation (lib) allows. All 325 cores are made by the same SET and RESET control lines crisscrossed.

This makes it clear why the matrix register bears this name. Its mode of operation is similar to matrix algebra, which it effectively embodies. As a comparison with the effect of a single core zero decoder described above and with regard to the example chosen for the purpose of explanation, two channels of input inhibition lines comprising 25 lines are in each case at time T _1, corresponding to the binary vectors of the half-addicr sum and the half-adder. Carry and also energized the common switching line. Accordingly, a total of 25 core zero decoders could be fulfilled and thus brought into the »/ th state. At time 7 ", the reset line is energized, which then resets all of the previously switched cores to the original" (! ") State, and the vector expressions of the simultaneous carry appear in parallel on the 25 sense lines of the output channel.

On the other hand, the implementation of the carry vector is illustrated by considering the Set of simultaneous equations as obtained from the iterative solution of equation (8b) and whose general form is derived from equation (lib), i.e.

a parallel half-add sum and a half-add carry are formed. This is done taking into account the two results of the first Step generates the number of simultaneous carry.

Finally, the half-adding sum of the summands is again half-added to the number of the simultaneous carry, forming the algebraic sum of the original summands.
According to FIG. 2 does the addition in detail how

ίο follows in front of you. Assume that the one through the vector. ,

• ■ Κ]

was left in the DR data register at the end of any previous instruction while the other summand

is stored at a specific location in the data memory. The addition of these two numbers can be carried out during two clock cycles, with each clock having two phases, namely phase A and phase

As phase B has / in other words, the operation to be described is carried out in four transmission periods.

During the phased of clock cycle 1, the DÄ data register is reset and the matrix register MA 1, which buffers the DÄ register, is set. The / li information is transferred to the MA 1 matrix register, with "L" s remaining in the £> /? Register. During the same period, a. The core corresponding to the memory address of the summand expressions (to be increased) is set in preparation for reading out during the next transmission period. In phase B of clock cycle 1, the MA 1 matrix register, which contains the / ij expressions, and the data memory address for the 5j expressions are simultaneously emptied or reset, and information is transferred back into two data registers DK and DR, respectively. Expression for expression, the DK register carries out a logical product or AND function with the Ai and Bi expressions and thereby generates the vector of the AT function. The Z) /? Register carries out an exclusive-OR or modulo-2 addition operation on the summand expression for expression, which then results in the vector of the /? Function. So:

■

55

+ K ₁ R ₁ R ₂ R ₃ ... R ^ ₁ + ... + Ki- ,.

Each term on the right-hand side of the equal sign is represented by a core zero decoder through which drive lines from the DK and ΟΛ data registers are drawn as required. The logical OR of the decoding clocks in each group of equations is thereby reduced. that the same sense lead is drawn through all of the cores which represent expressions in the relevant illustration for C ₁ . This requires as many obstructed sensing lines as there are Ubemags-AiiHJrücke.

Uic addition is by means of the various registers attainable by the fact that from the summands, in practice, that would produce the i-expressions Register likely to be the same register as that in which the ^ «expressions originally came were stored. The function of the D /? Register is very similar to the function of the accumulator register in a traditional arithmetic unit (arithmetic unit).

During phase W of clock cycle 2, the DK or the /? Data register is reset, while the Λ / 1 matrix register, which carries out a simultaneous transfer to the R and / ^ expressions, is set as well as MA 1 , the matrix

Buffer register for the Äi expressions. This can be show as

During phase B of clock cycle 2, both the A / 51 carry matrix register and the MA 1 buffer matrix register are reset, while the DÄ data register, which performs an exclusive OR operation on the two information channels fed to it, is set will. The result, which appears in the DÄ data register, the accumulator, is the sum or the Sj-expressions, and the execution of the addition instructions is done. In the abbreviated matrix notation this is:

As already mentioned above, the data register DR, which originally contained the addend (to be added) or the / 4 <expressions and which as carries out the exclusive-OR operation with the summand expressions in order to obtain Rt , and which later the Exclusive OR on the Rr and Ci expressions to obtain the expressions of the sum St , be one and the same register.

Therefore, if you consider the time required, the addition instruction requires two double-phase ones Clock periods or, assuming a 100 kHz clock, 20 μβ to completion. The entire command process requires access to memory and overflow control about 30 μβ. As equipment for circuit-like The addition process is implemented using two data registers, one of which is an exclusive OR function and the other is performing a logical AND function, and two matrix registers are required, one of which buffers a data register and the other takes care of the simultaneous carry.

F i g. 3 shows a block diagram of a corresponding arithmetic unit. This diagram illustrates the two data registers DR and DK and the two matrix registers MA 1 and MB1 and the four transmission channels which are all used in the addition process described.

In addition, however, two further data registers DM and DN and two matrix registers MA 2 and MB1 are also suitable. The functions of these registers are as follows:

Z) A / data register - receives and buffers the from information received on an input channel and, when reset, provides a type of feedback readout.

60

j Mr ₁ I = \ At ₁ j originally
M't! - Mti j feedback return.

This register was used to store the multiplicand designed during multiplication. ·

D / V data register - receives and buffers the from information received on an input channel and, when reset, provides feedback with a shift one place to the right.

I N ₁₁ = J AiA originally

Γ jV'tj J = IW ₊₁₁₁ I feedback reset.

MA 2 matrix register - receives and buffers the product of the vector present on the input transmission channel from the DM data register and the element with the lowest order of the vector present on the transmission channel from the JV data register. The equation for this operation is:

A / £ 2 matrix register - receives and buffers the information present on the input transmission channel from the DR register, but shifted one place to the right. So:

The registers DM, DN, MAl and MBl come into play in the multiplication and will be considered in detail below.

Returning once more to the addition process described above, F i g. 4 a a schematic diagram, which is based on the F i g. 2 and 3 and the wiring of the core zero decoder and the connections between the data and matrix registers for one example four digit adder shows. The following description of FIG. 4 with the circuit-like Formation of the invention. However, in describing the invention, they are in context with the F i g. 2 and 3, similar designations and reference numerals are used for the components and this description applies equally well to FIG. 4 to.

In Fig. 4, 14 core zero decoders 10-23 are shown, each of which is shown as a narrow rectangular band. Cores 10-19 form the Mßl carry matrix register. The data registers DK and DR are shown as functional blocks. It should be noted that the function of the data registers, namely, the generation of the reverse AND and the reverse exclusive OR, can be performed by a number of either electronic or mechanical means and that this invention is not intended to be limited to any particular means. For example, certain basic magnetic logic components such as B. NOT, Exclusive-OR and AND, which are applicable to the DR and DAT registers of this invention, in Chapter 10, pp. 161 to 166 in the publication "Digital Application of Magnetic Devices", edited by Albert J. Meyer hoff et al. ...

The output signals of the data register trigger the hindrance driver ID, which supplies the bundle of input lines which terminate at a supply voltage source V with the input signals. The oblique line at the junction of a core with a lead indicates that the lead in question passes through the core. The direction of the slope of the stroke with respect to

d «Siren» on the line indicates the direction in "Tlchef who" leads through.

DcTSteucn.gnalgcneratorSO carries out the control log

and ran ate "iiliche control for the arithmetic operation. The signals from the control generator actuate suitable current drivers SD and / M) which deliver current impulses in one direction so that individual core groups connected to the MA 1 and MBI controller are set and that all cores are also set back. The respective setting or resetting of the DR and £> AT registers is done under the control of the signal generator. In addition, if required by the control logic, the generator activates the hindrance driver connected to line K _0.

An output signal derived from the reset of each core induces a voltage in the sense lines inductively coupled therewith. It should be noted that in the case of the carry Matrizenregistcrs MBl pass multiple sense lines by more than one core, and thereby serve as an OR gate or mixer for those derived from the nuclei of output signals. When a sense lead passes through more than one core, its winding direction is reversed for successive cores, thereby providing some degree of noise suppression during the read or reset process of the cores.

The output of each individual sense line is connected to a sense amplifier. The sense amplifiers connected to the MA 1 register form the information channel "A" and those connected to the MBl register form channel "B". From these channels the information is fed to corresponding parts of the DR and £># registers, thereby closing the loop.

The wiring technology of the core zero decoder is clear from the representation of the ΛΛβΙ register in F ί g. 4 emerges. The equations for the simultaneous carry terms are of the general one Form as given in (11 a) or (lib), and are shown in equation (12) in binary matrix notation. The equations for the first four Transfer expressions are based on the form (Ub): '

C ₁ = K ₀

Ct = K ₀ R ₁ + K ₁

C _t = K ₀ R ₁ R ₁ + K ₁ R ₁ + K ₁ (Hb ')

C ₄ = K ₀ R ₁ R ₁ R ₃ + K ₁ R ₁ R ₃ + K ₂ R ₃ + K ₃

However, taking into account that the anti-coincidence decoders as described above require inverted input signals, it is more convenient, and perhaps better understood, to look at these decoders as if they were ordinary coincidence decoders in the description that follows. In practice, the core zero decoders actually need inverted signals on the bmgjngs-hinderungsLleitung, such as e.g. B. IT ₁ , F ₁ or

u . «. ^etc. - ^Ebe "so the data registers are written as if they generated the function itself and not the inverse function, although in practice the latter is required.

F-.s now follows the consideration of the first carry expression C ₁ in the equation (H b ') developed above from (lib). The _eS c equation has on the right

Page only one expression, namely AT ₀ . As mentioned earlier, each term on the right hand side of the equation is represented by a kernel zero decoder. The core 10 represents this single expression ajjf of the right-hand side of the equation, and the line K ₀ , which originates from the control signal generator 50 and runs via a hindrance driver, penetrates the core 10 in the direction that a current passed through it resets the core. This of course applies to everyone

ίο other obstruction lines running through the cores go through, alike.

The second carry term C ₂ has two terms, each represented by the kernels 11 and 12, on the right-hand side. The first expression ^ / ?, is realized in that the lines K ₀ and A ₁ pass through the "core 11. The expression K ₁ appears where the line K ₁ passes through the core 12. A common, the carry-over expression C ₂ corresponding sensing line 31 goes

so through cores 11 and 12, thereby providing the inclusive-OR operation on the outputs of these decoder expressions. Examination of the equation for C ₃ shows that each term on the right hand side of the equation is in circuitry as follows

as is realized: '

K ₀ R ₁ R ₁ - core 13 is penetrated by K ₀ , R ₁ and

R ₁ ■; ■. ■ _ ■ - _ ..

K ₁ R ₁ - core 14 is penetrated by K ₁ and R ₁

K ₁ - core 15 is penetrated by K _x

C ₄ is implemented in a similar way in terms of circuitry:

K ₀ R ₁ R ₁ R ₃ - Decoder_rerkern 16 is penetrated by. K ₀ , R ₁ , R ₁ , R ₃ ,

K ₁ R ₁ R ₃ - the decoder core 17 is penetrated by K ₁ , A ₁ , A ₃

K ₁ R ₃ - the core 18 is penetrated by K ₁ , R ₃ * ° and

K ₃ - the core 19 is penetrated by K ₃ .

The carry expressions appear accordingly as the signal outputs of the sense lines 30, 31, 32 and 33. The sense signals drive sense amplifiers 40, 41, 42 and 43, the outputs of which are the vector expressions B ₁ , B ₁ , B ₃ and fed to the two data registers DK and DR S ₄ will be.

The wiring of the register MA 1 is similar to that of MBl, but it is somewhat simpler because every expression R ₁ , A ₁ , A ₃ and A _{4 of} the register DR is buffered in it and each of these inhibiting lines is a core of the register MA 1

penetrates. Lines / T ₁ through ίΓ ₄ thus penetrate cores 20 through 23. The outputs of these latter cores are sensed by sense lines 34, 35, 36 and 37 which drive sense amplifiers 44, 45, 46 and 47. The outputs of this last group of sense amplifiers are the vector expressions A ₁ to A ₄ fed to the registers DR and DK .

The F i g. 5 has the same form as the block diagram of FIG. 2 shown method 1 of the addition process. The F i g. 5 shows the addition of two binary numbers, namely 0 / -LO and 0Λ0 /., With the aim of forming the sum LOLL and / cigt the type of information as it is in the various registers during different phases of the

17 18

Operation cycles is stored. The following loading sets cores 20 and 21 in the MA 1 register. the

Writing should also refer to the general, already at this point in time stored in the MA 1 register.

above with the help of FIG. 2 is QOLL, and in MBi is LOOO

operation related. saved.

Taking into account the F i g. 4 and 5 completes 5 clock cycle 2, phase B - on the control command

the addition of the two binary numbers 0 £ L0 and the control generator 50 are MA 1 and MBl

OLOL as follows: reset. The information is on the

Clock cycle 1, phase A - it is assumed that the "A" channel of MAl is now A ₁ = L, A ₂ = L, A ₃ = 0, that all cores 10 to 23 are originally in A ₁ = 0; and on channel "B" of MBl there is: reset status. It should also be noted that 10 B ₁ = 0, B ₂ = 0, B ₃ - 0, B _x = L. This information assumes that the summand (which is added) is at the same time the register DA, which is determined by the (Addend) , namely the binary number OLLO, which is set in the control generator. The ReRegister DR is stored and that the (to be vergisterDÄ performs an exclusive OR with the multiple) summand (Augend) OLOL in the data information from channels A and B, and that is stored in the memory. The control signal generator 50 15 result in DR is LOLL, which is the sum of the actuates the reset driver DR, which represents the data-original summand. This reads the register DR. With further consideration the addition process ended.

Anticoincidence decoding is intended for the purpose of FIG. 6 shows a diagram of the multiplication of the explanation, assuming that the reading process using the above-described adding or resetting of the register DK or DR, an Ausao tion arrangement according to method I is shown. The drawing signal from all of the register parts shows what is actually a point in time in the middle of a "0" store and no perceptible span multiplication process and not its beginning output from the parts storing "L" s. or end. It is assumed that the digits-Simultaneously the signal generator pulses the shifted partial product sum in the matrix driver for MA 1. Reading out the register MB1 stored in DR and that the prepared multiplicand _: th information activates the hindrance driver for which which is to be added to this sum, in ■> ■ lines Tf ₁ and R _x . The lines R _{2 and} R ₃ remain stored in the matrix register MAl. While at rest. Under these conditions, a phase B of the clock cycle under consideration prevents the flow of current in the lines A, and R _x the setting of the matrix registers MAl and MBl and cores 20 and 23. Only cores 21 and 22 of the matrix 30 conduct information about the Channels A and B, which zenregisters MA 1 are set. then brought into the data registers DK and DR

Clock cycle 1, phase B - the control signal - is where the logic product and the exclusive generator operates then the reset driver for MA1 OR corresponding expressions are derived, and also causes the (to be increased) during phase A of the next clock addend the data memory is read out. 35 cycle, the two data registers are reset, the cores 21 and 22 are switched to the reset 'and the carry matrix register MBl and the Z) A state and induce voltage-buffering matrix registers MA 1 are set in the sensing lines 35 and 36. These Voltages During phase B of this clock cycle, the matrix registers MA 1 and MB 1 are in turn reset by sense amplifiers 45 and 46 , transferred as A ₂ and A ₃ into the registers DR and DK . 40 and the exclusive OR or the sum is derived in the absence of switching signals from the cores 20 to the data register DR ,
and 23 the lines A ₁ and A _x remain idle. In phase A of the third clock expression Bi from the memory and the expressions / transmitter cycle, the data register DR, which contains the expressions St from register MA1 at the same time, is reset, and the information ( , ' read into "register DR and DK. the register DK mation 45 illustrate shifted to the left and performs a logical aND, so that from it overall a Matrizenregister MBl buffered. is the same stored information OLOO, and the register time, the multiplicand Data register DM - this DR performs an exclusive OR and stores a new 00LL, which is required for the multiplication. Data register - as well as the multiplier-:

Clock cycle 2, phase A - the control signal 50 data register DN emptied, and a special measure \

generator causes DK to be reset and DA trizen register MAl is set. This register

and simultaneously delivers to all core zero decoders forming a logical product of the lowest;

a set signal from MAl and MBl. _A. In this way positionJV ₁ (least significant bit) of the multiplier

become the hindrance lines "R ₁ , K ₂ , K ₄ and R ₃ , R _x and all terms Mt of the multiplicand. The

actuated. The inhibition line K ₀ is also 55 Result is that the next word, which is to the

operated by the control signal generator. In practice the partial product sum is added, a 0 is when

K _{0 is} always during this phase of the addition- the multiplier digit is 0 or equal to

activated. In the case of subtraction, however, the multiplicand is if the multiplier digit is a '

is the one's complement of the subtrahend to the minus L. The last two registers are marked with -

ends added up, with the AO line not activated 60 dashed lines shown as they are

is, which has the consequence that a carry into the lowest by the same matrix register MA1 and MBl

Adding stage is introduced, as negotiated in one of which at the beginning of this operation

guided embodiment of the invention applied- was discussed. The result of these actions

requires two's complement arithmetic. Below is an addition and a digits shift

under these circumstances, of course, only one core 65 will be performed at any two clock periods

set in the Λ / A1 register, namely the carry and that the multiplication of 24-digit numbers

kernel 19. All other kernels in the register remain (including sign bits) for 46 clock periods

then in the reset state. It is also finished, plus additional bars for the

jcs sign as well as for setting ^u , sign at the end of the multi

A block diagram of an arithmetic unit for carrying out the operations of the present invention differs from the method described above. 7 and the addition via Muluplikätionsdiagramme of Figures 8 and 9 UR * J ir.ii .A method 11 ", respectively. The (Jbertrags-Mair * cnrcg: s; cr MBi of method I is replaced here by a desire MB3 , in which the final sumir.e is retrieved by means of an inclusive-OR operation, with the sensing lines being used as a mixer in the celebrating manner will:

5 «= RiCi + RiCi,

if Ct is defined by equation (lib) and Ct is given by:

C ", » K ₉ R ₉ R ₁ Ri - Ri-i

-f K ₁ R ₁ RtR ₃ -Rt-I + ... + AJ-jäV-i.

This operation requires twice the number of Kem zero decoders as in the carry matrix type A / 51 of method I and also the parts Xi and Ri of the data registers DK and DR, which are not used at all in the operation according to method I. The advantage of the operations according to method II is that additions can be carried out at the rate of one addition per cycle. But that means a significant increase in the speed of multiplication.

Referring to FIG. 8 the following details of the addition process are to be recorded. The terms of the summand (which is added) are originally located in the data register DR. In phase A of the clock cycle 1, the data register DR is reset and the matrix buffer register MAl is set. At the same time, the expressions Bi of the summand (to be multiplied) are addressed in the data memory. During phase B of the first clock cycle, the load register MA 1 and the data storage location B _{1 are} emptied. When the information appears on the channels, the data registers DA and DR, which comprise the data parts Kt and Rt , are set. The last two parts of the register /) /? are necessary to generate the sum in the matrix register by this special operation. _t

During phase A of the second clock cycle, the data registers DR and DK are emptied, and the sum is formed in the matrix register MB 3. The concurrent carry equations Ct are only a function of the R and K terms, while the Q equations require R, TJ, A, and K terms. During phase B of the second clock cycle, the sum St from the matrix registers is brought into the data register R.

In the multiplication operation according to method II α \? "^ - ^W ' ^rc *' ^{when you} turn in the middle

The ^{ultimate plan} process begins, the partial product sum is stored in the matrix register MAl and the new summand MtN ₁ (to be increased) is stored in the matnzenregister MB3. During the phase of this clock cycle, these two matrix registers are emptied and the data registers Dtf and DR including their parts Kt and Rt are set.

During phase A of the next clock cycle, these data registers are emptied and a sum matrix register MB3, which is correctly shifted, as indicated by the index / -1, is set. At the same time, the lowest digit N _{1 of} the multiplier data registers DN and Mt or the multiplicand register DM is emptied, and

ίο the new summand MiN ₁ , which is added to the partial product sum, is generated in the matrix register MAl. The dashed lines indicate that these latter registers are the same as the original matrix registers MA 2 and MB3 . This multiplication scheme performs an addition every clock cycle. Depending on the requirements, additional clock cycles for adjusting the sign and forming the complement of the final product must be estimated.

ao The scheme also requires two sense amplifier channels, as in Method I, which are both unipolar, makes two new parts for the data registers DR and DK and their hindrance drivers, and twice the number of cores to carry out the

The simultaneous carry over function is required. On the other hand, the multiplication using method II is roughly twice as fast as that using method I.
Figures 10, 11 and 12 illustrate, in block form, another variation of arithmetic operations utilizing the magnetic techniques of the present invention. This variation is designated Method III. In the system arrangement of FIG. 10, a new matrix register identified as MBA has been introduced. This register forms the sum St as a function of an exclusive OR operation which is carried out with the Ct and / {(expressions.

The addition process according to method III, as shown in FIG. 11 requires far fewer components than Method II and is just as fast as this. The peculiarity of this method stems from the circuit-wise use of bipolar sense amplifiers. This enables a simple exclusive OR to be performed between two cores in the matrix register. In particular, as a result of the definition of Rt and Kt, only one kernel can be set at a time in a single equation of the simultaneous carry. If now other kernels buffering the Ai expressions have been set and the sense line includes all decoder kernels for the equation C "> of the carry-of-ten from one direction, e.g. B. penetrates from the left, while it penetrates the Ä _l0 core from the right, then an exclusive OR is obtained in that if either both cores are set or no core is set, the sensing line carries a pure zero signal and the Sense amplifier provides an "O" output. If, on the other hand, the / {“core and none

If the C, ₀ core is set, or if, on the other hand, one of the C ₁₀ cores is set and the Ä _{1 #} core is not set, the sensing amplifier delivers a "!" Output.

In detail, the addition process proceeds as follows: Originally the summand At (which is added) is in the data register DA, and the summand (to be increased) is in the memory. During phase Λ of the first clock generator

cycle the data register is emptied and the information is buffered in the matrix register MA 1. The data memory is activated at the same time. During phase B of the first clock cycle, both the buffer matrix register MA 1 and the data memory are emptied. While the information is now coming down the two channels, the data registers DK and DR are set and carry out the simple logical operations with the information presented.

During phase A of the second clock cycle, the data registers DK and DR are emptied and a sum matrix register MB4, which is represented by the block in which St = Ct -j- Rt , is set. In phase B of the second clock cycle, this matrix register is emptied and the sum is transferred from the matrix register to the data register DR , where it is used essentially to perform an exclusive OR operation with respect to zeros, which come down the other channel, which is easy entails an identity storage function. While this addition method still requires four transmission periods, no time is lost, since in a practical system at least four transmission periods are required for successive accesses to the data and instruction memory. The advantages of the techniques according to Method III are clearly evident when multiplying.

F i g. 12 graphically represents the multiplication process according to method III. If you start again in the middle of the calculation process, the position-shifted partial product sum is stored in the matrix register MB4 and the next summand (to be increased) is stored in the matrix register MA1. During the. During phase B of this clock cycle, both matrix registers are emptied and the information flows down channels A and B and into data registers DK and DR where the simple logical product and the logical exclusive OR are formed.

In phase A of the next clock cycle, the data registers DK and DR are emptied and the sum is formed in a matrix register MB 4 , specifically shifted in correct places, as indicated by the index "il". At the same time, the data register DM for the multiplicand Mt and the lowest digit N _{1 of} the multiplier data register DN are emptied, and the next summand (to be increased) for the sum of the partial products is formed in MAl . These blocks are shown in dashed lines because they are identical to the original matrix registers MAI and MBA at the start of the operation.

An addition and a shift process are carried out in this arrangement for two transmission periods or for 10 \ l% at a clock frequency of 100 kHz, and a full multiplication can be performed in 24 clock cycles plus additional cycles for adjusting the sign and testing at the beginning and end surgery to be performed. Method III is therefore very fast for logical operations and uses relatively few components. It should also be noted that in this case the parts Kt or Rt of the data registers DK and DR are not required, as was still the case with the very fast addition and multiplication according to method II.

Accordingly, the matrix register MBA only needs half as many cores as the sum matrix register MBT) in method II.

The above description of the invention and its embodiment in arithmetic by way of example Systems show that the inventive techniques are very good at performing complex logic Functions are suitable. Storage devices other than magnetic cores may be used can be used with advantage in the practical embodiment of the invention without deviating from the inventive concept.

Claims (2)

Patent claims: 1. Circuit arrangement for parallel generation a carry result (C) consisting of several bits (C <) after the function - K ₀ R ₂ -f- Aj in a parallel adder, where Rt is the result of the exclusive OR operation of those operand bits (At, Bt) for which the carry bit Ci is generated, Kt is the result of the AND operation of the end bit At and the addend bit Bi and K ₀ one bit which is fed to the adder from the next lower parallel adder stage, and where the sign "+" signifies the inclusive OR function and the sign "·" signifies the AND link, characterized in that a first number of AND elements (DK) are provided each of which receives at its input terminals a bit (Bt) of the addend (B) and a bit (At) of the end (A) that the output terminals of the parallel exclusive-OR gates of the parallel adder (DR) and the AND- Members (DK) are connected to a second number of AND members (MBl; eg 10), one of these latter AND members for each expression of the equation \ ~ t - Aq * Aj / \ j. . . / Vj - | ~ t ~ Äj · R ₂ · /? 3 ... Rt-i - \ - ... - \ - Kt - i is provided and connected with its input terminals to the output of those stages of the parallel adder (DR) and to the output of those AND gates (DK) whose corresponding bits (K, R) are contained in the expression concerned, and that the outputs of each of the A second number of AND elements (MB1; e.g. 10) for each equation are connected to the input terminals of an inclusive-OR element (e.g. 30 to 33 in FIG. 4), each of these inclusive-OR -Glieder on its output terminal that. provides the corresponding bit (Ci) of the carry result (C) for the parallel adder. 2. Circuit arrangement according to claim 1, characterized in that each of the second number of AND gates (MBl) has a magnetic element (F i g. 4 z. B. 10, 11, 12, 13 ....) with a substantially rectangular Has a hysteresis loop through which a combination of conductors (cf. in FIG. 1: B ₁ , B ₁ , ... B _n , switch-back line, switching line, sensing line) passes, some of which (Ri) with different