DE1297650B - Data transmission method for error detection - Google Patents

Description

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The invention relates to data transmission methods, separation steps and generation of a parity bit in which an error is recognized in a receiving station, which is compared with the received parity recognition in the received via a forward channel. According to the catch incoming signals accompanied by redundant test information at the same time via the back Useful information takes place and is transmitted back to the transmitting station via a reverse channel, where forward channel test or repeat request - they compared with the original signals Signals are transmitted back to the transmitting station. will.

Such systems are e.g. B. known from the Will in the returned signals

German Auslegeschriften 1170 460 and 1171463. If errors are discovered, the original signals are used

According to the invention, in such a io are retransmitted. However, it is possible that a

Data transmission method means provided to avoid errors in the normal transmission direction

in the event of an error being detected in the case of an error occurring in the reverse channel,

transmission of signals to the receiving station is compensated. Although in such a case the

additional error in the receiving station back to the sending station detects an error and how it

to introduce transmitted signals. 15 is the case with many systems, in a certain way

The invention can be used in systems, for example by deleting the erroneous signals

find where the receiving station from the output - could respond to it

incoming signals not only forms check bits, it is thus possible that the transmitting station of the

but these received signals beyond the occurrence of such an error are not "informed"

20 returns to the transmitting station via the reverse channel and the original signals are not repeated

transmitted. The latter contains storage and transmission. The result would be the defective

Retransmission devices to all-result signals in the forward channel in such a system

A comparison of the signals sent back can be lost.

with the data stored at the time of their transmission, however, any signal group in the

original signals recognized as faulty 35 receiving station recognized as faulty and to

To transmit signals again. Transmitting station with an additional, intentionally

The invention is characterized in that returned errors are returned, so the truth is

apart from the test signals, in a known manner, probability for a compensation or other

also the received information signals for the extensive non-detection of the double error in

Sending station are sent back where they are low in 30 of the sending station.

also known way with the meanwhile one of the simplest methods of production stored, originally sent information additional errors in the returned information be compared, and that means are provided, consists in reversing the polarity of the signals when an error is recognized at the receiving end, parity bits in the signal group that correspond to the original the information received over the forward channel contains 35 borrowed errors.

mation of this information before it is sent back could, however, especially with systems ment via the reverse channel through deliberate deletion of the through on the receiving side Introduction of a second error again to parity bit comparison information changes recognized as faulty, mations made in each case, correctly transmitted

In a particularly advantageous manner, useful information will be lost with such 40. This applies to the

Systems in which the test information is to be sent and in the event that the parity bit formed on the send side is used in the

is formed as a redundant check bit on the receiving end, transmission over the forward channel is falsified,

the object on which the invention is based d. H. is reversed while the useful information

solved by that in the useful information is transmitted instead of the direction.

originally sent parity bits that at 45 In this case, the transmitted and the

Error check on the receiving side determined parity bits generated on the receiving side do not match

the useful information transmitted back to the transmitting station, d. that is, the information would be "mistaken" as

mation is added. recognized incorrectly. As with the return

Method in which received information- the information according to the invention is the received signals sent back to the sending station by 50 parity bits received on the detection of a it with the meanwhile stored, originally error in its polarity reversed - d. H. so, To compare transmitted information, can be seen on the parity bit formed on the receiving side known, see, for example, the German interpretation set - will appear if the transmission is undisturbed writing 1036 308, column 1, paragraph 1. via the reverse channel on the sending side again

In the case of binary signals, one of the characters on the 55 is the correct character with the original, correct

The most common mistake is the inversion of a parity bit.

Drawing step element into a separating step element In the transmission system according to the invention or the other way around. In the case of a short group of elements, deletion of the data received on the receiving end (e.g. B. five elements) is the probability of stored information (a character) only then more than one such error is not very large, so 60 will be released when it is established that this that a simple method of recognition must be repeated for such characters. One of those The error consists in adding an additional element - the character must be repeatedly transmitted in itself which is known as the parity bit and its known way (preferably from a series State indicates whether the number of characters (or bits that are the same and therefore exist Separation) steps in the preceding elements - 65 distinctive and fail-safe) special group is odd or even. In the reception identifier are prefixed, at its empstation can the error z. B. by counting the detection on the catch side that was on the output Element group received characters (or the end character is first deleted; if the repeat

3 4

fetch identifier, it is a question of an incoming six-element group

new information, and the waiting character can be recognized (five information bits and one parity bit),

get to the output as error-free (although with so the element clock circuit encounters a par

Falsification of the parity bit, initially “erroneously” the rate clock circuit on; this is essentially

may have been identified as faulty). 5 an element counter with a total count of "6".

Conversely, when each 20 ms pulse is received, the borrowed case of the occurrence of two errors in the counter can be advanced one step, so that with the forward channel in this case the counter position is reached with pure parity "6" corresponds to this position of the test erroneously recognized as correct character by the time slot in which the parity bit for the return transmission to the transmitting station is still received Control signal that switches the output to the "!." State until the repetition flip-flop IF arrives, with an indicator to wait, which _{causes the deletion of the only output signal IZ 1.} During the supposedly correct character and the previous five time intervals are supplied by the flip-repeat transmission initiates.15 Flop IF an output signal If ₀ .

When using the during the operating time of the parity timer parity bits formed on the receiving side as an "additional error" in a system circuit, which would be via the forward channel according to the invention (as later clearly arriving signals are fed to the flip-flop 3 F, lighter is shown) a transmission of the send- Each received character step sets the flip-flop-side parity bits to the receiving side in principle 20 in the S state and generates an output signal 3 / _s , not necessary at all; it is nevertheless expedient because and accordingly, each separation step generates an error check on the receiving end, even if it is output signal3 / _m . Every time the flip-flop 3 F is not immediately evaluated for the transmission, an output signal 3 / _{s is} generated, this is sent to the, but important information about the over-parity counter flip-flop 2 F is supplied, namely the transmission quality of the Forward channel can deliver. 25 via two gate connections, which are also controlled by the

The invention will now be explained in more detail with reference to the single element clock circuit and the output figure. This shows schematically DIE 2Z signals ₁ and _2/0 mode, the invention essentially leads to the person you parts of a receiving station in which each ungleichnamigen inputs fed back to the expression. are. The flip-flop 2F is (by not shown

For the execution means described below) after each element group has been received

example, the use of one of a single is deferred. After receiving the first character

A five-step binary code step element of a group accompanied by a parity bit becomes the flip-flop 2F

assumed what groups of six binary- by the signal 3 / _s in connection with the EIe-

elements results. A parity bit "1" means a mente clock signal and the signal _2/0 in the

odd number of character steps switched in five-bit 35 "1" state. Every received

Code, while a parity bit "0" an odd character step element works the flip-flop

Indicates number of steps. once around; thus an output signal 2 Z _{1 shows} a

In the figure, the various conventionally odd number of character steps in the received

handy electronic components of the receiving station to NEN signal, and an output signal _2/0 a

represented by the usual symbols; so is z. B. 4 ° even number.

a gate circuit by a circle with one or during the counting of the character steps in several inputs and one output, parity counters are the received signals, which are represented by corresponding arrows. At least one for the first five bits, immediately after the Emp number in a circle, indicates the number of inputs that are sent back to the reverse channel. _{The output signal 3 / s} or 3 f _m for opening the gate circuit and generating 45 will be required via an output signal. A flip-speaking gate circuit to the regeneration flip-flop is supplied by two adjacent right-hand flop 4 F. These output signals are shown by 3 corners, one of which is arranged above the other after 4 F only during the first five reefs; the arrows indicate the one-element time cycles in which the control and outputs occur. Which is directly present for the formation of signal 50 signal If ₀ . When the sixth element-serving flip-flop occurs, the designation element-time clock disappears, the control signal If ₀ , voltages S and M, to the character or the separator with which the outputs of the flip-flop 3 F locked step state symbolize. Everyone else will. At the same time the control signal If _{1 appears} , flip-flops have the binary states "1" or "0" according to the state of the parity counter in. A counter is provided as a series of information 55 with either compound ₁ or 2 Z 2 / _0th If _{the signal If x appears} in the form of a number of bit memories at this time, the flip-flop sends bordering rectangles shown in a line that instead of the parity bit that accompanied the incoming elements at one end to an input and at the other end , a character step element to the back has an exit. The different in the figure backward channel.

The components shown not only interact with one another in a way that can still be described as the original parity bit, step, which an odd number of characters but also with other parts of the steps indicated in five-bit code, and there was no receiving station that errors are not part of the invention, the parity counter also supplies an odd number, which is therefore not shown in the drawing; the result is the tax level. So z. B. at the first detection of a 65 signal 2Z ₁ , which, as already explained, a character group of incoming elements transmits a clock step parity bit back to the transmitter, circuit is put into operation and generates element. If an element was received incorrectly, clock pulses in Intervals of 20 ms. the parity counter returns an even number of characters

steps and generates an output signal 2 / _? . The originally received character step parity bit is now replaced by a supplied by the flip-flop 4 F separation step. Thus, the six elements transmitted back to the transmitting station via the reverse channel contain not only the wrong element as received from the forward channel, but also an incorrect parity bit. When comparing the returned elements with the original elements on the send side, both the corrupted element and the parity bit produce an incorrect result. However, should one of these two elements be corrected during the transmission in the reverse channel due to any compensating error, an error still remains, which is recognized in the group transmitted back.

The parity bit received via the forward channel therefore does not become the Reverse channel is allowed through, it is in any case ao replaced (with which it corresponds if there are no errors). As a deletion or output of the received Character, as described above, only in the event of the arrival or absence of a repetition mark should take place before the next received character, a transmission of the transmission side would be formed parity bits to the receiving station per se is not absolutely necessary, but it is how also already noticed, expediently nevertheless carried out in order to provide important control options for the forward channel.

Compared to the known systems with pure parity comparison on the receiving side and repetition request in the event of a fault, the transmission system according to the invention has the advantage of Correction option for double errors in the forward channel and avoidance of unnecessary ones Repetitions if the parity bit is transmitted with interference and if the useful information has been transmitted correctly.

Compared with the known transmission systems with return transmission to the transmitting station and transmit-side element wise examination of the I, the proposed system has the \ compensation of the forward-K; An error in the reverse channel eirn of the incorrectly received character nid

Claims (2)

Claims: ι 1. A data transmission method in a receiving station shows a figure in which useful information takes place via a forward channel of redundant test information and test and / or playback signals are sent to the transmitting station via a forward channel, thereby identifying except for the test signals in an
If the received information is returned to the transmitting station, it is also compared in a known manner, originally stored information, η are provided (flip-flops 1 F .: associated gate circuits and S \ um in the receiver-side recognition in the forward channel Information to change this information vd transmission via the backward deliberate introduction of a zi. 1 2. Data transmission method spoke 1, in which the test information and is formed as redundant at the receiving end, thereby identifying: the useful information instead of the urs parity bits sent with the | gen error checking (by the Paij Determined parity bit of the useful information Mq transmitted for transmission 1 sheet of drawings