DE1293906B - Silicon planar transistor - Google Patents

Silicon planar transistor

Info

Publication number
DE1293906B
DE1293906B DEST23081A DEST023081A DE1293906B DE 1293906 B DE1293906 B DE 1293906B DE ST23081 A DEST23081 A DE ST23081A DE ST023081 A DEST023081 A DE ST023081A DE 1293906 B DE1293906 B DE 1293906B
Authority
DE
Germany
Prior art keywords
emitter
base
strips
planar transistor
silicon planar
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
DEST23081A
Other languages
German (de)
Inventor
Page Barry
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TDK Micronas GmbH
Original Assignee
Deutsche ITT Industries GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Deutsche ITT Industries GmbH filed Critical Deutsche ITT Industries GmbH
Publication of DE1293906B publication Critical patent/DE1293906B/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/4501—Shape
    • H01L2224/45012—Cross-sectional shape
    • H01L2224/45015—Cross-sectional shape being circular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H01L2224/486—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48617—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950 °C
    • H01L2224/48624—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20—Parameters
    • H01L2924/207—Diameter ranges
    • H01L2924/20752—Diameter ranges larger or equal to 20 microns less than 30 microns
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30105—Capacitance

Description

1 21 2

Die Erfindung betrifft einen Silizium-Planartransi- niedrigerem Widerstand in bekannter Weise herge-The invention relates to a silicon planar transi- lower resistance in a known manner.

stor für A-Verstärker mit 5 Watt Ausgangsleistung und stellt wurde. Die Siliziumscheibe 6 ist so behandelt,stor for A-amplifier with 5 watt output power and provides. The silicon wafer 6 is treated so

einem Produkt von Verstärkung und Bandbreite von daß sie Zonen vom p-Typ und vom η-Typ enthält.a product of gain and bandwidth of that it contains p-type and η-type zones.

600MHz, dessen Basiselektrode aus einem recht- Die Baiszone 4 besteht aus Silizium vom p-Typ, die eckigen Rahmen mit η von einer Seite des Rahmens 5 Emitterzone 3 und die Kollektorzone 6 aus SiliziumThe base zone 4 consists of p-type silicon, the angular frame with η from one side of the frame 5 emitter zone 3 and the collector zone 6 made of silicon

nach innen reichenden Basisstreifen besteht und vom n-Typ.inwardly extending base stripes and of the n-type.

dessen Emitterelektrode mit η + 1 Emitterstreifen F i g. 1 zeigt einen Elektrodenaufbau mit ineinden Rahmen bis auf einen Zwischenraum zu den andergreifenden Emitter- und Basiselektroden für Basisstreifen ausfüllt. einen Transistor mittlerer Leistung, bei dem eine Aus der französischen Patentschrift 1 335 510 ist io Emitterelektrode 1, beispielsweise eine Aluminiumein solcher Transistor mit η Basisstreifen und η + 1 schicht, welche in die Siliziumoberfläche einlegiert Emitterstreifen bekannt. In dieser Patentschrift wird ist, aus mehreren Streifen besteht und bei dem die das bekannte Verfahren zur Herstellung der einzel- Emitterelektrode 1 an allen Seiten von der Basisnen Zonen mit Hilfe von Masken beschrieben. Es elektrode 2 umgeben ist.its emitter electrode with η + 1 emitter stripe F i g. 1 shows an electrode structure with a frame except for a gap between the emitter and base electrodes for base strips. a transistor of medium power, in which an emitter electrode 1, for example an aluminum, is known from French patent 1 335 510, such a transistor with η base strips and η + 1 layer, which emitter strips are alloyed into the silicon surface. In this patent specification is, consists of several strips and in which the known method for producing the single emitter electrode 1 on all sides of the base zone is described with the aid of masks. There electrode 2 is surrounded.

findet sich jedoch kein Hinweis auf die Anordnung 15 Die beiden Elektroden nach der F i g. 1 liegen auf der Kontaktflächen für das Anbringen von Zu- der gleichen Oberfläche der entsprechenden Zonen, leitungen. was deutlicher aus Fig. 2 hervorgeht, in welcher ein Ferner ist aus der USA.-Patentschrift 3 083 441 Schnitt durch den Transistor nach der Fig. 1 längs die Kammstruktur der Emitterzone eines Transistors der Linie A-A dargestellt ist. Die Emitterelektrode 1 bekannt. Ineinandergreifende Kammstrukturen der ao liegt auf der Oberfläche der Emitterzone 3 vom beiden Elektroden eines dielektrischen Bauelements η-Typ in Abstand von dem pn-übergang zwischen sind aus der französischen Patentschrift 1 301 563 dieser Zone und der Basiszone 4 vom p-Typ. Dieser bekannt. pn-übergang ist durch eine oberflächliche Schicht Aus der Patentschrift 33 354 des Amtes für Erfin- aus Siliziumoxyd 5 geschützt, welche auf der Oberdungs- und Patentwesen in Ost-Berlin ist ein Tran- 25 fläche der Siliziumscheibe 6, in der der Transistor sistor bekannt, bei dem die Emitter- und Basisstreifen erzeugt wurde, angeordnet ist. Die Basiselektrode 2 so angeordnet sind, daß bei etwa quadratischem liegt auf der Basiszone 4 zwischen den Teilzonen Grundriß des Transistors die Kontaktflächen für die der Emitterzone 3. Nachdem Teile der Oxydschicht 5 Emitter- und die Basiszone sich diagonal gegenüber- weggeätzt wurden, ist über die ganze Länge des liegen. Die Länge der einzelnen Streifen nimmt hier- 30 Emitter-pn-Übergangs ein mäanderförmiger Streifen bei bei Annäherung der Streifen an diese Diagonale des Siliziumoxyds an der Oberfläche verblieben. Der ab, so daß in zwei Ecken größere Gebiete als Kon- KoIIektor-pn-Übergang zwischen den Zonen 4 und 6 taktflächen frei von Streifen bleiben. ist ebenfalls durch die Siliziumoxydschicht 5 an der Untersuchungen haben gezeigt, daß die optimale Oberfläche geschützt. Die wesentlichen Abmessungen Anordnung der einzelnen Streifen zusammen mit den 35 dieses Transistors sind folgende: Die Fläche der geometrischen Abmessungen für Transistortypen ver- Basiszone 4 beträgt 0,4 mm2, eine Emitterteilzone 3 schiedener vorbestimmter Kollektorverlustleistung hat eine Breite von 0,045 mm, die Emitter- und Basissehr unterschiedlich ist. elektroden 1 und 2 haben je eine Breite von 0,025 mm, Der Erfindung liegt deshalb die Aufgabe zugrunde, und die Emitterzone 3 hat eine Randlänge von die Basis- und die Emitterstreifen zusammen mit den 40 2,5 mm. Die Kontaktflächen der Basis- und der Kontaktflächen eines Silizium-Planartransistors für Emitterelektrode haben je eine Fläche von 0,11 mm2. 5-Watt-A-Verstärker und 600 MHz Verstärkungs- Zur Befestigung eines Golddrahtes mit einer Kugel Bandbreite-Produkt optimal geometrisch anzuordnen. am Ende (vgl. die F i g. 3), wird die Kugel 10 am Die Erfindung, die diese Aufgabe löst, besteht dar- Ende des Drahtes 11 beispielsweise auf die Basisin, daß je einer der Basis- und Emitterstreifen zum 45 elektrode 2 aufgedrückt, und zwar mit Hilfe des Erzeugen einer Kontaktfläche für das Anbringen von Endes eines nicht dargestellten Zuführungsrohres, Zuleitungen an die Elektroden verkürzt ist und daß durch welches der Draht 11 läuft. Es wurde experidie Basiszone eine Fläche von etwa 0,4 mm2 inner- mentell festgestellt, daß für einen guten Kontakt der halb eines Spielraumes der linearen Abmessungen von Kontaktdurchmesser nicht größer sein muß als der 20% nach unten und 40 «/ο nach oben einnimmt. 50 dreifache Durchmesser des Drahtes. So kann ein Die Erfindung wird nun an Hand eines in der Golddraht mit einem Durchmesser von 0,025 mm gut Zeichnung dargestellten Ausführungsbeispieles näher an einer der Kontaktflächen 8 oder 9 befestigt wererläutert. den, ohne daß ein besonderer Aufwand für das ge-F i g. 1 zeigt einen vergrößerten Grundriß des naue Aufbringen des Drahtes erforderlich ist, oder Silizium-Planartransistors mit den Basis- und Emitter- 55 ein Draht von 0,0375 mm Durchmesser kann bei gestreifen; nauer Einstellung der Position befestigt werden, so F i g. 2 zeigt den Schnitt durch den Teil eines epi- daß er geringfügig über das Gebiet hinausragt, jetaxialen Siliziumplättchens, in dem der Silizium- doch nicht zu nahe an den Übergang herankommt. Planartransistor hergestellt wurde, längs der Linie Im Gegensatz zu der Herstellung dieser Kontakte A-A der Fig. 1; 60 eines Silizium-Planartransistors nach der Erfindung F i g. 3 zeigt den Schnitt durch einen am Ende mit ergeben sich Schwierigkeiten bei der Herstellung der einer Kugel versehenen Golddraht, der als Zuleitung Kontakte der bekannten Transistoren, die zwei an der Kontaktfläche der Basiselektrode befestigt ist. Emitterstreifen haben und durch den Silizium-Planar-Die F i g. 1 und 2 zeigen im Grundriß und im transistor nach der Erfindung ersetzbar sind, bei dem Schnitt einen Silizium-Epitaxial-Planartransistor für 65 zwei Emitterteilzonen mit einer Breite von 0,045 mm mittlere Leistung, der aus einer dünnen Scheibe 6 und einer Länge von je 0,625 mm den gleichen aus Silizium besteht, welche nach dem Epitaxialver- Emitterumfang ergeben und etwa dieselbe Basisfahren auf der Oberfläche einer Unterlage 7 von fläche benötigen. Es ist auch möglich, die DrähteHowever, there is no reference to the arrangement 15. The two electrodes according to FIG. 1 lie on the contact surfaces for attaching to the same surface of the corresponding zones, lines. which can be seen more clearly from FIG. 2, in which a section through the transistor according to FIG. 1 along the comb structure of the emitter zone of a transistor along the line AA is also shown in US Pat. No. 3,083,441. The emitter electrode 1 is known. Interlocking comb structures of the ao lies on the surface of the emitter zone 3 of the two electrodes of a dielectric component η-type at a distance from the pn-junction between this zone and the base zone 4 of the p-type. This known. The pn junction is protected by a superficial layer From the patent 33 354 of the Office for Invention from silicon oxide 5, which is known from the Oberdungs- und Patentwesen in East Berlin, a tran- 25 surface of the silicon wafer 6 in which the transistor sistor is known , in which the emitter and base strips were produced, is arranged. The base electrode 2 are arranged so that when the base zone 4 is roughly square, the contact areas for the emitter zone 3 lie on the base zone 4 between the partial zones entire length of the lie. The length of the individual strips is a meandering strip that remains on the surface when the strips approach this diagonal of the silicon oxide. The off, so that in two corners larger areas as a connector-pn-junction between zones 4 and 6 remain free of stripes. is also through the silicon oxide layer 5 on the tests have shown that the optimal surface is protected. The main dimensions of the arrangement of the individual strips together with the 35 of this transistor are as follows: The area of the geometric dimensions for transistor types - base zone 4 is 0.4 mm 2 , an emitter sub-zone 3 of various predetermined collector power losses has a width of 0.045 mm, the emitter and base is very different. Electrodes 1 and 2 each have a width of 0.025 mm. The invention is therefore based on the object, and the emitter zone 3 has an edge length of the base and emitter strips together with the 40 2.5 mm. The contact areas of the base and the contact areas of a silicon planar transistor for the emitter electrode each have an area of 0.11 mm 2 . 5 watt A amplifier and 600 MHz amplification To attach a gold wire with a ball bandwidth product to be optimally arranged geometrically. At the end (see Fig. 3), the ball 10 is The invention that solves this problem consists of the end of the wire 11, for example, on the base that each of the base and emitter strips to the 45 electrode 2 pressed, with the help of the creation of a contact surface for attaching the end of a feed tube, not shown, leads to the electrodes is shortened and that through which the wire 11 runs. It was experimentally determined that the base zone has an area of about 0.4 mm 2 internally, so that half a range of the linear dimensions of the contact diameter does not have to be greater than the 20% downwards and 40% upwards for a good contact . 50 three times the diameter of the wire. The invention will now be explained in more detail on one of the contact surfaces 8 or 9 with the aid of an exemplary embodiment shown in the gold wire with a diameter of 0.025 mm. without any special effort for the ge-F i g. 1 shows an enlarged plan view of the precise application of the wire or silicon planar transistor with the base and emitter 55 a wire 0.0375 mm in diameter can be striped at; more precise setting of the position are attached, so F i g. 2 shows the section through the part of an epi- that it projects slightly beyond the area, jetaxial silicon wafer in which the silicon does not come too close to the transition. Planar transistor was manufactured along the line In contrast to the manufacture of these contacts AA of Fig. 1; 60 of a silicon planar transistor according to the invention F i g. 3 shows the section through a gold wire provided at the end with difficulties in the manufacture of a ball provided with gold wire, which is used as a feed line for contacts of the known transistors, and the two are attached to the contact surface of the base electrode. Have emitter strips and through the silicon planar die F i g. 1 and 2 show in plan and in the transistor according to the invention are replaceable, in the section a silicon epitaxial planar transistor for 65 two emitter sub-zones with a width of 0.045 mm mean power, which consists of a thin disk 6 and a length of 0.625 mm each the same consists of silicon, which result in the epitaxial emitter circumference and require approximately the same basic travel on the surface of a base 7 of area. It is also possible to use the wires

von 0,025 mm Durchmesser durch Aufdrücken mit einem meißelartigen Werkzeug zu befestigen, jedoch ist das Ausrichten viel schwieriger, und die Verbindung ist weniger gut. Drähte von 0,0375 mm Durchmesser können nicht auf diese Weise aufgebracht werden, da die Gefahr besteht, daß bei geringfügigen Abweichungen eine Beeinträchtigung des pn-Übergangs auftritt.0.025 mm in diameter by pressing on with a chisel-like tool, however alignment is much more difficult and the connection is less good. Wires 0.0375 mm in diameter cannot be applied in this way as there is a risk of minor Deviations an impairment of the pn-junction occurs.

Der Silizium-Planartransistor nach der Erfindung ist geeignet zur Verwendung bei 100 mA und einer Ausgangsleistung von 5 Watt in Verstärkern in Α-Schaltung und einer Groß-Signal-Leistungsververstärkung von 8 db. Der übliche flache Bereich in der Stromverstärkung-Emitterstrom-Kennlinie liegt bei einem Emitterstrom von etwa 150 mA, jedoch ist ein zufriedenstellender Betrieb auch bei 250 mA möglich.The silicon planar transistor of the invention is suitable for use at 100 mA and one Output power of 5 watts in amplifiers in Α-circuit and a large-signal power amplification from 8 db. The usual flat area in the current gain-emitter current characteristic is at an emitter current of about 150 mA, however, satisfactory operation is also at 250 mA possible.

Das Verstärkung-Bandbreite-Produkt beträgt 600MHz, eine Forderung, die zu einem C0B von 10 pF bei 10 V und so zu der oben beschriebenen Basiszone führt. Der Silizium-Planartransistor hat eine optimale Größe bei der beschriebenen Ausbildung. Die linearen Abmessungen konnten um nicht mehr als 20% vermindert und um nicht mehr als 40% vergrößert werden, ohne die geometrische An-Ordnung zu ändern.The gain-bandwidth product is 600MHz, a requirement that leads to a C 0B of 10 pF at 10 V and thus to the base zone described above. The silicon planar transistor has an optimal size in the design described. The linear dimensions could be reduced by no more than 20% and increased by no more than 40% without changing the geometrical arrangement.

Claims (4)

Patentansprüche:Patent claims: 1. Silizium-Planartransistor für A-Verstärker mit 5 Watt Ausgangsleistung und einem Produkt von Verstärkung und Bandbreite von 600 MHz, dessen Basiselektrode aus einem rechteckigen Rahmen mit η von einer Seite des Rahmens nach innen reichenden Basisstreifen besteht und dessen Emitterelektrode mit «+1 Emitterstreifen den Rahmen bis auf einen Zwischenraum zu den Basisstreifen ausfüllt, dadurch gekennzeichnet, daß je einer der Basis- (2) und Emitterstreifen (1) zum Erzeugen einer Kontaktfläche (8, 9) für das Anbringen von Zuleitungen an die Elektroden verkürzt ist und daß die Basiszone (4) eine Fläche von etwa 0,4 mm2 innerhalb eines Spielraums der linearen Abmessungen von 20% nach unten und 40% nach oben einnimmt.1. Silicon planar transistor for A amplifier with 5 watt output power and a product of gain and bandwidth of 600 MHz, the base electrode of which consists of a rectangular frame with η base strips extending inward from one side of the frame and the emitter electrode with «+1 emitter strips fills the frame except for a space between the base strips, characterized in that each of the base (2) and emitter strips (1) is shortened to produce a contact surface (8, 9) for attaching leads to the electrodes and that the Base zone (4) occupies an area of about 0.4 mm 2 within a range of linear dimensions of 20% downwards and 40% upwards. 2. Silizium-Planartransistor nach Anspruch 1, dadurch gekennzeichnet, daß an den Kontaktflächen (8, 9) je ein in Form einer Kugel (10) ausgebildetes Ende eines als Zuleitung dienenden Drahtes (11) angebracht ist.2. silicon planar transistor according to claim 1, characterized in that on the contact surfaces (8, 9) each have an end in the form of a ball (10) of one serving as a supply line Wire (11) is attached. 3. Silizium-Planartransistor nach Anspruch 1 oder 2, dadurch gekennzeichnet, daß die Emitterstreifen (1) die Emitterteilzonen (3) kontaktieren. 3. silicon planar transistor according to claim 1 or 2, characterized in that the emitter strips (1) contact the emitter sub-zones (3). 4. Silizium-Planartransistor nach den Ansprüchen 1 bis 3, dadurch gekennzeichnet, daß 0,025 mm breite Emitterstreifen (1) 0,045 mm breite Emitterteilzonen (3) einer Emitterzone mit einer Randlänge von 2,5 mm kontaktieren und daß die Kontaktflächen (8,9) 0,11mm2 groß sind.4. silicon planar transistor according to claims 1 to 3, characterized in that 0.025 mm wide emitter strips (1) 0.045 mm wide emitter sub-zones (3) contact an emitter zone with an edge length of 2.5 mm and that the contact surfaces (8, 9) 0.11mm 2 in size. Hierzu 1 Blatt Zeichnungen 1 sheet of drawings
DEST23081A 1963-12-31 1964-12-15 Silicon planar transistor Pending DE1293906B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB51338/63A GB1024166A (en) 1963-12-31 1963-12-31 Improvements in or relating to semiconductor devices

Publications (1)

Publication Number Publication Date
DE1293906B true DE1293906B (en) 1969-04-30

Family

ID=10459611

Family Applications (1)

Application Number Title Priority Date Filing Date
DEST23081A Pending DE1293906B (en) 1963-12-31 1964-12-15 Silicon planar transistor

Country Status (2)

Country Link
DE (1) DE1293906B (en)
GB (1) GB1024166A (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR1301563A (en) * 1960-09-21 1962-08-17 Ass Elect Ind Improvements to dielectric devices
US3083441A (en) * 1959-04-13 1963-04-02 Texas Instruments Inc Method for fabricating transistors
FR1335510A (en) * 1960-09-09 1963-08-23 Texas Instruments Inc Silicon transistors for high currents

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3083441A (en) * 1959-04-13 1963-04-02 Texas Instruments Inc Method for fabricating transistors
FR1335510A (en) * 1960-09-09 1963-08-23 Texas Instruments Inc Silicon transistors for high currents
FR1301563A (en) * 1960-09-21 1962-08-17 Ass Elect Ind Improvements to dielectric devices

Also Published As

Publication number Publication date
GB1024166A (en) 1966-03-30

Similar Documents

Publication Publication Date Title
DE961469C (en) Process for the production of semiconductor bodies for electrical transmission devices
DE3134074A1 (en) SEMICONDUCTOR COMPONENT
DE1914442C3 (en) Semiconductor device
DE2002810B2 (en) SEMICONDUCTOR DIODE FOR GENERATING OR AMPLIFICING MICROWAVES AND PROCEDURES FOR YOUR OPERATION
DE2911537A1 (en) DARLINGTON POWER TRANSISTOR
DE2147447C3 (en) Semiconductor component
DE1514008B2 (en) AREA TRANSISTOR
DE1293900B (en) Field effect semiconductor device
DE1614858C3 (en) Semiconductor device
DE1293906B (en) Silicon planar transistor
DE1188209B (en) Semiconductor component
DE1912931C3 (en) Semiconductor component
DE812091C (en) Amplifier from a semiconductor body
DE1489809A1 (en) Voltage-dependent semiconductor resistance, in particular Zener diode
DE2520134C3 (en) Thyristor with a rectangular semiconductor element
DE1614800C3 (en) Method for producing a planar transistor with tetrode properties
DE1297239C2 (en) POWER TRANSISTOR
DE2923693A1 (en) SWITCHING TRANSISTOR
DE1639458B1 (en) Semiconductor device
DE1259425B (en) Low-inductance connection of at least one switching element to a symmetrical ribbon line
DE1816439C3 (en) Power transistor
DE1965407A1 (en) Semiconductor device
DE1614026C3 (en) transistor
DE2332574A1 (en) METHOD OF MANUFACTURING A SEMICONDUCTOR AND A SEMICONDUCTOR DEVICE
DE2062333A1 (en) Semiconductor device with a multiple electrode, in particular multiple emitter power transistor