DE1276744B - Circuit arrangement for pulse-controlled, cyclically coded counting and / or dialing relay chains - Google Patents

Description

Circuit arrangement for pulse-controlled, cyclically coded working Counting and / or dialing relay chains The invention relates to a circuit arrangement for pulse-controlled, cyclically coded counting and / or dialing relay chains for telecommunications systems, in particular telephone exchanges, which at least have two clock stages, each consisting of two clock relays, in each of which the pickup winding of the second and the holding winding of the first clock relay in Series are connected in a common circuit, while the response circuit of the first and the holding circuit of the second clock relay via a changeover contact of the second clock relay are controlled alternately.

By the German Auslegeschrift 1190 997 relay chains are known, in which each clock stage runs through successively and periodically recurring cycles with four switching states each during the - with respect to the clock stage in question - the same number, z. B. three, successive switching states of the pulse relay (z. B. dropped out, actuated, dropped out) last, depending on whether none, only the first, the first and the second and / or only the second of the clock relay is energized.

The two clock relays are the second and each following controlled clock stage only from the two clock relays of the upstream controlling clock stage by holding each clock relay until the controlling pulse stage one and a half since the response of the considered clock relay Cycles, i.e. six switching states.

The second and the following clock stages are designed so that the respective clock stage executes a clock in the time in which the upstream controlling cycle stage runs through three cycles. To carry out this cycle, everyone has Clock relay has a response winding and a holding winding, each of which is controlled by itself will. After the completion of six switching states of the upstream controlling clock stage the holding winding of the respective clock relay is switched on via one contact of the other clock relay of the same clock stage and one contact each each clock relay of the previous clock stage short-circuited and only then the Holding circuit disconnected.

The disadvantage here is that to limit the short-circuit current two resistors are required per clock stage. Furthermore, the short circuit of the Hold winding of the respective clock relay is maintained or delayed for so long until all contacts of this clock relay are back in their original position. The control pulses must therefore have a certain minimum duration if the safe Function of the relay chain should be guaranteed. The degree of utilization of the known Relay chain is therefore restricted because its clock frequency is always lower must, as it z. B. would allow the normal fall times of the clock relays. A However, with the known relay chain, the holding windings are switched off without delay not easily feasible.

The invention is based on the object of an undelayed disconnection of the holding circuits and to create a relay chain in which with little effort and only using the relay times described at the beginning Tripartite is achieved.

According to the invention, this object is achieved in that each clock relay in three during the mentioned six switching states of the respective controlling clock stage alternately and successively effective holding circuits can be switched on, the last of which is separated at the end of the sixth of the switching states mentioned.

It is in the first holding circuit of the first clock relay second and each subsequent controlled clock stage switched on its response winding, while its holding winding is switched on in the second and third holding circuit is.

In the first to third holding circuit of the second clock relay second and each subsequent clock stage only its holding winding is switched on.

As a result of this arrangement, the relay chain works with the shortest at all possible actuation times of the relays, which are the case with normal flat relays 10 ms, including the contact times for reversing. From this it follows an upper clock frequency of about 40 Hz. Besides the elimination the known disadvantages, a saving in contacts is achieved. Here has at an embodiment of the invention, the first clock relay of the second clock stage two changeover and two normally open contacts and the second clock relay of the second clock stage a changeover contact and two normally open contacts, while the first clock relay is the upstream clock stage two changeover contacts and a normally open contact and that second clock relay of the upstream clock stage a changeover contact and a normally open contact exhibit. The first clock relay of the last, z. B. the third clock stage has two Normally open contacts and the second clock relay of the third clock stage have a switching and a working contact. These contact arrangements can be swapped accordingly.

The invention is explained in more detail using an exemplary embodiment shown in the drawing. Herein, FIG. 1 the circuit of a three-stage relay chain with an upstream clock stage T 1 and two clock stages T 2 and T3, F i g. 2 a to 2 d different circuit designs of the second and each subsequent clock stage with the beginning of the relay diagram and FIG. 3 is a complete relay diagram for the relay chain of FIG. 1.

The clock relays are designated with X and Y and, depending on their assignment to one of the clock stages, have the index designation 1, 2 or 3.

The response windings are labeled I and the holding windings are labeled II.

The relay chain is with the help of a contact i a not shown Pulse relay controlled. The circuit is drawn in the idle state, i. In other words, the pulse relay has not responded. After the end of each pulse it returns the contact i returns to the position shown.

With the first pulse, the pulse relay (not shown) responds and switches its contact i. The first clock relay X 1 of the first clock stage T 1 is excited by: 1. Earth, i, 1y1, XII, -.

With the contact 1x1 closed, the holding circuit for the first clock relay X1 and at the same time the response circuit for the second clock relay Y1 prepared.

When contact i returns to its rest position, it becomes two clock relays common circuit closed: 2nd earth, 1x1, i, XIII, YlI, -.

The clock relay Y1 responds and prepares with its contact 2 y 1 the response circuit of the first clock relay X 2 of the second clock stage T 2 . The clock relay X1 remains in circuit 2.

With the second pulse, the circuit 2 is interrupted by means of contact i, whereby the holding winding XI II is de-energized and the clock relay X 1 returns to its rest position.

The clock relay Y1 remains in the circuit: 3rd earth, i, 1 y 1, Y III, -.

At the end of the second pulse, contact i interrupts circuit 3 and clock relay Y 1 returns to its rest position. When the clock relay X1 drops out, the prepared circuit for the response winding I de; first clock relay X 2 closed in the second clock stage T 2 : 4th earth, 2x1, 2y1, 1y2, X21, -.

After the clock relay Y1 has returned to its rest position, the first one holds Clock relay X2 of clock stage T2 in a first holding circuit.

5. Earth, 4x2, 1y2, X21, -. This ends the first cycle.

At the beginning of the third pulse, the first clock stage initiates a new one A cycle in which circuits 1, 2, 3 and 5 become effective again. That Clock relay X1 prepares with its contact 2x1 the common circuit for the Pickup winding I of the second clock relay Y2 and the holding winding 1I of the first Clock relay X2 of the second clock stage. At the end of the third pulse this becomes Circuit closed: 6. Earth, 4x2, 2y1, 2x1, 1x2, X2H, Y21, -. In this circuit 6 responds to the timing relay Y2, at the same time the timing relay X2 is only activated in this Circuit continued because the contact 1y2 the first holding circuit 5 for the clock relay X2 has interrupted.

The clock relay Y2 switches to a first holding circuit: 7. Earth, 4x2, 1y2, Y211, -.

With the fourth pulse the clock relay X1 returns to its rest position, whereby the second holding circuit 6 for the clock relay X2 is interrupted and the clock relay X2 is switched to a third holding circuit: B. Earth, 4x2, 2y2, 3x1, 1x2, X211, Y21, -. In the pause after the end of the fourth pulse, the clock relay Y 1 returns to the rest position in the first clock stage T 1 , whereby the second cycle of the clock stage T1 is ended.

With the beginning of the fifth pulse and renewed activation of the clock relay X1 begins the third cycle.

The contact 3x1 interrupts the circuit 8, so that the clock relay X2 returns to its rest position, while the clock relay Y2 is in a second holding circuit is held: 9. Earth, 3x1, 2y2, 1y2, Y211, -.

At the end of the fifth pulse, the clock relay responds Y 1 prepared a third holding circuit for the clock relay Y2. This third one Holding circuit for the clock relay Y2, which takes effect at the beginning of the sixth pulse after the clock relay X1 has returned to its rest position, runs via: 10. Earth, 2x1, 2y1, 1y2, Y211, -.

At the end of the sixth pulse, the clock relay Y1 returns to its rest position, which ends the third cycle of the first clock stage. At the same time, the third holding circuit 10 for the clock relay Y2 is disconnected, and this returns to its rest position. The first cycle of the second clock stage T2 is thus ended. The control of the third clock stage T3, which has the same contact structure as the second clock stage T2, is handled in the same way. In the contact structure of clock stage T3, contacts of clock relays X 2, Y 2 take on the same functions as the contacts of clock relays X 1, Y 1 in clock stage T 2, while contacts of clock relays X3, Y3 in clock stage T 3 take on the same functions as the contacts of the clock relays X 2, Y 2 in the clock stage T2.

The first clock relay X 3 of the clock stage T 3 responds in a known manner for the first time when the circuit 8 is interrupted for the first time, that is at the beginning of the fifth pulse. The clock relay X2 is in the rest position. The response circuit for the clock relay X3 runs via: 11. Earth, 2x2, 3y2, 1y3, X31, -.

All further switching processes are analogous to those described above. The cycle of the third clock stage T3 extends over three cycles of the second Clock stage T2 and ends with the eighteenth pulse.

The total switching states of the clock relays of all three clock stages are shown in FIG. 3 shown. Of course, other contact combinations are also possible in the clock stages T 2 and T 3 while maintaining the concept of the invention, the beginning of the cycle of the second stage each time starting at a different point in time, which is indicated by an arrow in FIG. 2a to 2d is indicated.

From this it can be seen that the beginning of the first cycle of the second and each subsequent clock stage is not directly tied to the point in time which the first clock relay X1 of the previous clock stage T1 in its rest position returns, as shown in accordance with the relay chain the German Auslegeschrift 1190 997 at the in F i g. 1 shown and on hand from F i g. 2a and 3 explained relay chain according to the invention is the case.

This point in time can also be triggered by the response of the second clock relay Y1 (see Fig. 2b) or the response of the first clock relay X 1 (see Fig. 2 c) or on the return to the rest position of the second clock relay Y 1 (cf. F i g. 2 d) of the previous stage. This changes the cyclical Sequence of the four different switching states of the second and each subsequent cycle stage nothing. This means that each switching state of a clock stage is over three successive ones Switching states of the previous clock stage extends.

The in Fig. The circuit example shown in FIG. 1, including the associated circuit description, is therefore only one exemplary embodiment of four possible operating modes for the clock stages T 2 and T3.

Claims (4)

Claims: 1. Circuit arrangement for pulse-controlled, cyclically coded working counting and / or dialing relay chains in telecommunication systems, in particular telephone switching systems, which have at least two clock stages each consisting of two clock relays, in which the response winding of the second and the holding winding of the first clock relay in Series are connected in a common circuit, while the response circuit of the first and the holding circuit of the second clock relay are controlled alternately via a changeover contact of the second clock relay, and which work in a cycle of four successive switching states, with a switching state of each controlled clock stage over three successive switching states of the upstream controlling clock stage extends in that each clock relay responding in a controlled clock stage is held until the respective controlling clock stage has responded to the respective clock pulse lais has passed through six successive switching states, characterized in that each clock relay (X2; X 3 and Y2; Y3) in three during the mentioned six switching states of the respective controlling clock stage (X2 with 1y2 or 2y1 and 2x1 or 2y2 and 3 x 1, Y 2 with 4x2 or 3x1 or 2x1 and 2y1 in Figs. 1 and 2 a) alternately and successively effective holding circuits can be switched on, the last of which is separated at the end of the sixth of the switching states mentioned (by 3x1 or 2y1 in FIGS. 1 and 2a). 2. Circuit arrangement according to claim 1, characterized in that in the first holding circuit of the first Clock relay (X2) of the second (T2) and each subsequent controlled clock stage his Pickup winding (I) is switched on. 3. Circuit arrangement according to claim 1, characterized in that in the second and third holding circuit of the first Clock relay (X 2) of the second (T2) and each subsequent clock stage its holding winding (II) is switched on. 4. Circuit arrangement according to claim 1, characterized in that only its holding winding (II) is switched on in the first to third holding circuit of the second clock relay (Y2) of the second (T2) and each subsequent clock stage. Considered publications: Deutsche Auslegeschriften Nr. 1164 505, 1190997.