DE1234059B - Priority control for a data processing system consisting of several computers - Google Patents

Description

Priority control for a data processing system consisting of several computers C The invention relates to a program-controlled data processing system with a plurality of independently operating computers, each of which can transfer program parts to any other computer in accordance with its respective program. Furthermore, the data processing system has a common memory, which is optionally divided into several separately addressable memory blocks, a plurality of peripheral devices such as input / output devices and the like, and a central switching unit. The latter allows the cooperation of the computer with each other, the computer with the peripherals and memory blocks after a loading preferably from Rechnerprogranirnen voted precedence. The cooperation takes place in such a way that computer, where a program higher precedence is assigned to handle other computers, to memory blocks and peripherals obtained compared to machines having a lower priority a Favor th & supply. 9 The invention describes an advantageous priority control for such a data processing system.

Such data processing systems with several computers and several memory blocks, each computer optionally being able to work together with each memory block, allow simultaneous processing of several independent programs. In order to achieve full utilization of the computers and processing of the programs according to their importance, i.e. their priority, the individual computers must not be assigned any priority numbers that are generally valid for the system, as could be determined by wiring, for example. In the case of several known data processing systems, the priority allocation is carried out by means of a so-called service program. Utilities regulate the "distribution in the Great", d. In other words, they regulate the distribution of programs or program sections to the various computers and monitor the processing status. However, the priority assignment by programs has the disadvantage of being very time-consuming. So pass z. B. several memory cycles until a connection between different units (computer computer, computer memory) is established taking into account the respective priority.

The object of the invention is to create a system for priority assignment that allows the connection to be set up, including all necessary queries and tests, to be carried out in the shortest possible time. The features of the invention emerge from the claims, the advantages and details thereof from the description and the drawings. The drawings, in conjunction with the description, give an example of the invention, namely FIG. 1 is a block diagram of the system according to the invention Fig 2 * of the same switching imagewise cutouts and F i a 3 as well as the F i g. 4 and 5 necessary explanations of in FIG. 2 used circuit symbols.

In the following, without reference to the drawings for the time being, the principle the priority assignment as used in the data processing system according to the invention is described. There are n independent computers that work together with m Storage units form a program-controlled digital data processing system. Every computer can work together with every storage unit. Every computer works a stand-alone program. The programs are in the order of their importance Assigned priority numbers. The agreement should be used here for further description it can be made that higher priority numbers correspond to higher degrees of importance. The program of one computer can also be part of the program of another Be the computer. If a computer wants to give up parts of its own program, it gives a computer request signal, which causes him either a free computer is assigned to the program transfer or that the computer is assigned to it, who processes the program with the lowest priority, i.e. the one with the lowest Has priority. The processes of the computers are therefore changeable. Asks a calculator If a free computer is available, the requested one receives Calculator the respective priority of the requesting computer while the latter as well as all of the higher-priority computers located below this one the value ONE will be given lower priority. If no computer is free, how already mentioned, the program of the computer with the lowest priority was interrupted, and this computer is made available to the requesting party. After completion of a program, the respective computer emits a computer-free signal, and all of them Computers that are primarily below this computer receive a value of ONE increased priority. If, on the other hand, several computers request one computer at the same time to transfer the program, if at all possible, it will be the highest for the computer A computer is assigned priority among the requesting computers.

Fig. 1 now shows the circuit according to the invention, which operates according to this principle, as a block diagram. Four computers 6, 7, 8 and 9 work together with the central unit 5 , which enables "large-scale distribution". This accepts computer-free signals from individual computers and essentially ensures the necessary switchovers that are necessary when a computer transfers parts of the program or when a computer is to be connected to a new or further memory unit. To enable each computer to work with each memory, the central unit 5 contains a crossbar-like switching system. If a computer, e.g. If, for example, that of the lowest priority is interrupted for the purpose of program takeover, he must cancel his own program and save the position of his registers etc. before the program is taken over. This process is commonly known as "copy status". For the status copy, each of the computers 6, 7, 8 and 9 thus has an interrupt mechanism, which, however, are not shown in the drawing. The storage units are also not shown, since they are not essential for an understanding of the invention. Every computer has an ordinal number, a number. It is arbitrarily determined here that the computer 6 carries the number 1, the computer 7 the number 2, the computer 8 the number 3 and the computer 9 the number 4. At its outputs 56 to 59, the central unit indicates the number of the respective free reported computer and, if there are several free computers, the number of one of these computers. All except the computers 6 to 9 and the central processing unit 5 in FIG. 1 are used for priority assignment.

With 1 there is designated a priority allocator. This indicates the priority distribution in the computing system on its multiple lines g, h, i and k. For this purpose, each of the multiple lines is permanently assigned a priority number, e.g. B. the multiple line k priority 4, i priority 3, h priority 2 and g priority 1, corresponding to the four possible priorities with four computers. Each multiple line, however, indicates the number of a computer. The computer specified by a multiple line has the priority of the same. If, for example, the computer number 4 is given by the line h, the computer 9, whose number is 4, has priority 2. All decision units of the data processing system that have to make decisions taking the priority distribution into account are connected to the multiple lines g, li, i , k connected. In the drawing, these lead to priority detectors 2, 2a, 2b and computer detectors 4, 4a.

The computer-free message must be sent to the priority assigner for priority assignment according to the principles mentioned above. This is done via the lines 165, 166 and 167. through the lines 151+ 154+ to the Vorrangzuordner requested computer receives commands 1 for classifying free but in the scale of Vorränge. The number of the computer concerned required for this is fed to him via lines 56 to 59. In addition, the priority allocator 1 must be informed when one of the computers requests another computer. He still does not need this knowledge in the form of the number of the requesting computer, but in the form of the priority number of the computer concerned. The priority detector 2 is provided for converting the number of the respective requesting computer into its respective priority number. This receives the computer request messages over the lines 246, 247, 248, 249, the last digit identifying the computer requesting each. The computer detector 2 gives the respective priority number of the requesting computer via a priority separator 3 to the priority allocator 1 and to a computer detector 4.

The priority allocator 1 can only process one computer request at a time. However, since there is in principle the possibility that several computers request another computer to transfer the program at the same time, the priority separator 3 only forwards the highest of the priority numbers reported to it by the priority detector 2 to the priority allocator 1 . The simultaneous request does not need to be given by the simultaneous occurrence of several computer request signals, but also by several computer request duration signals, namely when no computer is free and the agreement regarding the interruption of the computer of the lowest priority does not exist. Unless the possibility of the described simultaneity is not given by computer request signals that can Vorrangvereinzeler 3 as well as the still to be explained more Vorrangvereinzeler 3 accounts b later.

In principle, the priority assigner 1 cannot process the numbers of computers; instead, it must always be supplied with the priority numbers of the computers in question. For this reason, the lines 165, 166 and 167 provided for the computer-free message also pass through a priority detector 2b and, if necessary, the priority separator 3b.

The computer detector 4 sends a response to the computer requesting the computer requesting it. This is necessary for the case when several computers request another computer at the same time. But only one, namely that of the highest priority, can be considered. For this, the priority separator 3 emits a signal which causes the priority reclassification in the priority allocator 1 and at the same time arrives at the computer detector 4. This now determines the computer number belonging to the priority signal and sends a signal to the computer concerned as a request to transfer the program.

When explaining the system principles, it was said that if a free computer is not available, the one with the lowest priority is to be made available to a requesting computer. However, this measure cannot be carried out if the requesting computer itself has the lowest priority. In this case there is no free computer. The requirement is not taken into account. This is achieved in a simple manner in that the priority detector 2 does not emit a priority signal for requesting computers with priority 1 (lowest priority). The absence of the feedback signal can serve as an indication to the computer making the request that it has the lowest priority and therefore cannot transfer any program parts.

But if a computer, a part of the program from another computer has been handed over for processing, itself requests a free computer again, can also be done differently. With a given program structure, it can expedient or necessary that a computer another computer that is on same main program is working, is not allowed to interrupt.

As stated several times above, if a free computer is not available, the computer with the lowest priority is made available to the computer making the request. In this case, the priority assigner 1 must be informed by the central unit5 of the number of the lower-ranked computer instead of the number of the free computer. For this purpose, a multiple line leads from connection 168 of priority allocator 1 to central unit 5, which forwards the number communicated to it in this way to the computer (see previous paragraph).

The principle of priority overriding the requested over the requesting computer is opposed to the principle of sub-arrangement. The control the system for the intended superposition is, however, simpler. Get here a computer automatically bans a request when it has the lowest precedence Has. In the case of an organization as indicated in the penultimate paragraph, all other computers assigned to the computer with the lowest priority also have Request prohibition. In the opposite case, if the requesting computer retains its priority and the requested computers are given priority subordinate new, It must be constantly checked whether a newly assigned computer has the lowest priority has or not. If the former is the case, no further computers may be requested will. Such a procedure requires something in terms of technical implementation extra effort. But it falls under the invention as well as the principle of superordinate.

The units 2 a, 3 a and 4 a of FIG. 1 are now used for the priority allocation of further units of the data processing system, such as storage and input / output units. Call z. If, for example, several computers are running such a unit at the same time, the computer with the highest priority in each case is requested by the computer detector 4a to establish a connection with the memory or input / output unit etc. called up by it. For the case of control with respect to riffs in each case only one in its availability is dependent on priority issues unit of the data processing system is the Vorrangre-clung with a Kombination2a, 3a, 4a to accomplish. However, if there are reasons against it due to the data processing system in each CD (e.g. several computers have simultaneous access to several independent storage units), each unit can of course be assigned a combination of a priority detector, priority separator and computer detector.

The technical design of Vorrangzuordners 1, Vorranadetektors 2, the Vorrangvereinzelers 3 and the computer 4 shows the detector F i g. 2.

The Vorranzzuordner 1 consists essentially of a register 111 to 144. This includes in its four sliding bodies 14, 13, 12, 11, four with respect to the sliding function jointly addressable memory locations ... 1. . . 2, ... 3, ... 4. Thus loading is the first shift position of the storage locations 141, 142, 143 and 144 so that second one of the memory locations 131, 132, 133 and 134, etc. The register is for displacing of binary vectors of four bits each. The actual circuit of the register is shown in FIG. 3 explained. This indicates the drawing symbols used in FIG. 2 on the left and the actual design as an equivalent on the right. As can be seen from it, the control lines c, c + inscribing lines, b, b + sliding line are unellar for single-digit shifting to the right and a, a + sliding lines for single-digit shifting to the left.

Each shift point takes up a computer number with its four memory cells. It is assumed that the computer numbers. in the -Code [are generally indicated. Each number thus requires four bits to represent it. If - is used in a different code to represent numbers, the number of storage cells per shift position changes. A priority number is still assigned to each shift point. From left to right, the sliding positions have the precedence 4, 3, 2 and 1 , which is also evident from the second digit of the reference numerals. According to the invention the procedure is such that a computer is assigned to the priority of his number storing memory location Thus, the multiple output lines k (priority 4), 1 (priority 3), h priority 2), and - (priority 1) of the register (s. also F i 2-1.1 ) it can be determined immediately which computer belongs to which priority. As already mentioned, this is done by the priority detector 2. In this, the register output lines k, i, h and the computer request lines 246, 247, 248, 249 form a crossbar system, the intersection points of which are occupied by AND circuits (see also F i 1-. 4). The outputs of all AND circuits in each case on a register (multiple) output line lead to an OR circuit 24, 23, 22 each. B. at the OR circuit 24 states that the computer currently issuing a computer request signal via one of the lines 246 to 249 has priority 4; his The address is therefore in the shift position 141 to 144. In accordance with what has been said above, no priority signal is issued for a computer request from a computer with the priority 1 C ZD (lowest priority). If several priority signals occur simultaneously at the outputs of the priority detector 2, C corresponding to several computer request signals on the lines 246 to 249, the priority separator 3 only forwards the priority signal of the highest priority in each case. It therefore contains the following logic: V4 = 24, V3 = 24 & 23, V2 = 24 & 23 & 22. V2, V3, V4 mean individual output signals for the priorities 2, 3 and 4, and 22, 23 and 24 denote output signals at the OR circuits of the same name of the priority detector 2.

The following control principles apply to registers 111 to 144: If a computer with priority requests a further computer, its number and that of all computers with lower priority are shifted one place to the right Priority 4 a computer request signal to the priority detector 2, then the number of the same in the shift position 131 to 134 (priority 3), the number of the computer of priority 3 in the shift position 1121 to 124 (priority 2) and that of the computer has priority 2 into the shift position 111 to 114 (priority 1) . The OR circuits 163 and 164 are provided to control all shifts to the right and the OR circuits 161 and 162 to control all shifts to the left. nale (lines 165 to 167, see also Fig . 2) If a computer with priority a sends a computer-free signal, the numbers of all computers with lower priority are increased by one elle shifted to the left; their priority is increased by the value ONE. Accordingly, the following computer-free signals arrive via lines 165 to 167 : Line 165: Computer with priority 4 is ready. Line 166: Computer with priority 3 is ready. Line 167: Computer with priority 2 is ready. After a computer request signal and the priority rearrangement caused by this by shifting the relevant numbers in the register to the right, the number of the free computer and the computer assigned to the requesting computer must be entered in the vacant shift point.

Computer numbers specified by the central unit 5 are written into shift positions via lines c, c- # of the memory cells (see FIG. 3) . The inscribing lines of the shifting points lead to inscribing circuits 151 to 154. When the inscribing signals 151+ to 154+ occur, these switch the number of the free computer specified by the central unit 5 to the inscribing lines. The write -in circuits 151 to 154 ″ are explained in FIG. 5. According to this, each write-in circuit consists of eight AND circuits, four of which have two non-negated inputs and the other four each have one negated and one non-negated input. Circuits are connected to the control line coming from the right with an unnegated input to CD C. One (input side) negated and unnegated AND circuit each lead to one of the lines 56 to 59. The two output lines of each AND circuit pair run over one of all the memory cells Shift point of the register common line harness to a memory cell of the relevant shift point (see Fig. 2), because as can be seen from Fig. 3 , each memory cell has an unnegated and a negated input (e.g. RS flip-flop) , to each of which leads one line of the double line c or c +. The output of the unnegated AND circuit (FIG . 5) associated with a memory cell is connected to the unnegi 1st input of the memory cell (F i g. 2 and 3) and the output of the respective negated AND circuit to the negated input of the memory cell.

Since each time a free shift point is to be written to, the priority of the same corresponds to the old priority of the requesting computer, a flag (not shown in the drawings) is provided which saves the priority of the requesting computer over the shift cycle and then one to the stored priority makes corresponding pulse distribution on lines 154+ to 151+. Computer with priority write-in pulse a requests the computer to line up a = 4 154+ 3 153+ 2 152+ The enrollment lines 151+ to 154+ are also used when the data processing system starts computing to enter the computer numbers in the register 111 to 144 for the purpose of assigning priority for the first time.

The computer detector 4 is constructed similarly to the priority detector 2: In it, the output lines of the priority separator 3 form a crossbar system with the register output lines k, i, h of the priority assigner 1. AND circuits (see also FIG. 4) are inserted into the crossbar system and connected to OR circuits 461 to 491. Each of these OR circuits leads to one, the computer detector output line 46 to 49. A computer receives a signal via its computer detector output line when it has a) issued a computer request signal, b) does not have the lowest priority (1) and C c) at simultaneous computer request by several computers of these has the highest priority.

Logically formulated, the computer detector b, -i outputs a signal at its outputs 46 to 49 under the following conditions, if , the following applies: Cl = -46 V4 & 141VV3 & 131VV2 & 121 C2 47 V4 & 142 V V3 & 132 V V2 & 122 C3 48 V4 & 143 V V3 & 133 V V2 & 123 C4 49 V4 & 144 V V3 & 134 V V2 & 124 Cl, C2, C3, C4 refer to the system-internal designations of computers 6, 7, 8 and 9 and should indicate that Terminal 46 is connected to computer 6 (C 1), 4.7 to computer 7 (C 2), 48 to computer 8 (C 3) and 49 to computer 9 (C 4) , 121 to 141 denote the output signals of the memory cells of the same name Re- "isters in the priority allocator 1. It is assumed that the Code corresponding to the last digits of the reference characters of the memory cells is provided for each shift position. If a different code is used to represent the computer number, the logic of the priority detector 2 and the computer detector 4 change accordingly.

A "priority 1 detector" 17 is connected to the storage cells 111 to 114 of the right shift point (priority 1). A line leads from this via the central unit 5 to each computer 6, 7, 8, 9 , each line receiving a signal whose computer has priority 1 , the number of which is therefore in the right shift position. This is important when a computer is not allowed to interrupt another computer that is working on the same main program. As in the description of FIG. 1 mentioned, these signals are used to suppress computer requests. In the case of using a Codes, the lines, terminal 168, can also be used to indicate to the central unit 5 the number of the computer with the lowest priority. If a different code is used, separate lines are to be provided for transferring the number of the computer with the lowest priority. In this case, the "Vorran-1 detector" can also be placed in the central unit 5 .

In the foregoing, a specific embodiment of the invention has been described in an example. This embodiment can be modified in many ways within the scope of the invention, both in terms of the specific technical and organizational design. In particular, all known memory cells which are equivalent to the listed memory cells in their effect can be used for the registers 111 to 144 of the priority folder 1. Because of their high functional reliability, magnetic storage cores are particularly advantageous if their switching speed is sufficiently high for the data processing system.

The above-described arrangement according to the invention fulfills all the requirements to be placed on a high-speed C multi-computer system. These are: 1. Invariance of the programs against system configurations (here computer assignments).

2. The shortest possible waiting times for the handover of the program.

3. Priorities of the computers can be specified by programs; Evaluation for time constraints by i 'circuits, not by programs. 4. Fast prioritization.

While known multi-computer systems with priority distribution by service programs for priority rearrangements require several memory cycles, the system according to the invention accomplishes the same task in only about half a memory cycle. In some cases, for reasons of better coordination and monitoring of the computers in the data processing system, it will be necessary to use a service program that is superordinate to all computers. And for a variety of reasons, even in view of the advantages of the invention given above, it can be expedient to have the service program perform the actual priority assignment. In this case, too, it is useful to save the respective priority distribution of the computers in the priority allocator 1. The computers now give all messages such as computer requests and computer free signals to the utility program. This rearranges the precedence and communicates the new precedence distribution directly to precedence allocator 1. The measures provided for driving the circuits such as the priority Vorrangzuordners detectors 2 and 2b, the Vorrangvereinzelner 3 and 3 b and the Rechnerdetekter -nen 4 Kgs #, then omitted. The measure depends on the expediency seen from the utility program. In contrast, the arrangement of the priority detector 2a, the priority separator 3a and the computer detector 4a is retained. This then decides, taking into account the respective priority distribution given by the priority allocator 1 , as before, which of the computer simultaneously requesting a unit (computer, peripheral device, etc.) receives access to the requested unit. The service program is thus relieved of this work, which means a considerable simplification of the same and a faster assignment of the corresponding unit.

Claims (1)

Claims: 1. Program-controlled data processing system with a plurality of independently working computers, each of which can transfer program parts to any other computer according to its respective program, with a common memory, which is optionally divided into several separately addressable memory blocks, with a plurality of peripheral devices such as Input / output devices and the like, and with a central switching unit that enables the computers to work together, with the peripheral devices and the memory blocks according to a priority sequence preferably determined by the computer programs, in such a way that computers with a higher priority are assigned to them is, compared to computers with low priority, a preferential access to other computers, memory blocks and peripheral devices received, d a - characterized in that to enable the transfer of program parts of a priority computer to a free Rec hner or a computer of lower priority is set in a register of the central switching unit (5) each with the number of one of several free computers or the currently lower-ranked computer, and that a priority circuit (1, 2) is provided that the indicates the respective priority number of a computer by its switch position, which lowers the respective priority number of a computer and the priority numbers of the computers with lower priority compared to this computer by the value ONE if it requests a computer that gives the requested free computer the priority number of the requesting computer and which, after a computer has become free, increases by ONE the precedence numbers of those computers which, at the time of the free notification, have lower precedence numbers than the free-registered computer. C 2. System according to claim 1, characterized in that the priority circuit (1, 2) consists of a sliding register (111 to 144) and a priority detector (2) that the sliding register (1) has as many sliding positions as the computer ( 6 to 9) are available that each shift point has as many memory locations (141 to 144, 131 to 134) as the code words indicating the computer numbers include binary digits and that each shift point is assigned a fixed priority in the sense that each computer has the Priority number of the shift position of the shiftable register storing its number is assigned to '. 3. System according to claim 2, characterized in that the priority detector (2) on a computer request, the priority of the request, t and the displacement of the computer display the number of this computer and all priority lower computers in the shiftable register by one place in the direction primarily caused by lower sliding positions. 4. System according to claims 2 and 3, characterized in that the priority detector (2) consists of a logical network whose input lines are the output lines of the shiftable register on the one hand and the computer request lines on the other hand, that the logical network has as many output lines as that shiftable register has shifting points, each shifting point being assigned an output line, and that in the case of a computer request signal from a computer, that output line emits a signal whose assigned shifting point stores the number of the requesting computer. 5. System according to claim 4, characterized in that the priority detector for the requesting computer with the lowest priority in each case does not emit an output signal. 6. System according to claims 1 to 5, characterized in that means are provided for writing the number of a free computer in a shift point of the shiftable register that has become free by a computer request, which store the priority of the requesting computer for at least one clock pulse and then the Enter the number of the free computer in the shift point of the original priority of the requesting computer. 7. System according to claims 1 to 6, characterized in that for the computer-free message the free reporting lines of the computer lead via a priority detector (2 b) to the control part (161 to 167) of the sliding register. 8. System according to claim 7, characterized in that the control part (161 to 167) is so auscrebildet that when there is a signal on a free reporting line of priority (a) the contents of the shift points with the operations a- 1, a- 2, ... be pushed into the sliding positions a-2, a-3 .... 9. System according to claims 1 to 8, characterized in that a computer detector (4) is provided which, when a signal is emitted by the priority detector (2), sends a signal c> to the computer, the priority of which is equal to that priority indicated by the priority detector. 10. System according to spoke 9, characterized in that the computer detector (4) consists of a logical network, the input lines of the Vchrrangdetektors on the one hand and the, en (k, i, h, g) of the shiftable output line register on the other hand. 11. System according to claims 1 to 10, characterized in that the priority detectors (2 to 2b) are each followed by a priority separator (3 to 3b) , each priority separator with the simultaneous output of several signals by the priority detector assigned to it only the signal with the highest priority. 12. System according to claims 1 to 11, characterized in that switching means (17) are provided which indicate the number of the lowest priority computer in the central unit (5) and that the central unit then switches this number to that of her when a computer is requested There are lines (56 to 59) leading to the shiftable register if no computer is free at the time of the computer request. 13. System according to claim 12, characterized in that the central unit (5) does not give the number of the respective lowest priority computer to the lines leading to the shiftable register if this computer has previously transferred program parts to one or more computers. 14. System according to claims 1 and 2, characterized in that means are provided which control the priority allocator (1) in accordance with a service program (151+ to 154+, 163, 164, 165, which monitors the flow of the computer programs and assigns priority) to 168), possibly with partial or complete deactivation of the other control circuits of the priority allocator, such as priority detectors (2, 2b), priority separator (3, 3b) and computer detector (4).