DE112021003053T5 - COMPUTING DEVICE AND VEHICLE CONTROL DEVICE - Google Patents

Abstract

If a comprehensive multiple parallel operation such. For example, if a deep neural network is implemented in hardware, circuit overhead of an error detection mechanism is increased. In order to solve the problems described above, the present invention proposes a computing device 1 including: large-scale multi-parallel computing elements 110 represented by a neural network; and an error detector 120 for detecting a presence or absence and a location of an error in the computing element 110, and image data processed by the computing element 110 and outputting a recognition result 3, wherein the computing element 110 in which the error detector 120 is arranged is a computing element 110 in which a change in recognition increases when an error, bit inversion or the like occurs.

Description

technical field

The present invention relates to computing devices. Among these, the present invention particularly relates to an arrangement of computing elements constituting a computing device.

Technical background

As an application example of a computing device realized by a plurality of computing elements, a neural network such as B. a deep neural network available. In addition, it is known that a convolution neural network (CNN), which is one of deep neural networks, is applied to image recognition processing, which is one type of data processing. In such image processing, it is known that the recognition accuracy is drastically improved as compared with a conventional rule-based algorithm, and practical application in various fields has progressed.

For example, in the field of automobile industry, it is conceivable to contribute to prevention of serious accidents by applying a CNN to environment recognition for driving assistance and automatic driving. As a requirement of an apparatus processing a CNN, it is required to process an image sent from a camera in a cycle on the order of tens of milliseconds at high speed. For this reason, a device equipped with an expensive GPU is required. However, due to a recent weight reduction of an algorithm and progress of an installation technique for compressing a model, an inexpensive device can be selected, and an ECU in which a CNN is installed has been put into practical use for commercial vehicles as well.

On the other hand, it is required to meet high safety and reliability standards defined in ISO 26262 or the like for in-vehicle components. That is, there is a high demand for an error rate and an error detection rate of an arithmetic circuit and software for image processing.

As means for detecting an error of a computing device in which a general combinatorial logic circuit (random logic) is mounted, the following technique is known. For example, a technique of detecting whether the output values always agree or not by a lockstep method (a duplication method) is known. In addition, a technique is known in which an error detection pattern (a test signal) for detecting an error of a computing element is input to a circuit to determine whether an output value of the circuit agrees with an expected value.

For example, Patent Literature 1 discloses a configuration in which, for the purpose of self-diagnosing the presence or absence of an error in an image processing device. storing which computational elements are used as computational elements in pipelines arranged in plural stages, and only the computational elements used are tested to generate a test pattern, thereby enabling inspection in a short time without performing an overall inspection.

Rejection list

patent literature

PTL 1: JP 2017-092757 A

Summary of the Invention

Technical problem

However, if data processing by several computing elements z. For example, in a CNN that requires large-scale plural parallel product-sum arithmetic operations, there is a problem that a circuit overhead and an investigation time for error detection increase even if the conventional technique is applied because there is no pipeline-type processing is.

In such a case z. B. a device used for calculation, such as e.g. B. a computing device expensive. In addition, the number of parallel computing elements that can be mounted on the device decreases and the data processing speed, e.g. B. the frame rate of the image processing.

The present invention has been made to solve such a problem, and an object of the present invention is to provide a computing device which can reduce the circuit overhead for error detection and reduce the cost of the device. It is to be noted that in the present specification, an error including a deficiency and a defect is expressed as an error.

the solution of the problem

An example of a computing device according to the present invention is a computing device that performs predetermined data processing on input data, the computing device including: a plurality of computing elements each performing calculation on an input and outputting a result of the calculation to realize the data processing; and an error detector that is arranged in at least one of the plurality of computing elements and detects an error of the computing element, wherein the error detector is arranged in a computing element that is determined according to an influence degree that includes a degree of influence on the data processing by a calculation result of the computing element indicates the multiple computational elements.

In addition, an example of a vehicle control device according to the present invention is a vehicle control device that outputs a control signal for controlling a vehicle based on image data, the vehicle control device including: a plurality of computing elements each performing a calculation on an input based on the image data, to realize generation of the control signal; and an error detector which is arranged in at least one of the plurality of calculation elements and detects an error of the calculation element, wherein the error detector is arranged in a calculation element which is determined according to an influence degree indicating a degree of influence on the control on the vehicle by a calculation result of the indicates a computational element among the plurality of computational elements.

Advantageous Effects of the Invention

According to the present invention, it is possible to increase the number of error detectors to be arranged, i.e. H. to prevent a circuit overhead in error detection in a computing device using a neural network or the like.

The problems, configurations, and effects other than those described above will become apparent from the description of the embodiments below.

character list

• [ 1A ] 1A 14 is a block diagram illustrating a configuration example of a computing device according to a first embodiment of the present invention.
• [ 1B ] 1B 14 is a block diagram illustrating a configuration example of a computing element (without an error detector) according to the first embodiment of the present invention.
• [ 1C ] 1C 14 is a block diagram illustrating a configuration example of a computing element and an error detector arranged in the computing element according to the first embodiment of the present invention.
• [ 1D ] 1D 12 is a block diagram illustrating a configuration example of a computing device provided with an error detector array element and an error detector array storage unit according to the first embodiment of the present invention.
• [ 1E ] 1E Fig. 12 is a diagram illustrating an example of error detector arrangement information used in the first embodiment of the present invention.
• [ 1F ] 1F 14 is a flowchart illustrating an example of processing of determining presence or absence of an error detector in the first embodiment of the present invention.
• [ 2A ] 2A 14 is a block diagram illustrating a configuration example of a computing device according to a second embodiment of the present invention.
• [ 2 B ] 2 B FIG. 12 is a diagram illustrating an example of error detector arrangement map information used in the embodiment of the present invention.
• [ 2C ] 2C Fig. 12 is a diagram illustrating an example of error detector arrangement information used in the second embodiment of the present invention.
• [ 3A ] 3A 14 is a block diagram illustrating a configuration example of a computing device according to a third embodiment of the present invention.
• [ 3B ] 3B 12 is a block diagram illustrating a diagram showing error detector arrangement information according to the third embodiment of the present invention.
• [ 4A ] 4A 14 is a block diagram illustrating a configuration example of a computing element according to a fourth embodiment of the present invention.
• [ 4B ] 4B 14 is a block diagram illustrating an example in which an error detector is arranged in an apparatus of the operation unit according to the fourth embodiment of the present invention.
• [ 4C ] 4C 14 is an enlarged view illustrating an example of a computing element in which an error detector is arranged in the apparatus of the operation unit according to the fourth embodiment of the present invention.
• [ 4D ] 4D 14 is an enlarged view illustrating an example in which functions of the operation unit apparatus are switched in the fourth embodiment of the present invention.
• [ 4E ] 4E 14 is a diagram illustrating an example of error detector arrangement information used in the fourth embodiment of the present invention.
• [ 5A ] 5A 12 is a diagram illustrating layers of neurons (computational elements 110) of a fifth embodiment of the present invention.
• [ 5B ] 5B 14 is a diagram illustrating an example of an arrangement of error detectors according to the fifth embodiment of the present invention.
• [ 6 ] 6 Fig. 14 is a diagram for explaining an application example of each embodiment of the present invention.

Description of the embodiments

In the following, embodiments of the present invention will be described with reference to the drawings. Each embodiment is an example for describing the present invention, and omissions and simplifications are appropriately made for clarity of description. The present invention can be implemented in various other forms. Unless otherwise noted, each component may be singular or plural.

Positions, sizes, shapes, ranges and the like of the respective components illustrated in the drawings and the like may not represent actual positions, sizes, shapes, ranges and the like to facilitate understanding of the invention. For this reason, the present invention is not necessarily limited to the position, size, shape, scope, etc. disclosed in the drawings and the like.

As an example of information processed in each embodiment, the terms "table" and "information" are used, however, "list", "queue" or "information" and "table" can be used. In addition, the identifier information can be read as "identifier", "name", "ID", "number" or the like.

If there are multiple elements that have the same or similar functions, the same reference numbers may be denoted with different subscripts. In addition, if it is not necessary to distinguish the plural components, the description can be made by omitting the index.

In each embodiment, processing performed by executing a program can be described. Here, the computer executes a program through a processor (e.g. CPU, GPU) and performs processing defined by the program using a storage resource (e.g. memory), an interface device (e.g a communication port) and the like. Therefore, the subject of the processing performed by executing the program can be a processor. Similarly, the subject of the processing performed by executing the program may be a controller, device, system, computer, or node having a processor. The object of the processing performed by executing the program may be an arithmetic unit and may include a dedicated circuit that performs a specific processing. Here the dedicated circuit z. a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a complex programmable logic device (CPLD), or the like.

The program can be installed from a program source in the computer. The program source can B. be a program delivery server or a computer-readable storage medium. When the program source is a program delivery server, the program delivery server may include a processor and a memory resource storing a distribution target program, and the processor of the program delivery server may distribute the distribution target program to another computer. In addition, in the embodiment, two or more programs can be realized as one program, or one program can be realized as two or more programs.

In the following, embodiments of the present invention will be described with reference to the drawings. Note that in the following embodiment, an example in which the present invention is applied to an in-vehicle ECU for vehicle control such as advanced driver assistance system (ADAS) or autonomous driving (AD) is described. However, the present invention is not limited to the in-vehicle ECUs for ADAS and AD. In addition, the present invention can be applied to general data processing such as e.g. B. Image processing can be applied. Among them, the present invention can be particularly applied to computing devices that require security, such as e.g. B. a system control can be widely applied.

<First Embodiment>

A first embodiment in which the present invention is applied to an in-vehicle ECU for ADAS and AD will be described with reference to FIG 1A until 1F described. 1A 14 is a block diagram illustrating a configuration example of a computing device according to a first embodiment.

As an example of data processing, a computing device 1 includes a computing unit 11 that performs image processing on image data 2, which is input data, and outputs a recognition result 3, which is output data. It is assumed that the arithmetic unit 11 performs a comprehensive parallel calculation such as e.g. B. CNN performs and performs processing across multiple layers, each layer comprising the compute elements 110 shown in 1B are illustrated, ie neurons arranged in parallel. Inputs 130 of the computing elements 110, e.g. B. input signals, may each be coupled to outputs 140 of the previous layer's computational elements 110, or may be coupled to only some optional outputs, and the number of neurons (computational elements 110) of each layer may be optional. As described above, the computing unit 11 includes the plurality of computing elements 110. In addition, information indicating normal/abnormal 4 which is a detection result of an error detector 120, which will be described later, is output from the computing device 1.

Additionally, as a mechanism for detecting that the computing element 110 is faulty, e.g. B. an error detector 120, which in 1C is illustrated, arranged. The error detector 120 has the following configuration. The configuration includes a test signal generation circuit 121 for generating a test signal 150 in the input unit of the computing element 110, an input side selector 122 for switching between an input 130 to the computing element and the test signal 150, and a comparator 123 for confirming whether the test signal 150 matches an expected value. An output 140 is then output from the arithmetic element 110 . In addition, a normal/abnormal signal 160 from the error detector 120 is output from the comparator 123 . This configuration is an example, and the present invention is not limited to this as long as it has a function of detecting a failure of the computing element 110 . In addition, an "arrangement" in the computing element brings about a state that can detect a failure of the computing element and includes e.g. B. a connection to the computing element. In addition, to realize the arrangement, both an arrangement using an FPGA and the like and a fixed arrangement are included as hardware, as will be described later.

Here are the computing element 110 in the present embodiment, in which the error detector. 120 is arranged and the computing element 110 is not arranged mixed. The reason why the presence or absence of the error detector is mixed will be described below. It is noted that in the present embodiment, the error detector 120 is arranged in at least one computing element 110 .

in the case of an arithmetic element in a general random logic, when a circuit element or a wiring is defective at one point (in 1 bit), a calculation result or a result of data processing deviates from an expected value and a system using the arithmetic element often has A great influence. On the other hand, in an arithmetic unit 110 including a circuit that performs a product sum operation of a large number of input signals such as B. a CNN and a rounding function such. B. has a bit shift and an activation function, even if a 1-bit error occurs, a change in a calculation result is often negligible. In addition, even if the change in the calculation result in one calculation element is large, since the calculation is performed in the next and subsequent layers containing the results of other calculation elements, the change in the expected value in the result of data processing ( the recognition result 3), which is the final calculation result, must be minute.

In addition, the operational parameters (weight, preload, etc.) of the CNN obtained by training using the training data provided for each layer and each compute element are set, are determined, different values are assigned. Since a calculation element assigned a minute value close to zero among the assigned parameters has only a minute result regardless of what data is input, it can be said that the influence of the error imparted to the calculation result and the recognition result 3 , is small.

For the above reason, the degree of influence of the error imparted to the calculation result of the computing element 110 and the data processing result of the computing device 1 differs depending on the characteristics of the algorithm itself and how the operation parameters are assigned (result of learning). The degree of influence is studied in advance during designing of the CNN, a calculation element having a large influence on the calculation result is determined, and the error detector 120 is arranged with respect to the calculation element.

In order to realize this, in the present embodiment, as in 1D 1, an error detector array element 101 and an error detector array storage unit 102 are provided. That is, the error detector arrangement element 101 determines the arrangement of the error detectors 120 based on error detector arrangement information 1021 stored in the error detector arrangement storage unit 102 . The function of the error detection array element 101 is processing according to a program, but the function can be realized as hardware. It is to be noted that in each embodiment described later, according to the computing device 1 shown in FIG 1A and 1D is illustrated can be used as a vehicle control device.

Illustrated here 1E an example of the error detector arrangement information 1021. The error detector arrangement information 1021 includes “calculation element” that is identification information for identifying the calculation element, “degree of influence” that indicates the influence of the calculation result of the calculation element given to the recognition processing, and “ the presence or absence of an arrangement” of the error detector 120. For example, use a name other than a number.

Here, the degree of influence is an index that is calculated by a predetermined algorithm and indicates the degree of influence on the data processing of the computing device 1 by the calculation result of the computing element. Therefore, the degree of influence includes an item that is determined according to a result of data processing, which will be described later, and/or control according to the result of data processing. This enables appropriate error detection according to the data processing and application goal of the computing device 1.

Specifically, the degree of influence includes a degree of deterioration (a recognition accuracy) that is a degree of change in a recognition result as a result of data processing, and an item that is determined according to the influence of the recognition result on the control result of the vehicle. As described above, the degree of influence indicates the degree of influence on data processing by a calculation result of a computing element or the like.

Note that in the present embodiment, the threshold of the degree of influence is stored as "0.5", and when the threshold is exceeded, it is determined that "the presence or absence of an arrangement" is ordered, that is, H. the error detector 120 is arranged in the corresponding computing element 110 . On the other hand, when the degree of influence is equal to or smaller than the threshold value, it is determined that "the presence or absence of an arrangement" is not present, i. H. the error detector 120 is not located in the corresponding computing element 110 . In addition, the error detector arrangement information 1021 does not have to include the “degree of influence”.

Furthermore, the “presence or absence of an arrangement” can be determined by combining multiple requirements. For example, it can be determined based on a product, a sum, or the like of the degree of change in the recognition result and the degree of influence of the recognition result on the control result of the vehicle. In addition, the degree of influence may be recalculated using both the degree of change in the recognition result and the degree of influence of the recognition result on the control result of the vehicle. Moreover, each of them can be used such that it is determined that the failure detector is arranged when both the degree of change in the detection result and the degree of influence of the detection result on the control result of the vehicle exceed a threshold.

It is to be noted that the arrangement of the error detector 120 is the same regardless of the error detector arrangement element 101 and the error detectors a Arrangement memory unit 102 can be determined manually. In addition, the error detector array element 101 and the error detector array storage unit 102 may be provided in a device other than the computing device 1 . In this case, it is desirable to provide them in a designing device or a manufacturing device of the computing device 1 and to determine the presence or absence of the arrangement of the error detector 120 during the designing or the manufacturing. The processing in this case will be described with reference to a flow chart shown in 1F is illustrated.

First, in step S1, the design device reads in a learning image stored in advance according to the designer's operation and performs learning, i. H. a parameter update. Next, in step S2, the design device evaluates the accuracy based on the result of the learning, i. H. the accuracy of image processing using the inference image stored in advance. This evaluation serves to determine an index display performance, i. H. calculate an accuracy of the computing device determined by a predetermined algorithm. Then steps S1 and S2 are repeated until the accuracy meets a certain norm or a predetermined number is reached.

Next, in step S3, the design device carries out error injection at the place (the calculation element) at which the degree of influence is to be examined based on the conclusion image. Then, in step S4, the design device evaluates the degree of influence of each calculation element. That is, the design device calculates the degree of influence, as in 1E is illustrated and determines the presence or absence of the placement of the error detector in the computing element. Using this result, the defect detector is placed in the manufacturing device. It is to be noted that steps S3 and S4 are repeated until an error portion (an arithmetic element) for which examination of the degree of influence is desired ends.

Next, an example of the arrangement of the error detector 120 will be described below. As described above, one of the methods for determining the degree of influence of an error in the CNN for image processing is to evaluate the degree of change in the recognition result as described above. In the simplest evaluation method in this example, the recognition accuracy is calculated from the inference result when the image data is input to the learned CNN for inference. The recognition accuracy can e.g. B. by the coordinates of the bounding box of the vehicle in which the object is detected and by how much difference the size has from the correct value. A threshold is defined in terms of how much the value of the recognition accuracy deteriorates at the time of failure, and the computing element 110 that deteriorates more than the threshold or the device of the operation unit constituting the computing element becomes a reference for arranging the error detector 120. That is, in the present example, the degree of deterioration indicating the detection accuracy is used as the degree of influence.

Note that in this case, the degree of change in the result of the recognition processing that occurs when an error and/or bit inversion of the computing element 110 occurs can be used as the degree of degradation.

In addition, it is also conceivable to use, as the influence degree, an evaluation criterion considering not only the accuracy of a recognition but also the influence of the recognition result due to the error on the ADAS and AD applications. Specifically, a view is whether a change in the bounding box of the recognition result due to an error leads to sudden control. That is, in the image during driving, it is considered that there is no influence on the control due to erroneous detection far from the host vehicle (if it is recognized that there is detection although there is no detection) or a minute change in the bounding box. On the other hand, if erroneous detection occurs a few meters in front of the host vehicle due to an error, there is a possibility of leading to an emergency control such as B. sudden braking or sudden steering. It can be said that it is desirable to dispose the error detector 120 for the error section (the computing element 110) having an influence like the latter. That is, in the present example, whether or not the given control is executed is also used as the degree of influence. As an example, the possibility of executing a predetermined control as the degree of influence in a plurality of assumed scenes through simulation or the like can be used. In addition, the given control includes emergency control including sudden steering and sudden braking when the computing device 1 outputs a control signal of the vehicle. In this case, the error detector 120 is arranged in the arithmetic unit 110 that performs a calculation that causes the emergency control. As a result, a Failure protection control can be implemented in ADAS and AD.

If such the present embodiment is actually applied, a definition of what kind of erroneous detection/non-detection has a large influence on the control is obtained from a driving locus such as a road. an expressway or an urban area, a host vehicle speed, a degree of congestion around vehicles, and the like, and a reference is made.

<Effects of the first embodiment>

As a configuration in the case of performing error detection of the computing device, the error detector is preferably arranged in a portion that has a high degree of influence on the detection result, and thereby the number of error detectors can be reduced, high security can be ensured, and device costs can be suppressed .

<Second embodiment>

In view of the influence on the recognition result, when the failure of the computing element 110 occurs fixedly, a countermeasure can be taken as in the first embodiment. Here, even in the computing elements 110 in which the error detector 120 is not arranged, if some of them are defective, the influence on the calculation result increases and thus a countermeasure is required. Therefore, in a second embodiment, it is possible to detect an error also for a computing element 110 which is determined to have a small influence of the error and in which the error detector 120 is not arranged. Therefore, in the second embodiment, the computing element in which the error detector 120 is arranged is dynamically changed. In other words, error detector 120 is dynamically relocated with respect to compute element 110 . As described above, in the second embodiment, the arrangement relationship between the error detector 120 and the computing element 110 is dynamically changed. The details are described below.

First illustrated 2A a configuration of the computing device 1 of the present embodiment. As in 2A As illustrated, the computing device 1 of the present embodiment includes a computing unit 11, an error detector reconfiguration element 12, a

error detector arrangement planning device 13 and an error detector arrangement planning unit 14. The arithmetic unit 11 includes a plurality of arithmetic elements 110. Here, the functions of the error detector reconfiguration element 12 and the error detector arrangement planning device 13 are processed according to a program, but the functions may be implemented as hardware.

Here, when a placement replacement trigger 6 is received, the failure detector placement planning device 13 issues an instruction to the failure detector reconfiguration item 12 to perform rearrangement (configuration) according to failure detector placement plan information stored in the failure detector placement planning unit 14 . Therefore, the error detector reconfiguration element 12 rearranges the error detector 120 according to the error detector arrangement plan information. It is noted that although it is in 2A is not illustrated, the present embodiment may also include an error detector array element 101 and an error detector array storage unit 102 similarly to the first embodiment. in this case, the error detector reconfiguration element 12 and the error detector arrangement planning unit 14 may have the functions of the error detector arrangement element 101 and the error detector arrangement storage unit 102, respectively. In the following, the present embodiment will be described on the assumption that the error detector arrangement planning unit 14 has the function of the error detector arrangement storage unit 102 .

Details of the present embodiment are described below. First, the error detector arrangement planning unit 14 stores error detector arrangement plan information 141 contained in 2 B are illustrated. In accordance with this content, the error detector reconfiguration element 12 rearranges the error detector 120 . It should be noted that for this purpose the computing device 1 is desirably a reconfigurable device such as e.g. B. is an FPGA.

Here, the error detector arrangement plan information 141 is planned by the error detector arrangement planning device 13 using the error detector arrangement information 1021 of FIG 2C (same as 1E) created. For this purpose, the error detector arrangement planner 13 first sets comparison level calculus of influence degree, ie, Nos. 3 to 5, 7, 10 and M, which are calculus of the threshold value or less, in the error detector arrangement information 1021 . Then, the error detector arrangement planner 13 stores the identification information of these calculation elements in the Calculation elements (threshold value or less) that have a low degree of influence of the error detector arrangement plan information 141 . Here, in the present embodiment, the identification information of the error detector arrangement information 1021 is used, but it can be assigned again. Then, the error detector arrangement planner 13 replaces the computing element in which the error detector 120 is arranged for each time, and records the replacement in the error detector arrangement information 1021 . It is to be noted that in 2 B The presence or absence of the arrangement is determined for each time, however, a trigger other than time can be used. As described above, in the present embodiment, the computing element 110 in which the error detector 120 is arranged changes periodically.

In the following, details of the exchange, i. H. the arrangement conversion, which is the reconfiguration of the error detector 120, will be described. First, it is assumed that the number of calculation elements in which no error detector is arranged is N (where N is a natural number). Here, when n is defined as a replacement detection number, it is assumed that the error detector 120 is arranged for n calculation elements (e.g., the upper n of the error detector arrangement plan information 141). For example, when n=2, the failure detector arrangement planner 13 records “arrangement” in Nos. 3 and 4 at time = t.

Here n<N and n is also a natural number. At this time there is no error detector in the computing elements other than those described above (#5 and subsequent numbers in 2 B) arranged.

Next, the error detector placement scheduler 13 instructs the error detector reconfiguration element 12 to place the error detector 120 in the compute elements #5 and #7 at a timing specified by the placement exchange trigger 6, such as: B. Waiting for a signal or initialization when the engine is turned on. At this time, the error detector arrangement planner 13 does not arrange the error detector 120 in the calculation elements #3, #4 and #10 except for #5 and #7. According to this command, the error detector reconfiguration element 12 replaces and reconfigures the arrangement of the error detectors in the arithmetic unit.

The error detector arrangement scheduler 13 repeats such replacement of the arrangement of the error detectors, that is, arrangement conversion, every time the arrangement exchange trigger 6 is received. When this has been repeated x times, the computational elements up to #M are covered. Here, a relationship of n * x > N (x is also a natural number) holds. Note that in the (x+1)-th arrangement conversion (one round), the process returns to the first arrangement. As a result, as in 2A is illustrated, “Computing element has a small influence on the recognition result. Error detector is not arranged at the time of the diagram", "Calculation element has a small influence on the detection result. Error detector is placed at the time of the diagram" and "Calculation element has a large influence on the detection result. Error Detector Array Target” side by side. That is, the error detector 120 is arranged for at least one computing element and the error detector 120 is not arranged for at least one of the other computing elements.

Furthermore, in the example described above, the error detectors are replaced by the constant number (n=2), but this number can be variable. However, the error detector arrangement planner 13 sets an upper limit not to exceed the total number of error detectors 120 . In addition, the number of placements of the error detector 120 of “computational element having a small influence on the detection result” is the same in each round of placement conversion, but may be variable. For example, the error detector arrangement planning device 13 can increase the number of arrangements of a computing element that has a greater degree of influence of the error detector arrangement information 1021 . In this case, the failure detector placement planner 13 desirably determines the number of placements in relation to the degree of influence.

In addition, the defect detector arrangement plan information 141 indicating this arrangement may be programmed based on a counter or a mathematical expression, or may be stored in the defect detector arrangement plan unit 14 in the form of a table or the like, as shown in FIG 2 B is illustrated. Additionally, as described above, the arrangement translation trigger may wait for a signal turning on the engine or use any cycle.

<Effects of the second embodiment>

According to the present embodiment, reliability can be achieved even for a computing element having a low degree of influence such as e.g. B. has a sensitivity of a 1 bit error, ie a Computing element in which the error detector 120 is not arranged can be ensured.

<Third embodiment>

Next, a third embodiment will be described in which the error detector 120 is arranged according to various situations and environments. Vehicles often drive under various driving environments such as B. Time zones and locations (roadways, etc.). Therefore, it is necessary to perform control suitable for the environment also in ADAS and AD for the vehicle. At this point in time, the degree of influence of a very sensitive neuron, i. H. of the computing element 110, may be different for each environment. Here, when the error detector 120 is arranged corresponding to each assumed environment, the numerical value of the degree of influence is high and the sensitivity for each computing element is high as a whole, and the difference is hardly generated. Therefore, there is a problem that the number of calculation elements to be arranged increases. That is, there is an overhead in arranging the error detector 120 .

Therefore, in the present embodiment, the degree of influence of the computing element is calculated for each environment and stored in the error detector array storage unit 102 of FIG 3A is stored and the arrangement of the error detector 120 is determined using the calculated degree of influence. This is detailed below, but the environment also includes a scene, situation, condition, time zone, weather, position, and the like.

First illustrated 3A A configuration of a computing device 1 of the present embodiment. As in 3A As illustrated, the computing device 1 of the present embodiment includes an error detector reconfiguration element 12, an environment determination device 15 and an error detector arrangement storage unit 102 in addition to the computation unit 11. The functions of the error detector reconfiguration element 12 and the environment determination device 15 are processing according to a program, but the functions can be hardware be implemented.

It is noted that although it is in 3A is not illustrated, the present embodiment may also include a failure detector array element 101 and a failure detector array planning unit 14 similarly to the first and second embodiments. In this case, the error detector reconfiguration element 12 and the error detector arrangement storage unit 102 may have the functions of the error detector arrangement element 101 and the error detector arrangement planning unit 14, respectively. That is, for the first to third embodiments, the functions can be implemented in combination. Moreover, each of these parts may be provided in an external device of the computing device 1 as in the first and second embodiments.

Here, the error detector arrangement storage unit 102 has a storage function similar to that of the first embodiment, but it is different from the first embodiment in that the error detector arrangement information 1021 is stored for each environment. That is, the error detector arrangement storage unit 102 of the present embodiment stores all error detector arrangement information such as e.g. B. the error detector arrangement information 1021-1 of the environment 1 (expressway) and the error detector arrangement information 1021-2 of the environment 2 (urban area) ... which are in 3B are illustrated. In addition, although not illustrated, the environment of the error detector arrangement information 1021 may include time zones such as e.g. B. night and day, weather such. e.g. good weather and rainy weather and a position/area such as e.g. B. contain a city area and a suburb.

The processing of the present embodiment will be described below. First, the environment determination device 15 reads in a condition 5 related to imaging and driving. Here, the environment determination device 15 may determine the environment based on the inputted condition 5, or may use a result determined as the condition 5 by an external computing device as the environment.

Next, the environment determination device 15 outputs the environment as the determination result to the error detector reconfiguration element 12 . Then, the error detector reconfiguration element 12 sets the error detector arrangement information 1021 corresponding to the received environment. For example, when the environment is an “expressway”, the error detector reconfiguration element 12 sets the error detector arrangement information 1021 - 1 for the error detector in the environment 1 . Then, the error detector reconfiguration element 12 arranges the error detector 120 using the error detector arrangement information 1021-1.

In addition, when it is detected that the environment changes according to the entered Condition 5 has changed, the environment determination device 15 outputs the fact to the error detector reconfiguration element 12 . Then, the error detector reconfiguration element 12 rearranges the error detector 120 in the arithmetic unit 11 with reference to the error detector arrangement information 1021 in the error detector arrangement storage unit 102 . Therefore, the computing device 1 is desirably a reconfigurable device such as e.g. an FPGA. Note that the environment determination device 15 may output the change in environment when the vehicle is in a stopped state, e.g. B. waiting for a traffic light, or when the vehicle is in a running state at a low speed (a situation where safety is assured). In addition, the error detector reconfiguration element 12 can perform reconfiguration in the state described above.

<Effects of the third embodiment>

Since the failure detector 120 can be arranged according to various driving environments, vehicle control can be performed according to the driving environment.

<Fourth embodiment>

In the first to third embodiments, the error detector 120 is arranged in units of neurons, ie, arithmetic elements 110, but in a fourth embodiment, it is further determined whether to arrange the error detector 120 for the operation unit device therein. The operation unit apparatus includes an integrator 111 and the like as will be described later. It is known that the CNN has a configuration that in 4A illustrated has an example of an arithmetic configuration of a neuron (a calculation element 110). That is, each of the arithmetic elements 110 constituting the arithmetic unit 11 includes operation unit devices such as B. an integrator 111, a cumulative adder 112, a bit shift (rounding) 113, a bias coefficient adder 114 and an activation function arithmetic element (ReLU arithmetic element) 115. Here, in such a configuration, the values of the weight and the bias coefficient are in general for each neuron different. Therefore, it is also possible to calculate the degree of influence for each device of the operation unit in the neuron in addition to calculating the degree of influence for each neuron (each computing element 110) based on the values of the weight and the bias coefficient. In the present embodiment, the degree of influence is calculated for each device of the operation unit, and the error detector 120 is arranged in the computing element 110 having a high degree of influence, such as e.g. Am 4B is illustrated, whereby circuit overhead can be further held down. Processing for this purpose is described below.

The configuration of the present embodiment can be realized by any one of the first to third embodiments or a combination thereof. Here, the configuration of the first embodiment, ie, the configuration of 1D , described as an example. However, as the error detector arrangement information 1021, the error detector arrangement information 1021-3 shown in 4E are illustrated, used. Here, the error detector arrangement information 1021-3 stored in 4E 1, the degree of influence for each operation unit of each computing element constituting the computing device 1 is illustrated. Then, the error detector arrangement element 101 determines the arrangement of the error detector 120 based on the error detector arrangement information 1021-3 stored in the error detector arrangement storage unit 102 through the processing described above.

The description of the processing of determining the arrangement of the error detector 120 according to the present embodiment ends. Next, a response if an error is detected in the device of the operation unit will be described.

First, as in 4B 1, assume that the error detectors 120 for the operation unit device are arranged based on the error detector arrangement information 1021-3. Among them, since the degrees of influence of an integrator 1 and an integrator F are larger than the threshold in the upper left calculation element 110-1 (No. 1), as in FIG 4E 1, the error detectors 120 are located therein. An enlarged view of computing element 110-1 is shown in FIG 4C illustrated.

Here, the error detector array element 101 is informed by the error detector 120 of the integrator #1 that the integrator 1 is in error. Next, the error detector array element 101 sets an integrator in which the error detector 120 is not arranged using the error detector array information 1021-3. Then the error detector array element 101 sets an integrator under a predetermined condition such as e.g. B. one that has the smallest degree of influence among the integrators. This is because it can be determined that the smaller the degree of influence, the smaller the influence is even if the integrator 1 is replaced with the integrator 1 which is a defective device of the operation unit.

As a result, it is assumed in the present example that the error detection array element 101 designates an integrator 2 . Then, the error detector arrangement element 101 exchanges the functions of the integrator 1 and the integrator 2 with respect to the calculation element 110 and issues an instruction to arrange the error detector 120 to the integrator 2. As a result, the computing element 110-1 is configured as shown in 4D is illustrated. Therefore, also in the present embodiment, the computing device 1 is desirably a reconfigurable device such as e.g. an FPGA.

It is noted that the error detection array element 101 first swaps the functions of the integrator 1 and the integrator 2 each time an error is detected, and causes the integrator 1 and the integrator 2 to perform alternative processing. Then, if this alternative processing has been performed a certain number or more, the error detector arranging element 101 issues an instruction to arrange the error detector 120 . Further, when the number of alternative processings is a certain number or more, the error detector arrangement element 101 desirably gives warning information to an external device such as a computer. B. an in-vehicle terminal.

Further, it is desirable that the error detecting array element 101 is a device of the operation unit whose function is switched from those that meet a predetermined condition such as e.g. B. selects a neighboring device.

It is to be noted that this processing can be similarly performed also in the first to third embodiments. That is, it is also possible to replace the processing of the computing element in which the error is detected with that of another computing element for processing.

<Effects of the fourth embodiment>

By performing the arrangement in the device of the operation unit, it is possible to more precisely arrange the error detector with respect to the computing element. In addition, even if an error is detected, it is possible to prevent the system from entering the degeneration mode or the stop mode directly, and it is possible to stop the operation of the system such as e.g. B. to safely continue vehicle control for a while.

<Fifth embodiment>

Next, a fifth embodiment will be described in which the error detector 120 is commonly arranged for each type of device of the operation unit constituting each of the computing elements 110 arranged in parallel.

in the arithmetic device 1, there is a case where the calculation of each neuron (arithmetic element 110) cannot be implemented in one device due to a limitation of circuit resources. For example, in a network in which layers in which neurons are arranged are continued, as in 5A illustrated, the following configuration is provided. That is, the arithmetic configuration of a neuron (an arithmetic element 110) includes an integrator 111, a cumulative adder 112, a bit shift (round) 113 which is a rounding arithmetic element, a bias coefficient adder 114, an activation function arithmetic element (ReLU arithmetic element) 115 and the like. In this case, the combination of the input data, the weight and the value of the bias coefficient is different for each neuron. In such a calculation apparatus 1, K calculation elements 110 are mounted in the frame line on the calculation unit 11, and when the calculation is completed, the weights are switched to the weights of the next Ks calculation units 11 to perform the calculation. In such a case, since the same computing element is used continuously only by changing parameters, the arrangement of the error detector cannot be determined by the degree of influence of the weight or the preload coefficient on the calculation result.

On the other hand, it can be defined by the type of the device of the operation unit, which due to the algorithmic properties has a high degree of influence on the error. For example, the cumulative adder is 112 in 5B a portion that has high sensitivity because the influence of the error is accumulated. In addition, since the activation function arithmetic element (ReLU arithmetic element) 115 outputs a negative value of zero and the other values as they are, it can be said that the sensitivity of the sign bit, ie the degree of influence, is relatively high. Therefore, the present embodiment has a configuration in which the error detector 120 is arranged in advance with respect to these operation unit devices. Note that the configuration of the present embodiment can be realized by any one of the first to fourth embodiments or a combination thereof. Here the configuration of the first embodiment, ie the configuration of 1D , described as an example.

For this purpose, the error detector array element 101 uses configuration information of the computing element 110 that has been stored in advance. This configuration information defines the presence or absence of an arrangement for each device of the operation unit. For this reason, it is determined that the devices of the operation unit to be arranged are determined by the error detector arrangement element 101 and the error detectors 120 are arranged with respect thereto. Here, the error detector arrangement element 101 can determine to arrange the error detector 120 shared by the same type of devices of the operation unit. That is, as in 5B As illustrated, the error detector 120 shared by the plurality of cumulative adders 112 is arranged. As described above, the arrangement of the shared error detector 120 can also be carried out in the first to fourth embodiments.

As described above, in the present embodiment, the error detector 120 is z. B. in the cumulative adder 112 or a predetermined device of the operation unit such. B. a sign bit of rounding, a bias adder or the like (which are not illustrated) arranged.

<Effects of the fifth embodiment>

According to the present embodiment, the error detector 120 can be efficiently arranged even in a computing device device having a relatively small circuit resource.

<Combination of the First to Fifth Embodiments>

This is the end of the description of the first to fifth embodiments. Note that the processing of each embodiment can be executed independently or can be realized by combining at least two of them.

<Application example of the first to fifth embodiments>

Next, an application example regarding the arrangement of the error detector 120 of the first to fifth embodiments will be explained with reference to FIG 6 described. Note that in the present example, an example in which the computing device 1 is applied to an in-vehicle control device called an in-vehicle ECU is described, however, the first to fifth embodiments can be similarly applied to an in-vehicle control device. In the present application example, a control result is learned in a vehicle 3000, and this result is fed back to activities in a design and manufacturing department. In the following, the processing with the configuration of the first embodiment, that is, the configuration of 1D described as an example. However, the present application example can be realized by any one of the first to fifth embodiments or a combination thereof.

First contains in 6 a vehicle 3000, a vehicle control device 1A-1, and a communication device 3001, which can be realized by the computing device 1. These components are connected to each other by means of a communication path. In addition, it is assumed that the vehicle control device 1A-1 has the configuration of 1D owns.

Here, the failure detector array element 101 of the vehicle control device 1A-1 performs the processing of each embodiment. Furthermore, the error detector array element 101 performs at least one of steps S1 to S4 in 1F in order using the processing result and the control result of the vehicle control device 1A-1. Then, the error detecting arrangement element 101 sends its own processing result via the communication device 3001 to a server device 1000 used in the design/manufacturing department.

Here, the server device 1000 is realized by what is called a computer, and executes a processing device such as a computer. For example, a CPU executes processing according to a program. Then, the server device 1000 performs the remaining processing of steps S1 to S4 of 1F using the processing result of the error detector arranging element 101, and stores the result in a file system 4000. Note that if the error detector arranging element 101 executes steps S1 to S4, the server device 1000 returns the result in File system 4000 stores. It should be noted that the file system 4000 only needs to be able to store information and inside or outside. of the server device 1000 may be provided. Then, the design and manufacture are performed by reflecting the result to manufacture the vehicle control device 1A-2.

Therefore, it is possible to realize a more realistic arrangement of the failure detector 120 reflecting the result of actual control.

Reference List

1

computing device

11

unit of account

12

Error detector reconfiguration element

13

Error detector layout planning device

14

error detector placement planning unit

15

environment determination device

102

error detector array memory unit

110

element of calculation

111

integrator

112

Cumulative adder

113

Bit Shift (Rounds)

114

bias coefficient adder

115

Activation Function Calculator (ReLU Calculator)

120

error detector

121

test signal generation circuit

122

selection device

123

comparator

130

input

140

output

150

test signal

160

Normal/abnormal signal

170

Scope of computing elements that can be mounted on a device

2

image data

3

recognition result

4

Normal/Abnormal

QUOTES INCLUDED IN DESCRIPTION

This list of documents cited by the applicant was generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Patent Literature Cited

• JP 2017092757 A [0007]

Claims (14)

A computing device that performs predetermined data processing on input data, the computing device comprising: a plurality of computing elements each performing computation on an input and outputting a result of the computation to realize data processing; and an error detector disposed in at least one of the plurality of computing elements and detecting an error of the computing element, wherein the error detector is arranged in a computing element that is determined according to an influence degree indicating a degree of influence on data processing by a calculation result of the computing element among the plurality of computing elements. computing device claim 1 wherein the predetermined data processing is recognition processing on the input data, and the degree of influence is determined according to an influence of a calculation result of the computing element given to a recognition result of the recognition processing and/or a control according to the recognition result. computing device claim 2 , wherein the degree of influence indicates an influence given to a recognition result of the recognition processing by a calculation result of the calculation element and is determined according to a degree of change of a result of the data processing that occurs when an error and/or a bit inversion of the calculation element occurs. computing device claim 2 wherein the computing device is a computing device that reads in image data and outputs a control signal for controlling a vehicle, the degree of influence is determined by an influence given to a control according to the recognition result by a calculation result of the computing element, and the error detector is arranged in a computing element , which causes an emergency control of the vehicle by the control signal. computing device claim 4 further comprising: an environment determination device that determines a photographing environment for photographing the image data; and an error detector arrangement storage unit that stores a presence or absence of arrangement of the error detector for each of the photographing environments, the error detector being arranged according to the photographing environment determined by the environment determination device using the error detector arrangement storage unit. Computing device according to one of Claims 1 until 5 , wherein a computing element in which the error detector is arranged is dynamically changed according to a predetermined condition. computing device claim 6 , wherein the computing element in which the error detector is located is changed periodically. computing device claim 6 , wherein a function of a computing element in which the error detector is arranged and a function of a computing element in which the error detector is not arranged are reversed. computing device claim 8 , wherein when the error detector detects an error of a computing element in which the error detector is arranged, a function of the computing element in which the error is detected and a function of the computing element in which the error detector is not arranged are reversed. computing device claim 9 wherein the computing device is a computing device that reads in image data and outputs a control signal for controlling a vehicle and terminates control to the vehicle when the number of computing elements whose functions have been exchanged exceeds a predetermined threshold. A vehicle control device that outputs a control signal for controlling a vehicle based on image data, the vehicle control device comprising: a plurality of computing elements each performing computation on an input based on the image data to realize generation of the control signal; and an error detector disposed in at least one of the plurality of computing elements and detecting an error of the computing element, wherein the failure detector is arranged in an arithmetic element determined according to an influence degree indicating a degree of influence on the control on the vehicle by a calculation result of the arithmetic element among the plurality of arithmetic elements. Vehicle control device claim 11 , wherein the error detector is arranged in a computing element which causes an emergency control of the vehicle by the control signal. Vehicle control device claim 11 or 12 wherein when the error detector detects an error of a computing element in which the error detector is arranged, a function of a computing element in which the error is detected and a function of a computing element in which the error detector is not arranged are exchanged. Vehicle control device Claim 13 wherein when the number of compute elements in which the functions are exchanged exceeds a predetermined threshold, control to the vehicle is terminated.

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