DE112021000647T5 - ACOUSTIC WAVE RF RESONATORS INTEGRATED IN HIGH ELECTRON MOBILITY TRANSISTORS INCLUDING COMMON PIEZOELECTRIC/BUFFER LAYER AND METHODS OF FORMING SAME - Google Patents

Abstract

An RF integrated circuit device may include a substrate and a high electron mobility transistor (HEMT) device on the substrate including a ScAlN layer configured to provide a buffer layer of the HEMT device to form a 2DEG channel region of the HEMT device. An RF piezoelectric resonator device may be provided on the substrate including the ScAlN layer sandwiched between an upper electrode and a lower electrode of the RF piezoelectric resonator device to provide a piezoelectric resonator for the RF piezoelectric resonator device.

Description

The present application claims the priority of U.S. Patent Application No. 62/963,915 entitled Transistor BAW (TBAW) Filter Monolithic Integration filed with the USPTO on January 21, 2020 and this application claims priority to U.S. Patent Application No. 16/990,638 ; filed with the USPTO on August 11, 2020, which is a continuation-in-part of the U.S. Patent Application No. 16/822,689 is; filed with the USPTO on March 18, 2020, which is a continuation of the U.S. Patent Application No. 16/433,849 is; filed with the USPTO on June 6, 2019, which is a continuation of the U.S. Patent Application No. 15/784,919 is; filed October 16, 2017, now U.S. Patent 10,355,659 , which is a continuation-in-part of patent application Ser. No. 15/068,510; filed with the USPTO on March 11, 2016, now U.S. Patent No. 10,217,930 , the entire disclosure of which is incorporated herein by reference in its entirety.

STATE OF THE ART

Piezoelectric-based semiconductor resonator devices have been developed to act as filters and oscillators in integrated circuit devices. For example, it is known to use a piezoelectric material surface acoustic wave resonator or a piezoelectric material bulk acoustic wave resonator as part of a filter in a mobile communication device.

High Electronic Mobility Transistors (HEMTs) are used as amplifiers in RF applications. For example, HEMT devices are further described in U.S. Patent Application Publication No. US2015/0028346 discussed, the disclosure of which is incorporated herein by reference.

EXECUTIVE SUMMARY

An RF integrated circuit device may include a substrate and a high electron mobility transistor (HEMT) device on the substrate including a ScAlN layer configured to provide a buffer layer of the HEMT device to form a 2DEG channel region of the HEMT device. An RF piezoelectric resonator device may be provided on the substrate including the ScAlN layer sandwiched between an upper electrode and a lower electrode of the RF piezoelectric resonator device to provide a piezoelectric resonator for the RF piezoelectric resonator device.

character list

• 1A 12 is a schematic cross-sectional representation of a monolithic RF BAW piezoelectric resonator and HEMT device with a shared Sc _x Al _1-x -N layer, which in some embodiments according to the present invention comprises the piezoelectric layer in the piezoelectric resonator and the buffer layer in the HEMT device.
• 1B FIG. 12 is a circuit diagram showing the RF BAW monolithic piezoelectric resonator and HEMT device of FIG 1A in some embodiments according to the present invention.
• 2 FIG. 12 is a detailed cross-sectional view of a portion of a HEMT stack of semiconductor materials in section A of FIG 1A with the Sc _x Al _1-x N shared layer as the barrier layer in some embodiments according to the present invention.
• the 3A until 24D 12 are cross-sectional views showing a transfer process for forming the RF BAW monolithic piezoelectric resonator and the HEMT device including the Sc _x Al _1-x -N shared layer of FIG 1A using a sacrificial layer to form a resonator cavity and a HEMT cavity with parasitic capacitance in some embodiments according to the present invention.
• the 25A until 36D 12 are cross-sectional views showing a transfer process for forming the RF BAW monolithic piezoelectric resonator and the HEMT device including the Sc _x Al _1-x -N shared layer of FIG 1A using a patterned support layer to form a resonator cavity during bonding and a HEMT cavity with parasitic capacitance in some embodiments according to the present invention.
• the 37A until 47D 12 are cross-sectional views illustrating a transfer process for forming the monolithic RF BAW piezoelectric resonator and HEMT device including the Sc _x Al _1-x -N shared layer with a multilayer mirror in some embodiments according to the present invention.
• 48 Fig. 12 is a schematic cross-sectional view of a monolithic RF SAW piezoelectric resonator and HEMT device device with a shared Sc _x Al _1-x -N layer providing the piezoelectric layer in the piezoelectric resonator and the buffer layer in the HEMT device in some embodiments according to the present invention.
• 49 Figure 12 is a schematic representation of a transmit module including a BAW filter, an amplifier implemented using at least one HEMT device, and a switch implemented using at least one HEMT device, which in some embodiments according to the present invention are in an integrated form factor are mounted, included.
• 50 Figure 12 is a schematic representation of a Partial Complete Front End Module (CFE) high band device that includes a BAW filter, an amplifier implemented using at least one HEMT device, and a switch implemented using at least one HEMT device. Devices mounted in an integrated form factor in some embodiments according to the present invention.
• 51 is a schematic representation of a switched bank of duplexers that includes at least one BAW filter and at least one switch (implemented using at least one HEMT device, such as a bypass switch or a multi-throw switch, which in some embodiments are assembled in an integrated form factor according to the present invention.
• 52 is a schematic representation of an antenna switching module including at least one BAW filter and at least one switch (implemented using at least one HEMT device, such as a bypass switch or a multi-throw switch, which in some embodiments according to of the present invention are assembled in an integrated form factor.
• 53 12 is a schematic representation of a diversity reception FEM that includes at least one low-noise amplifier implemented using at least one HEMT device, at least one BAW filter, and at least one switch implemented using at least one HEMT device , which in some embodiments according to the present invention are assembled in an integrated form factor.
• 54 Figure 12 is a schematic representation of a power amplifier duplexer (PA duplexer) including at least one power amplifier implemented using at least one HEMT device and at least one BAW filter assembled in an integrated form factor in some embodiments in accordance with the present invention are.

DETAILED DESCRIPTION OF ACCORDING TO THE INVENTION

EMBODIMENTS

According to the present invention, techniques are provided that generally relate to electronic devices. In particular, the present invention provides techniques relating to a manufacturing method and structure for acoustic wave resonator devices integrated with high electron mobility transistor devices, including single crystal piezoelectric layers, which can be shared by both devices to provide synergistic functional and structural advantages for provide each. By way of example only, the invention has been applied to a single crystal resonator device for a communication device, a mobile device, a computer device, among others.

As recognized by the inventors of the present invention, the performance of piezoelectric resonator devices can be improved, particularly at frequencies in the 5G range, by providing high quality piezoelectric single crystal layers. However, forming such high quality single crystal piezoelectric layers can be difficult due to the tendency of some piezoelectric materials, such as AlN, to crack or otherwise fail due to thermal issues or increased stresses resulting from epitaxial processes typically used to form single crystal piezoelectric layers be. For example, some epitaxial processes can grow piezoelectric materials on Si where temperatures can exceed about 1000 degrees Celsius. When the wafer is cooled, the materials can crack due to excessive induced stresses (particularly when the piezoelectric materials are formed to thicknesses suitable for radio frequency applications - like 5G). As the inventors of the present invention further recognize, stress equalization can be used to counteract the stresses described above by growing other layers on the piezoelectric materials, such as a cap configured to make the piezoelectric materials resistant to cracking .

Accordingly, as recognized by the inventors of the present invention, the integration of a piezoelectric resonator device into a HEMT device can provide several advantages to the design and performance of each device. In particular, one or more layers of a HEMT device (such as the channel layer) may provide stress relief for an epi-grown piezoelectric layer, such as a Sc _x Al _1-x -N layer, by removing the channel layer as part of the epi process is grown on the piezoelectric layer. In addition, the piezoelectric layer can also provide a good structure for forming a HEMT channel layer such as GaN. Moreover, when the piezoelectric resonator device and the HEMT device are fabricated as a monolithically integrated device, the same piezoelectric layer can be shared by both devices. For example, a Sc _x Al _1-x -N layer may extend over a substrate, around a Sc _x Al _1-x -N piezoelectric layer of the resonator device in a first region of the substrate, and a Sc _x Al _1-x -N - to provide a buffer layer of the HEMT device in a second region of the substrate.

In some embodiments, stress balancing includes configurations in which a shared piezoelectric layer can be stress balanced relative to the HEMT channel layer. In some embodiments, a stress between the shared piezoelectric layer and the HEMT channel layer may be considered "stress balanced" when the stress is in a range between about +400 MPa and about -400 MPa.

As the inventors further appreciate, in some embodiments, a Sc _x Al _1-x -N piezoelectric layer can provide a relatively high K and can provide good lattice matching for the formation of the HEMT channel layer. In addition, the composition of the Sc _x Al _1-x N can be configured to both adjust K and configure the lattice to accommodate the growth of other III-N channel layers for the HEMT device. For example, in some embodiments, Sc _0.18 Al _0.82 N can be used for good K and lattice matching for a GaN channel. In other embodiments, Sc _0.30 Al _0.70 N can be used to provide lattice matching for an InGaN channel. Other III-N materials can be used for the channel layer, which can be matched to the Sc _x Al _1-x -N shared layer.

Methods of forming a piezoelectric resonator device that is integrated into a HEMT device can utilize a transfer process by forming a semiconductor stack of materials comprising the shared piezoelectric layer and the rest of the HEMT layers, including a III-N channel layer (on the piezoelectric layer as a buffer layer for the HEMT), the barrier layer and an optional top layer. The HEMT stack can be further processed to form the source and drain regions and the gate. The metallization for ohmic contacts to the source, drain and gate can also be used to form a bottom electrode for the resonator.

The entire structure (the resonator and the HEMT) can then be transferred onto a supporting substrate (e.g. Si <100>) so that the growth substrate (on which the shared piezoelectric layer and the HEMT stack were grown) is removed can. Once the growth substrate has been removed, the exposed backside of the piezoelectric layer can be processed to form, for example, a top electrode (for the resonator) and vias and contacts (for the resonator and HEMT). Accordingly, the transfer process allows both sides of the shared piezoelectric layer to be used (for both the resonator and the HEMT). As further appreciated by the inventors of the present invention, surface acoustic wave resonator devices may also be integrated into HEMT devices through a shared piezoelectric layer in some embodiments according to the invention, possibly not utilizing a transfer process. It goes without saying that other materials can also be used as the carrier substrate in some embodiments according to the invention.

As the inventors of the present invention further appreciate, in some embodiments according to the invention, the thickness of the HEMT channel layer can be configured to provide stress balancing for the formation of the shared piezoelectric layer. In particular, the thickness of a HEMT channel layer is typically reduced. However, as recognized by the inventors of the present invention, in some embodiments according to the invention, the thickness of the HEMT channel layer can be increased to provide improved stress balancing for the underlying shared piezoelectric layer. Accordingly, the thickness and composition of the HEMT channel layer (as well as the respective thicknesses and compositions of the HEMT barrier can deck layers) can be configured for load balancing.

Furthermore, in some embodiments according to the invention, the growth substrate may be conditioned with hot nitrogen gas prior to growing the shared piezoelectric layer. For example, NH ₃ can be deposited on the surface of the growth substrate (such as SiC or Al ₂ O ₃ ) to form a SiN on the surface of the growth substrate. Because of the stress equalization, the SiN can allow for the growth of a thicker shared piezoelectric layer, which can also be more resistant to cracking after the epi process. In some embodiments according to the invention, the growth substrate may be silicon <111> or SiC. Other materials can also be used for the growth substrate.

1A Fig. 12 is a schematic cross-sectional representation of a bulk acoustic wave (BAW) RF monolithic piezoelectric resonator device 105 integrated into a HEMT device 100 that includes a shared Sc _x Al _1-x -N layer 110 that encapsulates the piezoelectric layer in of the piezoelectric resonator device 105 and the buffer layer in the HEMT device 100 in some embodiments according to the present invention. According to 1A For example, the Sc _x Al _1-x -N shared layer 110 extends over the monolithic supporting substrate 115 to provide the piezoelectric layer of the resonator device 105 and the buffer layer of the HEMT device 100. The HEMT device 100 includes a HEMT stack of materials A that form the active layers of the HEMT device 100, including a III-N channel layer 120, a barrier layer 125, and an optional cap layer 130 ( 12 ).

It will be appreciated that in some embodiments, the HEMT stack of materials A and the Sc _x Al _1-x -N shared layer 110 may be epitaxially grown on the support substrate 115 without removing any traces during the formation of the HEMT stack of materials A and the Sc _x Al _1-x -N shared layer 110 is introduced a vacuum break. In other words, once the reaction chamber used for the epi process has been brought up to temperature, the process continues until the formation of the HEMT material stack is complete before the temperature cools.

As in 1A further shown, the Sc _x Al _1-x -N shared layer 110 is sandwiched between a bottom electrode 135 and a top electrode 140 . The bottom electrode 135 is separated from the support substrate 115 by a resonator cavity 145 that allows the portion of the Sc _x Al _1-x -N shared layer 110 located between the top and bottom electrodes 135 and 140 to be exposed , in response to electromagnetic energy impinging on this portion of Sc _x Al _1-x -N shared layer 110, resonates to produce an electrical response at top and bottom electrodes 135 and 140. The resonator cavity 145 also allows the portion of the Sc _x Al _1-x -N shared layer 110 located between the top and bottom electrodes 135 and 140 to resonate in response to an electrical signal transmitted across the top and bottom electrodes the lower electrode 135 and 140 is applied resonates. Further, the resonance of the Sc _x Al _1-x -N shared layer 110 may be affected by the amount of Sc included in the Sc _x Al _1-x -N shared layer 110 .

It is further understood that the amount of Sc included in the Sc _x Al _1-x -N shared layer 110 also determines the lattice structure of the Sc _x Al _1-x -N shared layer 110, so that other materials such as the III-N channel layer, can be more easily lattice-matched to the Sc _x Al _1-x -N shared layer 110 underneath. For example, in some embodiments according to the present invention, a Sc _0.18 Al _0.72 -N layer is closely matched to the lattice structure of GaN. Accordingly, in some embodiments according to the invention, a GaN channel layer 120 may be grown on the region of the Sc _0.18 Al _0.72 -N shared layer included in the HEMT device 100 . It is understood that other Sc _x Al _1-x -N layer 110 compositions may be used for different III-N channel layers 120, such as InGaN, InGaAsN.

How further in 1A As shown, the HEMT device 100 also includes a parasitic capacitance cavity 150 between the HEMT material stack A and the supporting substrate 115. It is understood that the resonator cavity 145 and the parasitic capacitance cavity 150 may be formed in the same step or may be formed separately . Further, the resonator cavity 145 and the parasitic capacitance cavity 150 may have different volumes and may be spaced from the support substrate 115 by different amounts. The resonator cavity 145 and the parasitic capacitance cavity 150 may also be filled with gas, such as air, or may be a vacuum, in some embodiments.

As in 1A As shown, the Sc _x Al _1-x -N shared layer 110 includes an opening exposing the bottom electrode 135 such that a lei tend material can be formed therein. The conductive material protrudes from the opening to couple to a bottom electrode contact 2920 . The top electrode 140 includes a recess 2912 in a top surface thereof. A contact 2610 is on the top surface of the Sc _x Al _1-x -N shared layer 110 and is coupled to the top electrode 140 . Although this in 1A not shown, resonator device 105 may also include a cavity located over top electrode 140 . It is also understood that the cavities described herein may also have any shape that provides the functionality described.

How further in 1A As shown, the HEMT device 100 includes a source region 175, a drain region 180, and a gate 185, at a level in the HEMT stack A that is closest to the supporting substrate 115. FIG. Accordingly, the source region 175, the drain region 180 and the gate 185 of the HEMT device 100 are on the same side of the shared Sc _x Al _1-x -N layer 110 as the bottom electrode 140 of the resonator device 105. Further, respective metallizations 190 and 195 extend from the source region 175 and drain region 180 away from the HEMT stack A to respective contacts 1905, each extending through the shared Sc _x Al _1-x -N layer 110 extend. It is understood that the respective metallization 190 and 195 may be formed in the same step along with the bottom electrode 140 in some embodiments according to the invention. Furthermore, in some embodiments according to the invention, the respective contacts 1905 may be formed in the same step used to form the top electrode 140 .

The HEMT device 100 and the resonator device 105 are both supported by a dielectric layer 1420 (sometimes referred to herein as a support layer) that forms the bottom wall of both the resonator cavity 145 and the parasitic capacitance cavity 150 adjacent the surface of the support substrate 115 .

1B FIG. 12 is a circuit diagram 220 that includes the monolithic RF BAW piezoelectric resonator 105 and the HEMT device 100 of FIG 1A in some embodiments according to the present invention. In particular shows 1B that contacts of the piezoelectric BAW resonator 105 and the HEMT device 100 can be coupled together in some embodiments according to the invention to form a circuit like that in FIGS 49 until 54 to form shown.

2 FIG. 12 is a detailed cross-sectional view of the HEMT stack A of semiconductor materials of FIG 1A , including the Sc _x Al _1-x -N shared layer 110 in some embodiments according to the present invention. According to 2 For example, the Sc _x Al _1-x -N shared layer 110 extends over the supporting substrate 115 and is in the RF BAW piezoelectric resonator 105 (as a piezoelectric resonator) and in the HEMT device 100 (as a buffer layer) in some embodiments contains. As in 2 Further shown, a nucleation layer 110a may be formed on the growth substrate 2610 to promote the epitaxial growth of the Sc _x Al _1-x -N shared layer 110 . For example, an AlN or GaN nucleation layer can be formed on a Si <100> substrate resonator to promote the epitaxial growth of the Sc _x Al _1-x -N shared layer 110, depending on the doping level of Sc. In some embodiments, the thickness of the nucleation layer may be about 0.05 microns, for example using ALD. It should be understood that the nucleation layer may be removed (in whole or in part) with the growth substrate 2610 when the partially formed RF BAW piezoelectric resonator 105 and HEMT device 100 are transferred to the supporting substrate 115 . In some embodiments, the growth substrate 2610 can be Si, SiC, Al2O3, or glass. Other carrier substrates can also be used.

The Sc _x Al _1-x -N shared layer 110 can be formed to a thickness of about 0.5 microns using a process that provides a single crystal piezoelectric layer. In some embodiments, the single crystal piezoelectric layer may be formed via relatively ordered crystal growth such as MOCVD, MBE, HVPE, or the like. In some embodiments according to the invention, the Sc _x Al _1-x -N shared layer 110 may be Sc _0.180 Al _0.82 N (sometimes referred to herein as 18% Sc) formed to have a crystalline structure characterized by an XRD-o-rocking curve FWHM value in a range between about less than 1.0 degrees and about 0.001 degrees measured at a two-theta (2Θ) scan angle measured about the Sc _x Al _1-x Nc axis film reflection. In some embodiments, the amount of Sc can be up to about 40% depending on the materials used for the III-N channel layer and the amounts of those materials in the III-N channel layer.

The III-N channel layer 120 may be a GaN channel layer grown on the Sc _x Al _1-x -N shared layer 110 . In some embodiments, the GaN channel layer is grown to a thickness in a range between about 0.5 microns to about 1.0 microns. As recognized by the present inventors, the III-N channel layer 120 can be grown to be stress balanced relative to the underlying Sc _x Al _1-x -N shared layer 110 .

Junction layer 125 may be selected to provide a relatively voltage balanced junction with a relatively large band offset and polarization relative to channel layer 120 to support 2DEG channel region confinement and high voltage/high power applications. In some embodiments, barrier layer 125 may be Sc _x Al _1-x -N lattice matching to underlying shared Sc _x Al _1-x -N layer (buffer layer) 110 . In some embodiments, the barrier layer 125 may be AlGaN. It is understood that the barrier layer 125 may include a sub-barrier layer 123 adjacent the interface with the channel layer 120, which is a closer lattice match to the channel layer 120 to promote a less stressed transition from the channel layer 120 to the barrier layer 125. In some embodiments, the sub-barrier layer 123 may be AlN formed to a thickness in a range between about 1 micron and about 0.005 microns, which may transition to AlGaN or Sc _x Al _1-x -N as the formation progresses. In some embodiments, the sub-barrier layer 123 and the barrier layer 125 may be formed by changing the composition of the material during the process. For example, if the barrier layer 125 is to be ScAlN or AlGaN, the sub-barrier layer 123 may be initially formed as AlN and progress to include an amount of Sc or Ga until the target composition of ScAlN or AlGaN as the barrier layer 125 is achieved.

As in 2 further shown, the HEMT stack A may include a cap layer 130 grown on the barrier layer 125 . In some embodiments, the cap layer 130 may be GaN formed to a thickness in a range between about 0.01 and 0.001 microns. In some embodiments, the cover layer 130 may be eliminated. In still other embodiments, an amorphous AlN may be formed on barrier layer 125 .

the 13A until 24 12 are cross-sectional views showing a transfer process for forming the RF BAW monolithic piezoelectric resonator and the HEMT device including the Sc _x Al _1-x -N shared layer of FIG 1A using a transmission structure (supporting substrate) and a sacrificial layer to form a resonator cavity and a HEMT parasitic capacitance cavity in some embodiments according to the present invention. In these series of figures described below, the "A" figures show simplified diagrams representing top cross-sectional views of the piezoelectric BAW resonator and the HEMT device according to various embodiments of the present invention. Figures "B" show simplified diagrams depicting longitudinal sectional views of the same devices in Figures "A". Similarly, the "C" figures show simplified diagrams representing widthwise cross-sectional views of the same devices in the "A" figures. Similarly, the "D" figures show simplified diagrams, top cross-sectional views of the HEMT device 100, with widthwise cross-sectional views of the same devices illustrated in the "A" figures. In some cases, certain features may be omitted to emphasize other features and the relationships between those features. Those of ordinary skill in the art will recognize variations, modifications, and alternatives to the examples shown in this series of figures.

According to the 3A until 3C and 4 until 7 the piezoelectric layer 110 is formed on the growth substrate 1610. FIG. In some embodiments, growth substrate 1610 may include silicon (S), silicon carbide (SiC), Al ₂ O ₃ , or other similar materials. The piezoelectric layer 110 may be an epitaxial layer of Sc _x Al _1-x N or other similar materials. In addition, this piezoelectric layer 110 can be subjected to a thickness trimming. It goes without saying that the 4 until 7 1 illustrate an epi-growth process used to form HEMT stack A including piezoelectric layer 110, III-N channel layer 120, barrier layer 125, and optional cap layer 130. FIG.

The epi-growth process can be performed such that layers of the HEMT stack A are formed in a reaction chamber without cooling the HEMT stack A below the temperature at which the epi-growth is performed. In particular, as in the 4 until 7 As shown, the piezoelectric layer 110 may be formed on a nucleation layer 110A, such as AlN or GaN, on the growth substrate. The barrier layer 125 can be formed on the III-N channel layer using an under barrier layer 123 and the optional cap layer 130 can be formed on the barrier layer 125 . After HEMT stack A has grown, further processing of the HEMT stack can be done out-of-process, or alternatively as part of the epi-growth process.

In some embodiments, the epi-growth process may be performed in a MOCVD system where the piezoelectric layer 110 is Sc _x Al _1-x N, such as described in US patent application Ser 16/784,843 entitled Apparatus For Forming Single Crystal Piezoelectric Layers Using Low-Vapor Pressure Metalorganic Precursors In CVD Systems And Methods Of Forming Single Crystal Piezoelectric Layers Using The Same filed with the USPTO on February 7, 2020, commonly assigned to the present assignee, the entirety of which is hereby incorporated by reference. Some embodiments according to the invention may use low vapor pressure metal organic (MO) precursors to incorporate the Sc dopant at the target concentrations (e.g. 18%, 30% or more) by increasing the low vapor pressure MO precursor to a relative high temperature is heated (e.g. more than 150 degrees Celsius). For example, in some embodiments according to the invention, a CVD system can heat a low vapor pressure MO precursor such as tris(cyclopentadienyl)Sc (ie (Cp)3Sc)) and (MeCp)3Sc to at least 150 degrees Celsius. In embodiments according to the present invention, other low vapor pressure MO precursors can also be used to induce the epi-growth of HEMT stack A, as in FIGS 4 until 7 shown without performing a vacuum break.

In some embodiments, the source vessel containing the source of low vapor pressure organometallic (MO) precursors can be heated to at least 150 degrees Celsius, as can the lines that deliver the vapor of the low vapor pressure MO precursors to the CVD reactor chamber . In some embodiments, the CVD reactor is a horizontal flow reactor capable of producing laminar flow of the vapor of the low vapor pressure MO precursors over the wafers in the reactor. In some embodiments according to the invention, the horizontal flow reactor may include a planetary-type device that rotates during the deposition process and that rotates the wafer stations that hold each of the wafers.

In some embodiments according to the invention, the low vapor pressure MO precursor may be any organometallic material with a vapor pressure of 4.0 Pa or less at room temperature. In some embodiments according to the invention, the low vapor pressure MO precursor can be any organometallic material with a vapor pressure between about 4.0 Pa and about 0.004 Pa at room temperature. In still other embodiments according to the invention, the heated line that conducts the low vapor pressure MO precursor vapor to the CVD reactor chamber is thermally isolated from the other MO precursors and hydrides. For example, in some embodiments, the heated line that conducts the low vapor pressure MO precursor vapor to the CVD reactor chamber is delivered to the central injector column via a different route than that used to provide the other precursors, such as through a flexible heated line connected to a moving section of the CVD reactor. In particular, the other precursors to the central injector column may be delivered through a lower portion of the CVD reactor that remains stationary when the CVD reactor is opened, such as by raising the upper portion of the CVD reactor to open the CVD reactor chamber. Accordingly, when the CVD reactor chamber is in the open position, the top and bottom portions of the CVD reactor separate from one another to expose, for example, the planetary assemblies described herein.

As recognized by the inventors of the present invention, supplying the low vapor pressure MO precursor vapor to the central injector column in a different way than the other precursors can allow the low vapor pressure MO precursor vapor to reach the relatively high temperature is heated without adversely affecting the other precursors (e.g. heating) above room temperature. While the other precursors can be supplied via other precursor lines routed through the lower section and configured to connect/disconnect when the CVD reactor is closed/opened, the heated low vapor pressure precursor line can be closed of the central injector column remain a unitary flexible part, allowing the top section to move when opening/closing and yet being thermally isolated from the other precursors/curtains.

In some embodiments, the molar flow of the low vapor pressure MO precursor vapor is provided by a high temperature mass flow controller (MFC) located downstream of the heated low vapor pressure MO precursor source vessel. In some embodiments according to the invention, an MFC is located upstream of the heated source vessel for low vapor pressure MO precursors, and a high temperature pressure regulator is downstream of the heated source low vapor pressure MO precursor vessel is placed in series with the line that carries the low vapor pressure MO precursor vapor to the CVD reactor chamber. Accordingly, in embodiments in which a device such as the high-temperature MFC or the high-temperature pressure regulator, is placed in series with the line that conducts the low-vapor pressure MO precursor vapor to the CVD reactor chamber downstream of the heated low-vapor pressure MO precursor source vessel, the respective device configured to operate at relatively high temperatures, such as B. more than 150 degrees Celsius.

In some embodiments, when Sc, Ga, In, and Al are used in the HEMT stack A, the temperature within the CVD reactor chamber can be maintained at a temperature ranging between about 800 degrees Celsius and about 1500 degrees Celsius. The temperature within the CVD reactor chamber can be maintained at a temperature ranging between about 600 degrees Celsius and about 1000 degrees Celsius when Sc, Ga, Al, and In are used in the HEMT stack A in some embodiments.

As in 8th 1, the portion of the HEMT stack A over the Sc _x Al _1-x -N piezoelectric layer 110, which is in the region of the substrate associated with the resonator device 105, can be removed to reveal the surface of the Sc piezoelectric _x Al _1-x N layer 110 to expose. A protective layer may be formed on the surface of the Sc _x Al _1-x -N piezoelectric layer 110 to avoid damage during further processing of the remaining portion of the HEMT stack A on the area of the substrate containing the HEMT device 100 is assigned. In some embodiments according to the invention, the portion of the HEMT stack A over the Sc _x Al _1-x -N piezoelectric layer 110 shown in FIG 8th removed can be maintained while further processing HEMT stack A as shown in FIGS 9 until 12 shown is carried out.

According to the 9 until 12 HEMT stack A is further processed to provide the source and drain regions for HEMT device 100. FIG. In particular, as in 9 As shown, source and drain recesses 910 and 920 are formed in the top surface of HEMT stack A. FIG. Recesses 910 and 920 are formed to expose III-N channel layer 120 but do not extend into Sc _x Al _1-x N piezoelectric layer 110 that provides the buffer layer for HEMT device 100 . According to 10 For example, a III-N source and drain HEMT material may be regrown or otherwise deposited in source and drain recesses 910 and 920 to form source and drain regions 175 and 180 . In some embodiments, the source and drain regions are formed on doped GaN.

In some embodiments, the top surfaces can be planarized. In other embodiments, the source and drain regions protrude above the HEMT stack A surface. According to 11 For example, a gate depression 1110 is formed in the surface of HEMT stack A between the source and drain regions, which are conductive to a depth that exposes the barrier layer 125 but does not extend into the III-N channel layer 120. FIG . According to 12 a conductive gate material is deposited in gate recess 1110 to form gate 185 . In some embodiments, the gate electrode is formed on the surface of HEMT stack A and is not recessed below the surface of HEMT stack A. In some embodiments, the portion of HEMT stack A located on the region of growth substrate 1610 associated with resonator device 105 may be removed to expose the top surface of Sc _x Al _1-x -N piezoelectric layer 110 .

According to 13 patterned metallization is deposited on the source region 175 and the drain region 180 to form metal lines 195, respectively, which extend from the sides of the HEMT stack A to the surface of the Sc _x Al _1-x N piezoelectric layer 110 . The patterned metallization also forms the bottom electrode 135 for the resonator device 105 on the surface of the Sc _x Al _1-x -N piezoelectric layer 110 . In an example, the first passivation layer 1810 may include silicon nitride (SiN), silicon oxide (SiOx), or other similar materials. In a specific example, the first passivation layer 1810 may have a thickness ranging from about 50 nm to about 100 nm.

As in 14 As shown, a sacrificial layer 1405 is formed on the bottom electrode 135 and a sacrificial layer 1410 is formed on the surface of the HEMT device 100 . Sacrificial layers 1405 and 1410 may include polycrystalline silicon (poly-Si), amorphous silicon (a-Si), or other similar materials. In a specific example, these sacrificial layers 1405 and 1410 may be dry etched with a slope and deposited to a thickness of about 1 µm. Furthermore, phosphorus-doped SiO ₂ (PSG) can be used as a sacrificial layer with different combinations of carrier layers (e.g. SiNx).

A support layer 1420 may be formed over the resonator device 105 and the HEMT device 100 and over the sacrificial layers 1405 and 1410 . In an example, the support layer 1420 may include silicon dioxide (SiO ₂ ), silicon nitride (SiN), or other similar materials. In a specific example, the support layer 1420 may be deposited to a thickness of about 2-3 microns. In the case of a PSG sacrificial layer, other carrier layers (e.g. SiNx) can also be used. The top surface of the backing layer 1420 can then be polished. Polishing the backing 1420 forms a polished backing. In an example, the polishing process may include a chemical mechanical planarization process or the like.

According to 15 the polished surface 1421 of the support layer is coupled to the support substrate 115 via a bonding layer. In one example, the support substrate 115 may include an interconnect support layer 2220 (SiO ₂ or similar material) overlying the support substrate 115 of Si, Al ₂ O ₃ , silicon dioxide, silicon carbide (SiC), or similar materials. In a specific embodiment, the bond backing layer 2220 of the backing substrate 115 is physically coupled to the polished surface 1421 . Further, the physical coupling process may include a room temperature bonding process followed by a 300 degree Celsius annealing process.

As in 16 1, the growth substrate 1610 is removed to expose the bottom surface of the Sc _x Al _1-x N piezoelectric layer 110 opposite the surface on which the HEMT device 100 and the resonator device 105 were formed, as in FIGS 3A until 14 shown. In an example, the removal process may include a grinding process, a blank etch process, a film transfer process, an ion implantation transfer process, a laser crack transfer process, or the like, and combinations thereof. It should be understood that further processing of the HEMT device 100 and the resonator device 105 is shown with the support substrate 115 reversed.

According to the 17A until 17D the bottom electrode 135 may include molybdenum (Mo), ruthenium (Ru), tungsten (W), or other similar materials. In a specific example, the bottom electrode 135 may be subjected to a dry etch with a sloped electrode to open the via 2410 within the Sc _x Al _1-x -N piezoelectric layer 110 overlying the bottom electrode 135 and one or more release holes 2420 within the Sc _x Al _1-x -N piezoelectric layer 110 and the first passivation layer 1810 overlying the sacrificial layer 1405 . The via formation processes may include various types of etching processes. As in 17 Further shown, the etch may also be used to form vias 2415 in the Sc _x Al _1-x -N piezoelectric layer 110 to expose the metallization coupled to the source and drain regions of the HEMT device 100 . As an example, the slope may be about 60 degrees.

According to the 18A until 18D For example, the upper electrode 140 can be formed overlying the Sc _x Al _1-x -N piezoelectric layer 110. FIG. In one example, forming the top electrode 140 includes depositing a metal such as molybdenum (Mo), ruthenium (Ru), tungsten (W), or other similar materials; and then etching top electrode 140 to form electrode cavity 2511 and removing portion 2511 from top electrode 140 to form top metal 2520 in via 2410 to contact bottom electrode 135. As in FIG 18A until 18D Further shown, the metal may also be deposited in vias 2415 on HEMT device 105 to provide electrodes 1811 .

According to the 19A until 19D a first contact metal 2610 may be formed overlying a portion of the top electrode 140 and a portion of the Sc _x Al _1-x -N piezoelectric layer 110, and forming a second contact metal 2611 overlying a portion of the top metal 2520 and part of the Sc _x Al _1-x -N piezoelectric layer 110 . In an example, the first and second contact metals may include gold (Au), aluminum (Al), copper (Cu), nickel (Ni), aluminum bronze (AlCu), or related alloys of these materials, or other similar materials. As in the 19A until 19D further shown, the metal may also be deposited on the electrodes 1811 on the HEMT device 105 to form contacts 1905. FIG. In some embodiments according to the invention, an AlN heat sink 1910 may also be formed on the Sc _x Al _1-x -N piezoelectric layer 110 between the contacts 1905 .

According to the 20A until 20D A second passivation layer 2710 overlying the top electrode 140, the top metal 2520 and the Sc _x Al _1-x -N piezoelectric layer 110 may be formed. In an example, the second passivation layer 2710 may include silicon nitride (SiN), silicon oxide (SiOx), or other similar materials. In a specific example, the second passivation layer 2710 may have a thickness ranging from about 50 nm to about 100 nm.

According to the 21A until 21D sacrificial layer 1405 is removed to form resonator cavity 145 and sacrificial layer 1410 is removed to form HEMT cavity 150 . In an example, the removal process may include a poly-Si etch, or a Si etch, or the like.

According to the 22A until 22D For example, top electrode 140 and top metal 2520 may be processed to form processed top electrode 2910 and processed top metal 2920 . This step may follow formation of top electrode 140 and top metal 2520 . In one example, processing these two components involves depositing molybdenum (Mo), ruthenium (Ru), tungsten (W), or other similar materials; and then etching (e.g., dry etching or the like) this material to form the processed second electrode 2910 having an electrode cavity 2912 and the processed top metal 2920 . The processed top metal 2920 remains separated from the processed top electrode 2910 by removing portion 2911 . In a specific example, the processed top electrode 2910 is characterized by the addition of an energy confinement structure configured on the processed second electrode 2910 to increase Q.

According to the 23A until 23D For example, bottom electrode 135 can be processed to form processed bottom electrode 3010 . This step may follow the bottom electrode 135 formation. In one example, processing these two components involves depositing molybdenum (Mo), ruthenium (Ru), tungsten (W), or other similar materials; and then etching (e.g., dry etching or the like) this material to form the processed bottom electrode 3010 with an electrode cavity similar to the processed top electrode. The resonator cavity 2811 shows the change in cavity shape due to the processed bottom electrode 3010. In a specific example, the processed bottom electrode 3010 is characterized by the addition of an energy confinement structure configured on the processed second electrode 3010 to increase Q.

As in the 24A until 24D As shown, bottom electrode 135 may be processed to form processed bottom electrode 2310 and top electrode 140/top metal 2520 may be processed to form top electrode 2910/processed top metal 2920. FIG. These steps can follow the formation of each respective electrode, as for FIG 22A until 22D and 23A until 23D described. Those of ordinary skill in the art will recognize other variations, modifications, and alternatives.

the 25A until 36D 12 are cross-sectional views illustrating a transfer process for forming a monolithic RF BAW piezoelectric resonator and the HEMT device including the Sc _x Al _1-x -N shared layer 110 using a transfer structure (supporting substrate) without a sacrificial layer, to in some Embodiments according to the present invention to form a resonator cavity and a HEMT parasitic capacitance cavity. In these series of figures described below, the "A" figures show simplified diagrams representing top cross-sectional views of the piezoelectric BAW resonator and the HEMT device according to various embodiments of the present invention. Figures "B" show simplified diagrams depicting longitudinal sectional views of the same devices in Figures "A". Similarly, the "C" figures show simplified diagrams representing widthwise cross-sectional views of the same devices in the "A" figures. Similarly, the "D" figures show simplified diagrams, top cross-sectional views of the HEMT device 100, with widthwise cross-sectional views of the same devices illustrated in the "A" figures. In some cases, certain features may be omitted to emphasize other features and the relationships between those features. Those of ordinary skill in the art will recognize variations, modifications, and alternatives to the examples shown in this series of figures.

It is understood that embodiments according to the present invention in the 33 until 36 shown monolithic piezoelectric RF BAW resonator and HEMT device using the in FIGS 3 until 13 process described to provide the structure that, as in the 25 until 36 shown, is further processed using a transfer process but without the need for a sacrificial layer on the resonator device 105 or the HEMT device 100.

As in the 25A until 25D As shown, a support layer 1420 is formed on the bottom electrode 135 and the Sc _x Al _1-x -N shared layer 110 and on the HEMT device 100 . In an example, the support layer 1420 may include silicon dioxide (SiO ₂ ), silicon nitride (SiN), or other similar materials. In a specific example, this support layer 1420 may be deposited to a thickness of about 2-3 microns. As described above, in the case a PSG sacrificial layer, other carrier layers (e.g. SiNx) can also be used.

As in the 26A until 26D As shown, the backing 1420 is processed to form a backing 3511 including a recessed portion 3610 on the resonator device 105 . In an example, the processing may include partially etching the support layer 1420 to create a flat bonding surface. In a specific example, the processing may include a void area. In other examples, this step may be replaced with a polishing process, such as a chemical-mechanical planarization process or the like.

As in the 27A until 27D As shown, an indentation for an air cavity 3710 is formed within a portion of backing layer 3511 (to form backing layer 3512). In an example, the recess formation may include an etch process that stops at the first passivation layer 3410 . It is understood that the first passivation layer 3410 may also be formed on the HEMT device 100 such that the etch process may stop at the first passivation layer 3410 over the HEMT device 100 such that the parasitic capacitance cavity 2715 over the HEMT device 100 can be formed.

As in the 28A until 28D As shown, one or more cavity vents 3810 may be formed within a portion of the Sc _x Al _1-x -N shared layer 110 through the first passivation layer 3410 . In one example, cavity vent holes 3810 may be connected to air cavity 3710 .

As in the 29A until 29D As shown, the growth substrate 1610 and the structures formed therein are shown inverted to illustrate the bonding of the support layer 1420 overlying the support substrate 115. FIG. In one example, the support substrate 115 may include a bond backing layer 3920 (SiO ₂ or similar material) overlying the substrate. It is understood that the support substrate 115 may be Si, Al ₂ O ₃ , silicon dioxide (SiO ₂ ), silicon carbide (SiC), or other similar materials. In a specific embodiment, the bond backing 3920 of the backing substrate 115 is physically coupled to the polished backing. Further, the physical coupling process may include a room temperature bonding process followed by a 300 degree Celsius annealing process.

As in the 30A until 30D As shown, the growth substrate 1610 is removed so that the Sc _x Al _1-x -N shared layer 110 is transferred to the support substrate 115 to form the resonator cavity 3710 and the parasitic capacitance cavity 3715 . In an example, the removal of the growth substrate 1610 may be performed using a grinding process, a blank etch process, a film transfer process, an ion implantation transfer process, a laser crack transfer process, or the like, and combinations thereof.

As in the 31A until 31D As shown, an electrode via 4110 is formed within the Sc _x Al _1-x -N shared layer 110 overlying the bottom electrode 135 . Vias 3110 are also formed in the Sc _x Al _1-x -N shared layer 110 to expose the metallization layers of the HEMT device 100 that are coupled to the source and drain regions and the gate of the HEMT device 100 . The via formation processes may include various types of etching processes.

As in the 32A until 32D As shown, the top electrode 140 is formed to overlie the Sc _x Al _1-x -N shared layer 110 . In one example, the formation of the top electrode 140 can be accomplished by depositing a metal such as molybdenum (Mo), ruthenium (Ru), tungsten (W), or other similar materials; and then etching top electrode 140 to form electrode cavity 4211 and removing portion 4211 from top electrode 140 to form top metal 4220 . Furthermore, top metal 4220 is physically coupled to bottom electrode 135 through electrode via 4110 . As in the 32A until 32D further shown, the metal may also be deposited in vias 3110 to contact the mentalizations on HEMT device 105 with electrodes 3111 .

As in the 33A until 33D As shown, a first contact metal 4310 is formed overlying a portion of top electrode 140 and a portion of Sc _x Al _1-x -N piezoelectric layer 110, and forms a second contact metal 4311 overlying a portion of top metal 4220 and a part of the Sc _x Al _1-x -N piezoelectric layer 110 . The first and second contact metals may also be deposited in vias 3110 on HEMT device 100 to provide contacts 1810, 1815, and 1820a as shown. In an example, the first and second contact metals may include gold (Au), aluminum (Al), copper (Cu), nickel (Ni), aluminum bronze (AlCu), or other similar materials. This figure also shows the process step forming a second passivation layer 4320 overlying the second electrode 4210, the top metal 4220 and the Sc _x Al _1-x N piezoelectric layer 110. In an example, the second passivation layer 4320 may include silicon nitride (SiN), silicon oxide (SiOx), or other similar materials. In a specific example, the second passivation layer 4320 may have a thickness ranging from about 50 nm to about 100 nm.

As in the 34A until 34D As shown, top electrode 140 and top metal 4220 may be processed to form processed top electrode 4410 and processed top metal 4420 . This step may follow formation of top electrode 140 and top metal 4220 . This step may also include the formation of the AlN heat sink 3421 on the HEMT device 100. In one example, the processing of these two components includes depositing molybdenum (Mo), ruthenium (Ru), tungsten (W), or other similar materials; and then etching (e.g., dry etching or the like) this material to form the processed top electrode 4410 with an electrode cavity 4412 and the processed top metal 4420 . The processed top metal 4420 remains separated from the processed top electrode 141 by the removal of portion 4411 . In a specific example, the processed second electrode 4410 is characterized by the addition of an energy confinement structure configured on the processed top electrode 141 to increase Q.

As in the 35A until 35D As shown, the bottom electrode 135 can be formed by machining the bottom electrode 135. FIG. In one example, processing these two components involves depositing molybdenum (Mo), ruthenium (Ru), tungsten (W), or other similar materials; and then etching (e.g., dry etching or the like) this material to form the processed bottom electrode 4510 with an electrode cavity 3711 similar to the processed top electrode 4410 . Air cavity 4511 shows the change in cavity shape due to processed bottom electrode 4510. In a specific example, processed bottom electrode 4510 is characterized by the addition of an energy confinement structure configured on processed bottom electrode 4510 to increase Q.

As in the 36A until 36D As shown, bottom electrode 135 is processed to form processed bottom electrode 4510 and top electrode 4210/top metal 4220 is processed to form processed top electrode 4410/processed top metal 4420. FIG. These steps can follow the formation of each respective electrode, as for 34A until 34D and 35A until 35C described. Those of ordinary skill in the art will recognize other variations, modifications, and alternatives.

the 37A until 37D 10 illustrate methods for fabricating a monolithic piezoelectric RF BAW resonator 105 with a multilayer mirror structure and a HEMT device 100 containing the shared Sc _x Al _1-x -N layer 110 using a transmission structure (supporting substrate). In these series of figures described below, the “A” figures show simplified diagrams depicting top cross-sectional views of resonator devices 105 and HEMT devices 100 according to various embodiments of the present invention. Figures "B" show simplified diagrams depicting longitudinal sectional views of the same devices in Figures "A". Similarly, the "C" figures show simplified diagrams representing widthwise cross-sectional views of the same devices in the "A" figures. Similarly, the "D" figures show simplified diagrams, top cross-sectional views of the HEMT device 100, with widthwise cross-sectional views of the same devices illustrated in the "A" figures. In some cases, certain features are omitted to emphasize other features and the relationships between those features. Those of ordinary skill in the art will recognize variations, modifications, and alternatives to the examples shown in this series of figures.

It is understood that embodiments according to the present invention in the 37 until 47 shown monolithic piezoelectric RF BAW resonator and HEMT device using the in FIGS 3 until 13 process described to provide the structure that, as in the 37 until 47 shown, is further processed using a transfer process but without the need for a sacrificial layer on the resonator device 105, whereas a cavity on the HEMT device 100 using a sacrificial layer as in FIG 14 1, or by forming a depression in the support layer prior to bonding the structure to the support substrate 115, such as in FIGS 27 until 29 shown can be formed.

As in the 37A until 37D As shown, a multilayer mirror or reflector structure is formed on a bottom electrode 4810 located on the shared Sc _x Al _1-x -N piezoelectric layer 110 . In an example, the multilayer mirror includes at least one pair of layers including a low impedance layer 4910 and a high impedance layer 4920. In FIGS 37A until 37D two pairs of low/high impedance layers are shown (low: 4910 and 4911; high: 4920 and 4921). In one example, the mirror/reflector area may be larger than the resonator area and enclose the resonator area. In a specific embodiment, each layer thickness is approximately 1/4 the wavelength of an acoustic wave at a target frequency. The layers can be deposited sequentially and then etched, or each layer can be deposited and etched individually. In another example, the bottom electrode 4810 can be patterned after the mirror structure has been patterned.

As in the 38A until 38D As shown, a support layer 5010 is formed overlying the mirror structure (layers 4910, 4911, 4920, and 4921), the bottom electrode 135, the Sc _x Al _1-x -N shared layer 110, and the HEMT device 100 . In an example, the support layer 5010 may include silicon dioxide (SiO ₂ ), silicon nitride (SiN), or other similar materials. In a specific example, this sacrificial layer 5010 may be dry etched with a slope and deposited to a thickness of about 2-3 µm. As described above, other support layers (e.g. SiNx) can be used.

As in the 39A until 39D As shown, a depression 5012 is formed in the backing 5010 over HEMT stack A, and the backing 5010 may be polished to form a polished backing 5011 to enhance the bond strength provided by subsequent transfer. In an example, the polishing process may include a chemical mechanical planarization process or the like.

As in the 40A until 40D shown is the in the 39A until 39D structure formed inverted and shown with the polished support layer 5011 positioned opposite the support substrate 115, with a support substrate 115, prior to transfer. In an example, the support substrate 115 may include a bonding support layer 5220 (SiO ₂ or similar material) formed over the substrate support substrate of silicon (Si), sapphire (Al ₂ O ₃ ), silicon dioxide (SiO ₂ ), silicon carbide (SiC), or similar materials located.

As in the 41A until 41D As shown, the support substrate 115 is contacted and bonded to the polished support layer 5011 such that the recess 5012 and the support substrate 115 form a HEMT cavity 5103 of parasitic capacitance. Further, the physical coupling process may include a room temperature bonding process followed by a 300 degree Celsius annealing process.

As in the 42A until 42D As shown, the growth substrate 1610 is removed to expose the underlying surface of the Sc _x Al _1-x -N shared piezoelectric layer 110 . The removal of the growth substrate 1610 may be performed using a grinding process, a blank etch process, a film transfer process, an ion implantation transfer process, a laser crack transfer process, or the like, and combinations thereof.

As in the 42A until 42D Further shown, an electrode via 5410 is formed through the shared Sc _x Al _1-x -N piezoelectric layer 110 to expose the bottom electrode 135 on the opposite side of the Sc _x Al _1-x -N piezoelectric layer 110 . Additional vias 3110 may be formed through the shared Sc _x Al _1-x -N piezoelectric layer 110 to expose the metallization of the HEMT device 100 as shown. The via formation processes may include various types of etching processes.

As in the 43A until 43D As shown, a metal may be deposited to form a top electrode 140 overlying the Sc _x Al _1-x -N piezoelectric layer 110 and to form a top metal 5520 in the via 3110 . In one example, depositing the metal in the vias may be performed by depositing molybdenum (Mo), ruthenium (Ru), tungsten (W), or other similar material. Top electrode 140 may be etched to form electrode cavity 5511 by removing part of top electrode 140 to form top metal 5520 . Furthermore, the top metal 5520 is physically coupled to the bottom electrode 135 through the electrode via 5410 .

As in the 44A until 44D As shown, a first contact metal 5610 is formed over a portion of top electrode 140 and a portion of Sc _x Al _1-x -N shared piezoelectric layer 110, and a second contact metal 5611 may be formed over a portion of top metal 5520 and a portion of the Sc _x Al _1-x -N shared piezoelectric layer 110 . Furthermore, metal contacts 1905 can be formed on the electrodes 3112. FIG. In addition, a heat sink 1910 can be formed on the surface of HEMT device 100 between contacts 1810 and 1815 the. In some embodiments, the heat sink 41401 can be poly-AlN.

In an example, the first and second contact metals may include gold (Au), aluminum (Al), copper (Cu), nickel (Ni), aluminum bronze (AlCu), or other similar materials. This figure also shows the process step of forming a second passivation layer 5620 overlying the top electrode 5510, the top metal 5520, and the shared Sc _x Al _1-x N piezoelectric layer 110. FIG. In an example, the second passivation layer 5620 may include silicon nitride (SiN), silicon oxide (SiOx), or other similar materials. In a specific example, the second passivation layer 5620 may have a thickness ranging from about 50 nm to about 100 nm.

As in the 45A until 45D As shown, top electrode 140 and top metal 5520 may be processed to form processed top electrode 5710 and processed top metal 5720 . This step may follow formation of top electrode 140 and top metal 5520 . In one example, the processing of these two components includes depositing molybdenum (Mo), ruthenium (Ru), tungsten (W), or other similar materials; and then etching (e.g., dry etching or the like) this material to form the processed top electrode 5710 with an electrode cavity 5712 and the processed top metal 5720 . The processed top metal 5720 remains separated from the processed top electrode 5710 by the removal of portion 5711 . In a specific example, this processing imparts an increased thickness to the top electrode and top metal while creating the electrode cavity 5712 . In a specific example, the processed top electrode 5710 is characterized by the addition of an energy confinement structure configured on the processed top electrode 5710 to increase Q.

As in the 46A until 46D As shown, bottom electrode 4810 may be processed to form processed bottom electrode 135 . This step may follow the bottom electrode 4810 formation. In one example, the processing of these two components involves the deposition of molybdenum (Mo), ruthenium (Ru), tungsten (W), or other similar materials; and then etching (e.g., dry etching or the like) this material to form the processed lower electrode 5810 having an electrode cavity similar to the processed upper electrode 5710. In a specific example, the processed bottom electrode 5810 is characterized by the addition of an energy confinement structure configured on the processed top electrode 5810 to increase Q.

As in the 47A until 47D As shown, bottom electrode 135 may be processed to form processed bottom electrode 5810 and top electrode 140/top metal 5520 may be processed to form processed top electrode 5710/processed top metal 5720. FIG. These steps can follow the formation of each respective electrode, as for 45A until 45D and 46A until 46C described. Those of ordinary skill in the art will recognize other variations, modifications, and alternatives.

In any of the previous examples relating to transfer processes, energy confinement structures may be formed on the bottom electrode, the top electrode, or both. In one example, these energy confinement structures are mass-loaded areas surrounding the resonator area. The resonator area is the area where the first electrode, the shared Sc _x Al _1-x N piezoelectric layer, and the top electrode overlap. The larger mass load in the energy confinement structures lowers a cutoff frequency of the resonator. The cut-off frequency is the lower or upper limit of the frequency at which the acoustic wave can propagate in a direction parallel to the surface of the piezoelectric layer. Therefore, the cutoff frequency is the resonant frequency at which the wave propagates along the thickness direction, and is thus determined by the entire stacked structure of the resonator along the vertical direction.

As used herein, unless otherwise defined, the term "substrate" can include any overlying growth structure such as an aluminum, gallium, or a ternary compound of aluminum and gallium and a nitrogen-containing epitaxial region or functional regions, combinations, and the like.

In piezoelectric layers (e.g. ScAlN), sound waves with a frequency lower than the cut-off frequency can propagate in a parallel direction along the surface of the film, i.e. H. the sound wave has a high cut-off type dispersion characteristic. In this case, the mass-loaded area surrounding the resonator provides a barrier that prevents the acoustic wave from propagating outside the resonator. As a result, this feature increases the quality factor of the resonator and improves the performance of the resonator and consequently the filter.

48 12 is a cross-sectional view of a monolithic surface acoustic wave (SAW) resonator device 4800 integrated with a HEMT device 4805 that includes a shared Sc _x Al _1-x N piezoelectric layer 110 in some embodiments according to the invention. In particular, the Sc _x Al _1-x -N shared piezoelectric layer 110 provides the piezoelectric layer for the SAW resonator 4800 and provides the buffer layer for the HEMT device 4805 . It is understood that the materials described here with respect to the BAW resonator to the SAW configuration of 48 can be adjusted.

49 Figure 4 is a schematic representation of a transmit module 4900 that includes a BAW filter 4910, an amplifier 4915 implemented using at least one HEMT device, and a switch 4805 implemented using at least one HEMT device mounted in an integrated form factor as herein described in some embodiments according to the present invention.

50 Figure 12 is a schematic representation of a Partial Complete Front End Module (CFE) high band device 5000 that includes a BAW filter 5010, an amplifier 5015 implemented using at least one HEMT device, and a switch 5005 implemented using at least one HEMT device , assembled in an integrated form factor as described herein in some embodiments in accordance with the present invention.

51 Figure 12 is a schematic representation of a switched duplexer bank 5100 that includes at least one BAW filter 5110 and at least one switch 5105 (implemented using at least one HEMT device, such as a bypass switch or a multi-throw switch, the in some embodiments according to the present invention, are assembled in an integrated form factor.

52 Figure 5 is a schematic representation of an antenna switch module 5200 that includes at least one BAW filter 5210 and at least one switch 5205 (implemented using at least one HEMT device, such as a bypass switch or a multi-throw switch, mounted in an integrated form factor , in some embodiments according to the present invention.

53 12 is a schematic representation of a diversity reception FEM 5300 that includes at least one low-noise amplifier 5315 implemented using at least one HEMT device, at least one BAW filter 5310, and at least one switch 5305 implemented using at least one HEMT device. Device is implemented, which in some embodiments according to the present invention are assembled in an integrated form factor.

54 Fig. 12 is a schematic representation of a power amplifier duplexer (PA duplexer) 5400 that includes at least one power amplifier 5415 implemented using at least one HEMT device and at least one BAW filter 5410, which in some embodiments according to the present invention in a integrated form factor.

In this description, the same components have been given the same reference numbers, regardless of whether they are shown in different examples. In order to clearly and concisely illustrate one or more examples, the drawings are not necessarily to scale, and certain features may be shown in somewhat schematic form. Features described and/or illustrated with respect to one example may be used in an equivalent or similar manner in one or more other examples and/or in combination with or in place of the features of the other examples.

As used in the specification and claims, for purposes of describing and defining the disclosure, the terms "about" and "substantially" are used to represent the inherent degree of uncertainty associated with any quantitative comparison, value, measurement, or other representation can be attributed. The terms "approximately" and "substantially" are also used herein to represent the degree to which a quantitative representation may differ from a given reference without resulting in a change in the basic function of the subject matter. Comprising, containing, including, and/or plural forms of each of these are open-ended and include the parts listed and may include additional parts not listed. And/or is open-ended and includes one or more of the listed parts and combinations of the listed parts.

Although this document contains many details, these should not be construed as limitations on the scope of a claimed invention or what can be claimed, but rather as descriptions of features specific to particular embodiments. Certain features that are described in this document in connection with separate embodiments can also be used in combination be implemented in a single embodiment. Conversely, various features that are described in the context of a single embodiment may also be implemented in multiple embodiments separately or in any suitable sub-combination. Furthermore, although features are described above as functioning in certain combinations and can even initially be claimed as such, in some cases one or more features from a claimed combination may be removed from the combination and the claimed combination may be reduced to a sub-combination or a variation be directed to a sub-combination. Similarly, although acts are shown in the drawings in a particular order, it should not be construed that such acts must be performed in the particular order shown or in the sequential order, or that all acts shown must be performed in order to obtain desired results achieve.

Only a few examples and implementations are disclosed. Variations, modifications, and improvements to the examples and implementations described and other implementations can be made based on what is disclosed. Similarly, although acts are shown in the drawings in a particular order, it should not be construed that such acts must be performed in the particular order shown or in the sequential order, or that all acts shown must be performed in order to obtain desired results achieve. Furthermore, the separation of various system components in the embodiments described in this patent document should not be construed as requiring such separation in all embodiments.

While the foregoing is a complete description of specific embodiments, various modifications, alternative constructions, and equivalents may be used. As an example, the packaged device may include any combination of elements described above as well as outside of the present specification. Therefore, the above description and illustrations should not be taken as limiting the scope of the present invention, which is defined by the appended claims.

QUOTES INCLUDED IN DESCRIPTION

This list of the documents cited by the applicant was generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

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Claims (80)

Integrated RF circuit device comprising: a substrate; a high electron mobility (HEMT) transistor device on the substrate including a ScAlN layer configured to provide a buffer layer of the HEMT device to limit the formation of a 2DEG channel region of the HEMT device; and an RF piezoelectric resonator device on the substrate including the ScAlN layer sandwiched between an upper electrode and a lower electrode of the RF piezoelectric resonator device to provide a piezoelectric resonator for the RF piezoelectric resonator device. Integrated RF circuit device according to claim 1 , further comprising: a piezoelectric RF resonator cavity between the bottom electrode and the substrate. Integrated RF circuit device according to claim 1 , wherein the HEMT device further comprises: a GaN channel layer on the ScAlN layer; a barrier layer on the GaN channel layer to provide the 2DEG channel region in the GaN channel layer; a GaN drain region recessed into the GaN channel layer at a first end of the 2DEG channel region; a GaN source region recessed into the GaN channel layer at a second end of the 2DEG channel region opposite the first end of the 2DEG channel region; and a gate electrode between the GaN drain region and the GaN source region opposite to the barrier layer and configured to modulate the 2DEG channel region in the GaN channel layer Integrated RF circuit device according to claim 1 , wherein the ScAlN layer is stress balanced relative to a GaN channel layer of the HEMT device located on the ScAlN layer. Integrated RF circuit device according to claim 4 , wherein the ScAlN layer comprises Sc _0.18 Al _0.82 N. Integrated RF circuit device according to claim 4 , wherein the HEMT device further comprises: a GaN channel layer on the ScAlN layer; and a ScAlN barrier layer on the GaN channel layer to provide the 2DEG channel region in the GaN channel layer. Integrated RF circuit device according to claim 4 , wherein the HEMT device further comprises: a GaN channel layer on the ScAlN layer; and an AlGaN barrier layer on the GaN channel layer to provide the 2DEG channel region in the GaN channel layer. Integrated RF circuit device according to claim 4 , wherein the HEMT device further comprises: a GaN channel layer on the ScAlN layer; an AlN sub-barrier layer on the GaN channel layer; and a barrier layer including AlN on the AlN sub-barrier layer to provide the 2DEG channel region in the GaN channel layer. Integrated RF circuit device according to claim 1 , wherein the ScAlN layer comprises a single crystal ScAlN material. Integrated RF circuit device according to claim 9 , wherein the single crystal ScAlN material has a crystalline structure characterized by an XRD rocking curve FWHM value in a range between about less than 1.0 degrees and about 0.001 degrees as measured at a two-theta (2Θ ), is marked. Integrated RF circuit device according to claim 1 wherein the substrate comprises a silicon <100> substrate. Integrated RF circuit device according to claim 1 , wherein the ScAlN layer comprises a Sc _0.18 Al _0.82 N layer having a thickness of about 2 microns to about 0.01 microns, the HEMT device further comprising: a GaN channel layer on the Sc _{0, 18} Al _0.82 N layer, wherein the GaN channel layer has a thickness of about 0.1 micron to about 1.0 micron; and a ScAlN barrier layer on the GaN channel layer, the ScAlN barrier layer having a thickness of from about 200 nm to about 0.01 microns. Integrated RF circuit device according to claim 3 , further comprising: a GaN or SiN passivation layer between the gate electrode and the barrier layer. Integrated RF circuit device according to claim 3 , further comprising: a passivation layer grown directly on the barrier layer. Integrated RF circuit device according to claim 3 , wherein the GaN channel layer comprises an epi-GaN channel layer on the ScAlN layer. Integrated RF circuit device according to claim 3 , wherein the barrier layer further includes Sc, Ga or In. Integrated RF circuit device according to claim 15 , wherein the epi-GaN channel layer further comprises In and Al. Integrated RF circuit device according to claim 3 , wherein the GaN channel layer comprises In _x Ga _(1-x) N, where x ranges from greater than about 0.08 to about 0.12. Integrated RF circuit device according to claim 3 , wherein a spacing between the GaN drain region and the GaN source region is less than 5 micrometers and a breakdown field of the HEMT device is at least about 1.0 MV/cm to about 6.0 MV/cm. Integrated RF circuit device according to claim 3 , wherein a top surface of the barrier layer is located about 2 nm or less from a top surface of the HEMT device. Integrated RF circuit device according to claim 3 , further comprising: an amorphous AlN passivation layer between the gate electrode and the barrier layer. Integrated RF circuit device according to claim 1 wherein the HEMT device further comprises: a Group III N-channel layer grating matched to and on the ScAlN layer; a group III-N junction layer on the group III-N channel layer, the group III-N junction layer having a stress in a range between about -400 MPa and about +400 MPa, and around a channel region in the to provide Group III N-channel layer; a Group III N drain region recessed into the Group III N channel layer at a first end of the channel region; a Group III N source region recessed into the Group III N channel layer at a second end of the channel region opposite the first end of the channel region; and a gate electrode between the Group III N drain region and the Group III N source region. Integrated RF circuit device according to Claim 22 , where the Group III-N junction has a band gap of about 6 eV at room temperature. Integrated RF circuit device according to Claim 22 wherein a spacing between the Group III N drain region and the Group III N source region is less than 3 microns and a breakdown field of the HEMT device is at least about 1.0 MV/cm to about 6, is 0 MV/cm. Integrated RF circuit device according to Claim 22 wherein a top surface of the group III N junction is located about 2 nm or less from a top surface of the HEMT device extending between the gate electrode and the group III N drain region. Integrated RF circuit device according to Claim 22 , wherein the Group III-N barrier layer comprises ScAlN. Integrated RF circuit device according to claim 1 wherein the HEMT device further comprises: a Group III N-channel layer on the ScAIN layer; a group III-N junction layer on the group III-N channel layer to provide a channel region in the group III-N channel layer; a Group III-N cap layer on the Group III-N barrier layer; and wherein at least one of the Group III-N channel layer, the Group III-N barrier layer, and the Group III-N cap layer is configured to provide stress balancing relative to the ScAlN. An RF integrated circuit device comprising: a substrate; a piezoelectric resonator cavity on the substrate; a ScAlN piezoelectric resonator on the substrate and extending across the piezoelectric resonator cavity; a bottom electrode on the ScAlN piezoelectric resonator in the piezoelectric resonator cavity; a GaN channel layer grown on the ScAlN piezoelectric resonator over the piezoelectric resonator cavity; a barrier layer on the GaN channel layer to provide a 2DEG channel region in the GaN channel layer defined by the ScAlN piezoelectric resonator; a GaN drain region recessed into the GaN channel layer at a first end of the 2DEG channel region; a GaN source region recessed into the GaN channel layer at a second end of the 2DEG channel region opposite the first end of the channel region; and a gate electrode between the GaN drain region and the GaN source region of the junction layer and configured to modulate the 2DEG channel region in the GaN channel layer Integrated RF circuit device comprising: a silicon substrate; and a ScAIN layer providing a buffer layer for an epi-grown material stack included in a high electron mobility (HEMT) RF transistor device on the silicon substrate, and providing a piezoelectric resonator structure included in an RF filter on the silicon substrate is. Integrated RF circuit device according to claim 29 , wherein the ScAlN layer is configured to limit the formation of a 2DEG channel region in a GaN channel layer in the epi-grown material stack of the HEMT device. Integrated RF circuit device according to claim 29 , wherein the HEMT device comprises a first HEMT device that provides an amplified output signal in response to an input signal, the amplified output signal being coupled to an input of the RF filter configured to provide a filtered output signal, the device further comprising: a switch coupled to the filtered output signal, the switch including a second HEMT device on the substrate including the ScAlN layer, the switch configured to output either the filtered output signal or the input signal to a switching output to direct. Integrated RF circuit device according to claim 29 , wherein the HEMT device comprises a first HEMT device providing a switch configured to route a received signal from an antenna to an input of the RF filter to provide a filtered output, the device further comprising : a second HEMT device providing an amplifier configured to output an amplified signal. Integrated RF circuit device according to claim 29 , wherein the HEMT device comprises a power amplifier configured to provide an amplified signal to the RF filter. Integrated RF circuit device according to claim 29 , wherein the ScAlN layer comprises a Sc _x Al _1-x -N layer, where x ranges from about 0.18 to about 0.4. Integrated RF circuit device according to Claim 34 , wherein the Sc _x Al _1-x -N layer has a crystalline structure characterized by an XRD rocking curve FWHM value in a range between about less than 1.0 degrees and about 0.001 degrees measured about one scan angle Two-theta (2Θ). Integrated RF circuit device according to claim 29 wherein the piezoelectric resonator structure comprises a bulk acoustic wave (BAW) resonator or a surface acoustic wave resonator. Integrated RF circuit device according to claim 29 wherein the silicon substrate comprises a silicon <100> support substrate bonded to the ScAlN layer during fabrication. Integrated RF circuit device according to claim 29 , wherein the ScAlN layer comprises an epitaxially grown ScAlN layer. Integrated RF circuit device according to Claim 38 , wherein the epi-grown material stack is formed without a vacuum break. A method of forming an RF integrated circuit device, the method comprising: forming a Sc _x Al _1-x -N layer on a substrate, the Sc _x Al _1-x -N layer comprising a piezoelectric resonator region and a HEMT device region contains; forming a high electron mobility transistor (HEMT) channel layer on the Sc _x Al _1-x -N layer, wherein the HEMT channel layer is lattice-matched to the Sc _x Al _1-x -N layer to provide a 2DEG channel region ; forming a HEMT barrier layer on the HEMT channel layer, the HEMT barrier layer being lattice-matched to the Sc _x Al _1-x -N layer; and forming a piezoelectric resonator electrode on the piezoelectric resonator region. procedure after Claim 40 wherein forming the Sc _x Al ₁ -x -N layer comprises forming the Sc _x Al _1-x -N layer, where x = 0.18; and wherein forming the HEMT channel layer on the Sc _x Al _1-x -N layer comprises forming a GaN channel layer. procedure after Claim 40 wherein forming the Sc _x Al ₁ -x -N layer comprises forming the Sc _x Al _1-x -N layer, where x = 0.3; and wherein forming the HEMT channel layer on the Sc _x Al _1-x -N layer comprises forming an InGaN channel layer. procedure after Claim 40 , where the formation of the Sc _x Ali- _x -N layer is preceded by: Forming an AlN seed layer directly on the substrate. procedure after Claim 40 , wherein forming the Sc _x Al _1-x -N layer is preceded by: forming a GaN seed layer directly on the substrate. procedure after Claim 40 , wherein forming the HEMT barrier layer comprises forming a Sc _x Al _1-x -N barrier layer or an AlGaN barrier layer. procedure after Claim 45 , wherein forming the HEMT junction layer is preceded by: forming an AlN sub-junction layer directly on the HEMT channel layer. procedure after Claim 40 wherein processes from forming the Sc _x Al _1-x -N layer to forming the HEMT barrier layer include epitaxial growth processes performed without vacuum breaking. procedure after Claim 40 , wherein forming the Sc _x Al _1-x -N layer comprises forming the Sc _x Al _1-x -N layer to a thickness in a range between about 200 nm and 800 nm. procedure after Claim 40 , wherein forming the HEMT channel layer comprises forming the HEMT channel layer to a thickness in a range between about 0.5 microns and about 1.0 microns, procedure after Claim 40 , wherein forming the HEMT barrier layer comprises forming the HEMT barrier layer to a thickness in a range between about 50 nm and about 2 nm. procedure after Claim 40 , wherein the Sc _x Al _1-x -N layer comprises a single crystal Sc _x Al _1-x -N material. procedure after claim 5 wherein forming the Sc _x Al _1-x -N layer further comprises: providing a Sc precursor in a reaction chamber via a heated precursor line to form the single crystal Sc _x Al _1-x -N material on the substrate . procedure after Claim 52 , wherein the single crystal Sc _x Al _1-x -N material has a crystalline structure characterized by an XRD rocking curve FWHM value in a range between about less than 1.0 degree and about 0.001 degree, measured at a scan angle two theta (2Θ). procedure after Claim 52 wherein the heated precursor wire is heated to a temperature in a range between about 60 degrees Celsius and about 120 degrees Celsius. procedure after Claim 54 wherein the heated precursor conduit is between a source of Sc precursor and the reaction chamber. procedure after Claim 40 , wherein the substrate comprises a silicon <111> substrate, a SiC substrate or an Al ₂ O ₃ substrate. procedure after Claim 40 , further comprising: prior to forming the Sc _x Al _1-x -N layer, providing NH ₃ on a surface of the substrate at a temperature in a range between about 700 degrees Celsius and about 1200 degrees Celsius. procedure after Claim 40 wherein the RF integrated circuit device comprises a surface acoustic wave resonator device. procedure after Claim 40 wherein the RF integrated circuit device comprises a bulk acoustic wave resonator device. A method of forming an RF integrated circuit device, the method comprising: forming a single crystal Sc _x Al _1-x -N layer on a substrate; forming a high electron mobility transistor (HEMT) device including a channel layer and a depletion layer of the HEMT device on the single crystal Sc _x Al _1-x -N layer; and forming an RF piezoelectric resonator device from the single crystal Sc _x Al _1-x -N layer, the single crystal Sc _x Al _1-x -N layer being sandwiched between an upper electrode and a lower electrode of the piezoelectric RF resonator device is arranged to provide a piezoelectric resonator for the RF piezoelectric resonator device. procedure after Claim 60 , wherein the formation of the single-crystal Sc _x Al _1-x -N layer, the channel layer and the barrier layer of the HEMT device is performed without vacuum breaking. procedure after Claim 60 , wherein forming the single crystal Sc _x Al ₁ -x -N layer comprises forming the single crystal Sc _x Al _1-x -N layer, where x ranges from about 0.18 to about 0.4 . procedure after Claim 62 , wherein the channel layer comprises a GaN channel layer lattice-matched to the single crystal Sc _x Al _1-x -N layer. procedure after Claim 60 , wherein the channel layer strained on the single crystal Sc _x Al _1-x -N layer is stress balanced relative to the channel layer. procedure after Claim 64 , wherein a stress on the channel layer is in a range between about -400 MPa and about +400 MPa. procedure after Claim 65 wherein the substrate comprises a growth substrate, the method further comprising: epitaxially forming the single crystal Sc _x Al _1-x -N layer on a first side of the growth substrate; forming the channel layer and the barrier layer of the HEMT device on a first surface of the single crystal Sc _x Al _1-x -N layer over the first side of the growth substrate; forming the bottom electrode on the first surface of the single crystal Sc _x Al _1-x -N layer over the first side of the growth substrate; forming a sacrificial layer on the bottom electrode and on the barrier layer of the HEMT device; coupling the bottom electrode of the RF piezoelectric resonator device and the HEMT device to a support substrate over the first side of the growth substrate; and processing a second side of the growth substrate opposite to the first side of the growth substrate to expose a second surface of the single crystal Sc _x Al _1-x -N layer opposite to the first surface of the single crystal Sc _x Al _1-x -N- layer lies. procedure after Claim 66 , further comprising: forming a recess in the single crystal Sc _x Al _1-x -N layer to expose the bottom electrode; depositing a first metal on the second surface of the single crystal Sc _x Al _1-x -N layer to form a top electrode for the piezoelectric RF resonator device and in the recess to contact the bottom electrode; and forming a heat sink layer on the second surface of the single crystal Sc _x Al _1-x -N layer of the HEMT device spaced from the top electrode. procedure after Claim 67 , further comprising: removing the sacrificial layer from the bottom electrode and from the barrier layer of the HEMT device to form a resonator cavity and a parasitic HEMT capacitance cavity, respectively. procedure after Claim 67 , further comprising: depositing a second metal on the top electrode and on the first metal in the cavity to form a top electrode contact and a bottom electrode contact, respectively. procedure after Claim 69 , further comprising: depositing the second metal on the barrier layer to provide a source contact and a drain contact for the HEMT device. procedure after Claim 66 wherein forming the channel layer and the barrier layer of the HEMT device on the first surface of the single crystal Sc _x Al _1-x -N layer over the first side of the growth substrate is followed by: forming a protective HEMT layer on the HEMT device; and then forming the bottom electrode on the first surface of the single crystal Sc _x Al _1-x -N layer over the first side of the growth substrate. procedure after Claim 71 wherein forming the bottom electrode on the first surface of the single crystal Sc _x Al _1-x -N layer over the first side of the growth substrate is followed by: forming a resonator protection layer on the sacrificial layer and the bottom electrode; polishing a top surface of the resonator protection layer and a top surface of the HEMT protection layer; and then coupling the top surface of the resonator protection layer and the top surface of the HEMT protection layer to the supporting substrate. procedure after Claim 72 , further comprising: forming a recess in the single crystal Sc _x Al _1-x -N layer to expose the bottom electrode; depositing a first metal on the second surface of the single crystal Sc _x Al _1-x -N layer to form a top electrode for the piezoelectric RF resonator device and in the recess to contact the bottom electrode; and forming a heat sink layer on the second surface of the single crystal Sc _x Al _1-x -N layer of the HEMT device spaced from the top electrode. A method of forming a monolithic RF-HEMT/resonator integrated circuit device, the method comprising: epitaxially forming a single crystal Sc _x Al _1-x -N layer on a substrate; epitaxially forming a HEMT-III N-channel layer on the single crystal Sc _x Al _1-x -N layer, wherein the HEMT-III N-channel layer is lattice-matched to the single crystal Sc _x Al _1-x -N layer; epitaxially forming a HEMT-III N-junction layer on the HEMT-III N-channel layer; forming a source recess in the HEMT-III N-junction layer and in the HEMT-III N-channel layer; forming a drain recess in the HEMT-III N-junction layer and in the HEMT-III N-channel layer; forming a III-N material in the source recess and in the drain recess to provide a HEMT source region and a HEMT drain region, respectively; forming a gate recess in the HEMT-III N-junction layer between the source recess and the drain recess; and depositing a metal on the single crystal Sc _x Al _1-x -N layer, on the HEMT source region and on the HEMT drain region to form a bottom electrode for the resonator and a HEMT source contact and HEMT source contact respectively to form a HEMT drain contact. procedure after Claim 74 wherein the epitaxial growth of the single crystal Sc _x Al _1-x -N layer, the epitaxial growth of the HEMT-III-N channel layer, and the epitaxial growth of the HEMT-III-N barrier layer are performed without vacuum breaking. procedure after Claim 74 wherein epitaxially forming the HEMT-III-N barrier layer is followed by: forming a III-N-HEMT cap layer on the HEMT-III-N barrier layer. procedure after Claim 74 wherein epitaxially forming the HEMT-III N-junction layer is followed by: forming a SiN cap layer on the HEMT-III N-junction layer. procedure after Claim 74 wherein epitaxially forming the HEMT-III-N barrier layer is followed by: forming an amorphous AlN cap layer on the HEMT-III-N barrier layer. procedure after Claim 74 wherein the single crystal Sc _x Al ₁ -x -N layer comprises the single crystal Sc _x Al _1-x -N layer, where x ranges from about 0.18 to about 0.4, and the single crystal -Sc _x Al _1-x -N layer has a crystalline structure characterized by an XRD rocking curve FWHM value in a range between about less than 1.0 degree and about 0.001 degree measured about one scan angle Two-theta (2Θ). procedure after Claim 74 , further comprising: forming a sacrificial layer on the bottom electrode, on the HEMT source contact, and on the HEMT drain contact.

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