CN115280525A

CN115280525A - RF acoustic wave resonator integrated with high electron mobility transistor including shared piezoelectric/buffer layer and method of forming the same

Info

Publication number: CN115280525A
Application number: CN202180007983.XA
Authority: CN
Inventors: 杰弗里·B·谢利; 玛丽·温特斯; 克雷格·莫伊
Original assignee: Akoustis Inc
Current assignee: Akoustis Inc
Priority date: 2020-01-21
Filing date: 2021-01-19
Publication date: 2022-11-01
Also published as: WO2021150496A1; DE112021000647T5; KR20220130120A

Abstract

An RF integrated circuit device may include a substrate and a High Electron Mobility Transistor (HEMT) device on the substrate, the HEMT device including a ScAlN layer configured to provide a buffer layer of the HEMT device to define formation of a 2DEG channel region of the HEMT device. The RF piezoelectric resonator device may be on a substrate including a ScAlN layer sandwiched between top and bottom electrodes of the RF piezoelectric resonator device to provide a piezoelectric resonator for the RF piezoelectric resonator device.

Description

RF acoustic wave resonator integrated with high electron mobility transistor including shared piezoelectric/buffer layer and method of forming the same

Technical Field

This application claims priority to U.S. patent application No. 62/963,915, entitled "Transporter BAW (TBAW) Filter Monolithic Integration" filed on USPTO (U.S. patent and trademark office) at 21/1/2020, and to U.S. patent application No. 16/990,638, filed on USPTO at 11/8/2020; the latter is a continuation-in-part application of U.S. patent application Ser. No. 16/822,689, filed on USPTO at 18/3/2020; the latter is a continuation of U.S. patent application Ser. No. 16/433,849, which was filed on USPTO on 6/2019; the latter is a continuation of U.S. patent application Ser. No. 15/784,919, now U.S. patent No. 10,355,659, filed on 16/10/2017; the latter is U.S. patent application Ser. No. 15/068,510, filed on USPTO at 11.3.2016, now a continuation-in-part application of U.S. patent No. 10,217,930, the entire disclosure of which is incorporated herein by reference in its entirety.

Background

Piezoelectric-based semiconductor resonator devices have been developed for use as filters and oscillators in integrated circuit devices. For example, it is known to utilize piezoelectric material surface acoustic wave resonators or piezoelectric material bulk acoustic wave resonators as part of a filter in a mobile communication device.

High Electron Mobility Transistors (HEMTs) have been used as amplifiers in RF applications. HEMT devices are further discussed, for example, in U.S. patent application publication No. US2015/0028346, the disclosure of which is incorporated herein by reference.

Disclosure of Invention

The RF integrated circuit device may include a substrate and a High Electron Mobility Transistor (HEMT) device on the substrate, the HEMT device including a ScAlN layer configured to provide a buffer layer of the HEMT device to define (define) formation of a 2DEG channel region of the HEMT device. An RF piezoelectric resonator device may be on a substrate including a ScAlN layer sandwiched between top and bottom electrodes of the RF piezoelectric resonator device to provide a piezoelectric resonator for the RF piezoelectric resonator device.

Drawings

FIG. 1A is a cross-sectional schematic view of a monolithic RF BAW piezoelectric resonator and HEMT device including shared Sc in some embodiments according to the invention_xAl_1-xN layer of the Sc_xAl_1-xThe N layer provides a piezoelectric layer in the piezoelectric resonator and provides a buffer layer in the HEMT device.

Fig. 1B is a circuit diagram illustrating the monolithic RF BAW piezoelectric resonator and HEMT device of fig. 1A in some embodiments according to the present invention.

FIG. 2 is a schematic representation of a semiconductor device including a common Sc as a barrier layer in some embodiments according to the invention_xAl_1-xA detailed cross-sectional view of a portion of a HEMT stack of semiconductor material in part a of fig. 1A of the N layer.

3A-24D are cross-sectional views illustrating the use of a sacrificial layer to form a resonator cavity and a HEMT parasitic capacitance cavity to form a common Sc including FIG. 1A in some embodiments according to the invention_xA1_1-xMonolithic RF BAW piezoelectric resonators of N layers and transfer process of HEMT devices.

FIGS. 25A-36D are cross-sectional views illustrating the use of a patterned support layer to form a resonator cavity and a HEMT parasitic capacitance cavity in a bonding process to form a common Sc including FIG. 1A in some embodiments according to the invention_xA1_1-xMonolithic RF BAW piezoelectric resonators of N layers and transfer process of HEMT devices.

FIGS. 37A-47D are cross-sectional views illustrating the formation of a bag in some embodiments according to the inventionIncluding common Sc_xAl_1-xN-layer, monolithic RF BAW piezoelectric resonator with multilayer mirror, and HEMT device transfer process.

FIG. 48 is a table including common Sc in some embodiments according to the invention_xAl_1-xA cross-sectional view of a monolithic RF SAW piezoelectric resonator and HEMT device of N layer, the Sc_xAl_1-xThe N layer provides a piezoelectric layer in the piezoelectric resonator and a buffer layer in the HEMT device.

Fig. 49 is a schematic diagram of a transmit module in some embodiments according to the invention, including a BAW filter, an amplifier implemented using at least one HEMT device, and a switch implemented using at least one HEMT device, assembled in an integrated manner.

Fig. 50 is a schematic diagram of a partial full front end module (CFE) high band device including a BAW filter, an amplifier implemented using at least one HEMT device, and a switch implemented using at least one HEMT device assembled in an integrated manner in some embodiments according to the invention.

Fig. 51 is a schematic diagram of a switched-duplex bank including at least one BAW filter and at least one switch (implemented using at least one HEMT device, such as a bypass switch or a multi-throw switch) assembled in an integrated manner, in some embodiments according to the invention.

Fig. 52 is a schematic diagram of an antenna switch module including at least one BAW filter and at least one switch (implemented using at least one HEMT device, such as a bypass switch or a multi-throw switch) assembled in an integrated manner in some embodiments according to the invention.

Fig. 53 is a schematic diagram of a diversity receiving FEM including at least one low noise amplifier implemented using at least one HEMT device, at least one BAW filter, and at least one switch implemented using at least one HEMT device assembled in an integrated manner in some embodiments according to the invention.

Fig. 54 is a schematic diagram of a Power Amplifier (PA) duplexer in some embodiments according to the invention, including at least one power amplifier implemented using at least one HEMT device, and at least one BAW filter assembled in an integrated manner.

Detailed Description

In accordance with the present invention, techniques are provided that generally relate to electronic devices. More particularly, the present invention provides techniques related to fabrication methods and structures for acoustic wave resonator devices integrated with high electron mobility transistor devices, both of which include a single crystal piezoelectric layer that can be shared by both devices to provide synergistic functional and structural advantages for each device. Merely by way of example, the present invention has been applied to single crystal resonator devices for use in communication devices, mobile devices, computing devices, and the like.

As understood by the present inventors, the performance of a piezoelectric resonator device can be improved by providing a high quality single crystal piezoelectric layer, particularly at frequencies in the 5G range. However, forming such high quality single crystal piezoelectric layers can be difficult because some piezoelectric materials (such as AlN) tend to crack or otherwise fail due to thermal issues or increased stress generated by epitaxial type processes commonly used to form single crystal piezoelectric layers. For example, some epitaxial processes may grow piezoelectric material on Si, where the temperature may exceed about 1000 degrees celsius. When the wafer is cooled, the material may crack due to induced excessive stress (especially when the piezoelectric material is formed to a thickness suitable for high frequency applications such as 5G). As further understood by the inventors, strain balancing may be used to counteract the stress described above by growing other layers on the piezoelectric material, such as a cap configured to make the piezoelectric material resistant to cracking.

Thus, as understood by the inventors, integrating the piezoelectric resonator device with the HEMT device may provide some advantages for the formation and performance of each device. In particular, one or more layers (e.g., channel layers) of a HEMT device can be an epitaxially grown piezoelectric layer (such as Sc) by growing the channel layer on the piezoelectric layer as part of an epitaxial process_xAl_1-xN layers) provide strain balance. In addition, the piezoelectric layer may also be provided for forming a HEMT channel layer (such as Ga)N) is used. Further, when the piezoelectric resonator device and the HEMT device are fabricated as monolithically integrated devices, the same piezoelectric layer may be shared by both devices. For example, sc_xAl_1-xThe N layer may extend across the substrate to provide Sc of the resonator device at a first region of the substrate_xAl_1-xAn N piezoelectric layer and providing Sc of the HEMT device at the second region of the substrate_xAl_1-xAnd an N buffer layer.

In some embodiments, strain balancing includes configurations in which a common piezoelectric layer can be stress balanced with respect to the HEMT channel layer. In some embodiments, the strain may be considered "stress balanced" if the strain between the common piezoelectric layer and the HEMT channel layer is in a range between about +400MPa and about-400 MPa.

As further understood by the inventors, in some embodiments, sc_xAl_1-xThe N piezoelectric layer may provide a relatively high K and may provide a good lattice match for the formation of the HEMT channel layer. Further, sc_xAl_1-xThe composition of N may be configured to tune K along with configuring the lattice to accommodate growth of other III-N channel layers of the HEMT device. For example, in some embodiments, sc_0.18Al_0.82N can be used for good K and good lattice matching of the GaN channel. In other embodiments, sc_0.30Al_0.70N may be used to provide lattice matching for the InGaN channel. Other III-N materials may be used for the channel layer, these materials may be combined with Sc_xA1_1-xThe N common layers match.

Methods of forming a piezoelectric resonator device integrated with a HEMT device may utilize a transfer process by forming a stack of semiconductor materials including a common piezoelectric layer and a remaining HEMT layer including a III-N channel layer (on the piezoelectric layer as a buffer layer for the HEMT), a barrier layer and optionally a cap. The HEMT stack may be further processed to form source and drain regions and a gate. Metallization of ohmic contacts to the source, drain and gate electrodes may also be used to form the bottom electrode of the resonator.

The entire structure (resonator and HEMT) can then be transferred to a carrier substrate (such as Si <100 >) so that the growth substrate (on which the common piezoelectric layer and HEMT stack are grown) can be removed. Once the growth substrate is removed, the exposed backside of the piezoelectric layer can be processed to form, for example, the top electrode (for the resonator) and to form vias and contacts (for the resonator and HEMT). Thus, the transfer process allows the use of both sides of the common piezoelectric layer (for both the resonator and the HEMT). As further understood by the inventors, in some embodiments according to the invention, the surface acoustic wave resonator device can also be integrated with the HEMT device through a common piezoelectric layer, which may not utilize a transfer process. It will be appreciated that other materials may be used as the carrier substrate in some embodiments according to the invention.

As further understood by the inventors, in some embodiments according to the invention, the thickness of the HEMT channel layer may be configured to provide strain balance for forming the common piezoelectric layer. In particular, the thickness of the HEMT channel layer is generally reduced. However, as understood by the present inventors, in some embodiments according to the present invention, the thickness of the HEMT channel layer may be increased to provide an improved strain balance for the underlying common piezoelectric layer. Thus, the thickness and composition of the HEMT channel layer (and the corresponding thickness and composition of the HEMT barrier cap layer) may be configured for strain balancing.

Still further, in some embodiments according to the invention, the growth substrate may be conditioned with hot nitrogen gas prior to growth of the common piezoelectric layer. For example, NH may be provided to the surface of the growth substrate₃(e.g. SiC or Al)₂O₃) To form SiN at the surface of the growth substrate. Due to stress compensation, siN may enable growth of a thicker common piezoelectric layer, which may also be more resistant to cracking after the epitaxial process. In some embodiments according to the invention, the growth substrate can be silicon<111>Or SiC. Other materials may also be used for the growth substrate.

Fig. 1A is a cross-sectional schematic view of a monolithic RF Bulk Acoustic Wave (BAW) piezoelectric resonator device 105 integrated with a HEMT device 100 in some embodiments according to the invention, the piezoelectric resonator device 105 and HEMT device 100 comprising a common bulk acoustic wave (HEMT) resonatorSc of (2)_xA1_1- _xN layer 110, sc_xA1_1-x The N layer 110 provides a piezoelectric layer in the piezoelectric resonator device 105 and a buffer layer in the HEMT device 100. According to FIG. 1A, sc in common_xA1_1-xThe N layer 110 extends across the monolithic carrier substrate 115 to provide the piezoelectric layer of the resonator device 105 and the buffer layer of the HEMT device 100. The HEMT device 100 includes a HEMT material a stack that forms the active layer of the HEMT device 100, the HEMT material a stack including a III-N channel layer 120, a barrier layer 125 and an optional cap layer 130 (fig. 12).

It will be understood that in some embodiments, HEMT material a stack and common Sc_xAl_1-x The N layer 110 can be epitaxially grown on the carrier substrate 115 without stacking and sharing Sc on the HEMT material a_xAl_1-xVacuum break is introduced during the formation of the N layer 110. In other words, once the reaction chamber for the epitaxial process reaches temperature, the process continues until the formation of the HEMT material stack is completed before allowing the temperature to cool.

As further shown in fig. 1A, a common Sc_xAl_1-x The N layer 110 is sandwiched between a bottom electrode 135 and a top electrode 140. The bottom electrode 135 is separated from the carrier substrate 115 by a resonator cavity 145, which allows sharing of Sc_xAl_1-xPortions of N layer 110 between top electrode 135 and bottom electrode 140 in response to the impact on common Sc_xAl_1-xElectromagnetic energy on portions of N layer 110 resonates, producing an electrical response at top electrode 135 and bottom electrode 140. The resonator cavity 145 also allows for common Sc_xAl_1-xThe portion of N layer 110 between top electrode 135 and bottom electrode 140 resonates in response to an electrical signal applied to top electrode 135 and bottom electrode 140. Further, sc in common_xAl_1-xThe resonance of the N layer 110 may be subject to a common Sc_xAl_1-xInfluence of the level of Sc included in the N layer 110.

It will be further understood that Sc is included in the common use_xAl_1-xThe level of Sc in the N layer 110 also determines the common Sc_xAl_1-xThe lattice structure of N layer 110, thereby enabling other materials (such asIII-N channel layer) can be more easily lattice matched to the underlying common Sc_xAl_1-xN layers 110. For example, in some embodiments according to the invention, sc_0.18Al_0.72The N layer is closely matched to the lattice structure of GaN. Thus, in some embodiments according to the invention, a common Sc that can be included in the HEMT device 100_0.18Al_0.72A GaN channel layer 120 is grown on the region of the N layer. It will be understood that Sc_xAl_1-xOther compositions of N layer 110 may be used for different III-N channel layers 120, such as InGaN, inGaAsN.

As further shown in fig. 1A, the HEMT device 100 also includes a parasitic capacitance cavity 150 between the HEMT material stack a and the carrier substrate 115. It will be understood that the resonator cavity 145 and the parasitic capacitance cavity 150 may be formed in the same step or may be formed separately. Further, the resonator cavity 145 and the parasitic capacitance cavity 150 may have different volumes and may be spaced apart from the carrier substrate 115 by different amounts. In some embodiments, the resonator cavity 145 and the parasitic capacitance cavity 150 may also be filled with a gas (such as air) or may be a vacuum.

As shown in FIG. 1A, sc in common_xAl_1-x The N layer 110 includes an opening exposing the bottom electrode 135 so that a conductive material may be formed in the opening. The conductive material protrudes from the opening to couple to the bottom electrode contact 2920. The top electrode 140 includes a recess 2912 in an upper surface thereof. Contact 2610 is at common Sc_xAl_1-xOn the upper surface of the N layer 110 and coupled to the top electrode 140. Although not shown in fig. 1A, the resonator device 105 may also include a cavity located above the top electrode 140. It will also be understood that the cavities described herein may also be any shape that provides the described functionality.

As further shown in fig. 1A, the HEMT device 100 includes a source region 175, a drain region 180, and a gate 185 located at a level closest to the carrier substrate 115 in the HEMT stack a. Thus, the source 175, drain 180, and gate 185 of the HEMT device 100 are located at a common Sc with the bottom electrode 140 of the resonator device 105_xAl_1-xOn the same side of the N layers 110. Further, in the present invention, it is preferable that,corresponding

metallizations

190 and 195 extend from source region 175 and drain region 180 of HEMT stack a to corresponding contacts 1905, each extending through the common Sc_xA1_1-xN layers 110. It will be understood that in some embodiments according to the invention, the respective metallizations 190 and 195 can be formed in the same step as the bottom electrode 140. Still further, in some embodiments according to the invention, the respective contacts 1905 may be formed in the same step used to form the top electrode 140.

Both the HEMT device 100 and the resonator device 105 are supported by a dielectric layer 1420 (sometimes referred to herein as a support layer), the dielectric layer 1420 forming a lower wall of each of the resonator cavity 145 and the parasitic capacitor cavity 150 adjacent to a surface of the carrier substrate 115.

Fig. 1B is a circuit 220 diagram illustrating the monolithic RF BAW piezoelectric resonator 105 and HEMT device 100 of fig. 1A in some embodiments according to the present invention. In particular, fig. 1B illustrates that contacts of the BAW piezoelectric resonator 105 and contacts of the HEMT device 100 may be coupled together to form a circuit such as shown in fig. 49-54 in some embodiments according to the present invention.

FIG. 2 is a table including common Sc in some embodiments according to the invention_xA1_1-xA detailed cross-sectional view of the HEMT semiconductor material stack a in fig. 1A of the N layer 110. According to FIG. 2, sc in common_xA1_1-xThe N layer 110 extends across the carrier substrate 115 and is included in the RF BAW piezoelectric resonator 105 (as a piezoelectric resonator) and in the HEMT device 100 (as a buffer layer) in some embodiments. As further shown in fig. 2, a nucleation layer 110a may be formed on the growth substrate 2610 to facilitate common Sc_xAl_1-xEpitaxial growth of N layer 110. For example, depending on the Sc doping level, it may be in Si<100>Formation of AlN or GaN nucleation layers on substrate resonators to promote shared Sc_xAl_1-xEpitaxial growth of N layer 110. In some embodiments, the nucleation layer may be about 0.05 microns thick using, for example, ALD. It will be understood that the nucleation layer may be when the partially formed RF BAW piezoelectric resonator 105 and HEMT device 100 are transferred to the carrier substrate 115Is removed (in whole or in part) with the growth substrate 2610. In some embodiments, the growth substrate 2610 may be Si, siC, al₂O₃Or glass. Other carrier substrates may also be used.

Common Sc_xAl_1-x The N layer 110 can be formed to a thickness of about 0.5 microns using a method that provides a single crystal piezoelectric layer. In some embodiments, the single crystal piezoelectric layer may be formed via relatively ordered crystal growth (such as MOCVD, MBE, HVPE, etc.). In some embodiments according to the invention, sc is common_xAl_1-x The N layer 110 may be Sc formed to have a crystal structure_0.18Al_0.82N (sometimes referred to herein as 18% Sc), the crystal structure being characterized by an XRD ω -rocking curve FWHM value, which is in reference to Sc_xAl_1-xThe nc axis film reflects a measured 2 theta (2 theta) scan angle in a range between about less than 1.0 degree to about 0.001 degrees, e.g., as measured. In some embodiments, the level of Sc may be up to about 40% depending on the materials used for the III-N channel layer and the levels of those materials in the III-N channel layer.

The III-N channel layer 120 may be grown in common Sc_xAl_1-xA GaN channel layer on the N layer 110. In some embodiments, the GaN channel layer is grown to a thickness in a range between about 0.5 microns to about 1.0 microns. As understood by the inventors, the III-N channel layer 120 may be grown stress balanced with respect to the underlying common ScxA11-xN layer 110.

The barrier layer 125 may be selected to provide a relatively stress balanced barrier layer with a relatively large band offset and polarization with respect to the channel layer 120 to support definition of the 2DEG channel region and high voltage/power applications. In some embodiments, barrier layer 125 may be a common Sc with the underlying layers_xA1_1-x110-layer matched Sc N (buffered)_xA1_1-xAnd N crystal lattice. In some embodiments, the barrier layer 125 may be AlGaN. It will be appreciated that the barrier layer 125 may include a sub-barrier layer 123 adjacent to the interface with the channel layer 120, the sub-barrier layer 123 being more lattice matched to the channel layer 120 to facilitate a lower stress from the channel layer 120 to the barrier layer 125And (4) changing and transforming. In some embodiments, the sub-barrier 123 may be AlN formed to a thickness in a range between about 1 micron to about 0.005 micron, which may be converted to AlGaN or Sc as the formation progresses_xAl_1-xAnd N is added. In some embodiments, the sub-barrier layer 123 and the barrier layer 125 may be formed by changing the composition of the material in the process. For example, if the barrier layer 125 is ScAlN or AlGaN, the sub-barrier layer 123 may be initially formed as AlN and converted to include levels of Sc or Ga until the target composition of ScAlN or AlGaN as the barrier layer 125 is reached.

As further shown in fig. 2, HEMT stack a can include cap layer 130 grown on barrier layer 125. In some embodiments, cap layer 130 may be GaN formed to a thickness in the range of about 0.01 microns and 0.001 microns. In some embodiments, cap layer 130 may be removed. In other embodiments, amorphous AlN may be formed on the barrier layer 125.

13A-24 are cross-sectional views illustrating the use of a transfer structure (carrier substrate) and a sacrificial layer to form a resonator cavity and a HEMT parasitic capacitance cavity to form a common Sc including FIG. 1A in some embodiments according to the invention_xA1_1-xMonolithic RF BAW piezoelectric resonators of N layers and transfer process of HEMT devices. In the series of figures described below, figure "a" shows a diagram illustrating top cross-sectional views of a BAW piezoelectric resonator and HEMT device according to various embodiments of the present invention. The "B" diagram shows a diagram illustrating a longitudinal cross-sectional view of the same device in the "a" diagram. Similarly, the "C" diagram shows a diagram illustrating a lateral cross-sectional view of the same device in the "a" diagram. Similarly, the "D" diagram shows a simplified diagram of a top cross-sectional view of the HEMT device 100 showing a lateral cross-sectional view of the same device in the "a" diagram. In some cases, some features may be omitted to highlight other features and relationships between such features. Those of ordinary skill in the art will recognize variations, modifications, and alternatives to the examples shown in the series of figures.

According to fig. 3A-3C and 4-7, a piezoelectric layer 110 is formed on a growth substrate 1610. In some embodiments, growth substrate 1610 may comprise silicon (S)Silicon carbide (SiC) and Al₂O₃Or other similar material. The piezoelectric layer 110 can be Sc_xAl_1-xAn epitaxial layer of N or other similar material. Further, the piezoelectric layer 110 can be subjected to thickness trimming. It will be appreciated that fig. 4-7 illustrate an epitaxial growth process for forming a HEMT stack a that includes a piezoelectric layer 110, a III-N channel layer 120, a barrier layer 125 and an optional cap layer 130.

The epitaxial growth process may be performed such that the layers of the HEMT stack a are formed in the reaction chamber without cooling the HEMT stack a below the temperature at which epitaxial growth is performed. In particular, as shown in fig. 4-7, the piezoelectric layer 110 can be formed on a nucleation layer 110A of AlN or GaN, for example, on a growth substrate. A barrier layer 125 may be formed on the III-N channel layer using a sub-barrier layer 123, and an optional cap layer 130 may be formed on the barrier layer 125. After growth of the HEMT-stack a, further processing of the HEMT-stack may be performed outside the process or alternatively as part of the epitaxial growth process.

In some embodiments, the epitaxial growth process may be performed in a MOCVD system, where the piezoelectric layer 110 is Sc_xAl_1-xN as described In commonly assigned U.S. patent application Ser. No. 16/784,843, entitled "Apparatus For Forming Single Crystal Layers Using Low-Vapor Pressure Methods In CVD Systems And Methods Of Forming Single Crystal Layers Using The Same" filed on USPTO, for example, on 2, 7, 2020, which is hereby incorporated by reference In its entirety. Low vapor pressure Metal Organic (MO) precursors may be used according to some embodiments of the present invention to incorporate Sc dopants to a target concentration (e.g., 18%, 30%, or more) by heating the low vapor pressure MO precursors to a relatively high temperature, such as greater than 150 degrees celsius. For example, in some embodiments according to the invention, the CVD system may heat a low vapor pressure MO precursor, such as tris (cyclopentadienyl) Sc (i.e., (Cp) 3 Sc) and (MeCp) 3Sc, to at least 150 degrees celsius. Other low vapor pressure MO precursors can also be used in embodiments according to the invention to perform epitaxial growth of HEMT stack a without vacuum break, such asAs shown in fig. 4-7.

In some embodiments, a source vessel containing a source of a low vapor pressure Metal Organic (MO) precursor and a line delivering the low vapor pressure MO precursor vapor into a CVD reaction chamber may be heated to at least 150 degrees celsius. In some embodiments, the CVD reactor is a horizontal flow reactor that can produce a laminar flow of low vapor pressure MO precursor vapor over the wafers in the reactor. In some embodiments according to the invention, the horizontal flow reactor may comprise a planetary device that rotates and rotates the wafer table holding each wafer during the deposition process.

In some embodiments according to the invention, the low vapor pressure MO precursor can be any metal-organic material having a vapor pressure of 4.0Pa or less at room temperature. In some embodiments according to the invention, the low vapor pressure MO precursor can be any metal-organic material having a vapor pressure of about 4.0Pa to about 0.004Pa at room temperature. In still further embodiments according to the invention, the heating line that directs the low vapor pressure MO precursor vapor to the CVD reaction chamber is thermally isolated from the other MO precursors and hydrides. For example, in some embodiments, the heating line that directs the low vapor pressure MO precursor vapor to the CVD reaction chamber is provided to the central injection tower via a different path than the path used to provide the other precursors (such as through a flexible heating line connected to the moving portion of the CVD reactor). In particular, the other precursors may be provided to the central injection tower through a lower portion of the CVD reactor that remains stationary when the CVD reactor is opened by, for example, lifting an upper portion of the CVD reactor to open the CVD reaction chamber. Thus, when the CVD reactor chamber is in the open position, the upper and lower portions of the CVD reactor are separated from each other to expose, for example, the planetary arrangement described herein.

As understood by the inventors, providing the low vapor pressure MO precursor vapor to the central injection tower through a different pathway than other precursors may allow the low vapor pressure MO precursor vapor to be heated to a relatively high temperature without adversely affecting (e.g., heating) the other precursors, e.g., above room temperature. Thus, while other precursors may be provided via lines of other precursors routed through the lower portion that are configured to mate/unmate when the CVD reactor is closed/open, the heated low vapor pressure MO precursor lines to the central injection tower may remain as an integral flexible member that allows the upper portion to move when open/closed, yet be thermally isolated from the other precursors/precursor lines.

In some embodiments, the molar flow of the low vapor pressure MO precursor vapor is provided by a high temperature Mass Flow Controller (MFC) downstream of the heated low vapor pressure MO precursor source vessel. In some embodiments according to the invention, the MFC is located upstream of the heated low vapor pressure MO precursor source vessel, and the high temperature pressure controller is located downstream of the heated low vapor pressure MO precursor source vessel, coaxial with the line that directs the low vapor pressure MO precursor vapor to the CVD reaction chamber. Thus, in embodiments where a device (such as a high temperature MFC or high temperature pressure controller) is located co-axially with the line directing the low vapor pressure MO precursor vapor to the CVD reaction chamber downstream of the heated low vapor pressure MO precursor source vessel, the corresponding device is configured to operate at a relatively high temperature (such as greater than 150 degrees celsius).

In some embodiments, when Sc, ga, in, and Al are used In HEMT stack a, the temperature within the CVD reaction chamber can be maintained at a temperature In a range between about 800 degrees celsius and about 1500 degrees celsius. In some embodiments, when Sc, ga, al, and In are used In HEMT stack a, the temperature within the CVD reactor chamber may be maintained at a temperature In a range between about 600 degrees celsius to about 1000 degrees celsius.

As shown in fig. 8, sc of HEMT stack a in the region of the substrate assigned to the resonator device 105_xAl_1- _xPortions of the N piezoelectric layer 110 above can be removed to expose Sc_xAl_1-xThe surface of the N piezoelectric layer 110. May be in Sc_xAl_1-xA protective layer is formed on the surface of the N-piezoelectric layer 110 to avoid damage to the remaining portion of the HEMT stack a on the region of the substrate assigned to the HEMT device 100 during further processing. In some embodiments according to the invention, HEMT stack a can be maintained at Sc_xAl_1-xThe portion above the N piezoelectric layer 110 (shown removed in fig. 8) while the HEMT stack a is further processed as shown9-proceed as indicated at 12.

According to fig. 9-12, the HEMT stack a is further processed to provide source and drain regions of the HEMT device 100. Specifically, as shown in fig. 9, a source recess 910 and a drain recess 920 are formed in the upper surface of the HEMT stack a.

Recesses

910 and 920 are formed to expose the III-N channel layer 120, but not to extend to Sc providing a buffer layer for the HEMT device 100_xAl_1-xN piezoelectric layer 110. According to fig. 10, the iii-N source and drain HEMT material can be regrown or otherwise deposited in the source and drain

recesses

910 and 920 to form the source region 175 and the drain region 180. In some embodiments, the source and drain regions are formed on doped GaN.

In some embodiments, the upper surface may be flattened. In other embodiments, the source and drain regions overhang the surface of the HEMT stack a. According to fig. 11, a gate recess 1110 is formed in the surface of HEMT-stack a, between the source and drain regions, conducting to a depth that exposes barrier layer 125 but does not extend into III-N channel layer 120. According to fig. 12, a conductive gate material is deposited in gate recess 1110 to form gate 185. In some embodiments, the gate electrode is formed on the surface of the HEMT-stack a and is not recessed below the surface of the HEMT-stack a. In some embodiments, the portion of HEMT stack a on the region of growth substrate 1610 allocated to resonator device 105 may be removed to expose Sc_xA1_1-xThe upper surface of the N piezoelectric layer 110.

According to fig. 13, patterned metallization is deposited on the source and drain

regions

175 and 180 to form metal leads 195, respectively, extending away from the sides of the HEMT stack a to Sc_xAl_1-xThe surface of the N piezoelectric layer 110. Patterned metallization is also in Sc_xAl_1-x A bottom electrode 135 for the resonator device 105 is formed on the surface of the N piezoelectric layer 110. A first passivation layer 1810 may be formed on the bottom electrode 135 and the piezoelectric layer 110. In an example, the first passivation layer 1810 may include silicon nitride (SiN), silicon oxide (SiOx), or other similar materials. In a particular example, the first passivation layer 1810 may have a thickness ranging from about 50nm to about 100 nm.

As shown in fig. 14, a sacrificial layer 1405 is formed on the bottom electrode 135, and a sacrificial layer 1410 is formed over the surface of the HEMT device 100.

Sacrificial layers

1405 and 1410 may include polysilicon (poly-Si), amorphous silicon (a-Si), or other similar materials. In a specific example, these

sacrificial layers

1405 and 1410 may be subjected to a dry etch with a slope and deposited at a thickness of about 1 um. Further, phosphorus doped SiO₂(PSG) can be used as a sacrificial layer with different combinations of support layers (e.g., siNx).

A support layer 1420 may be formed over the resonator device 105 and the HEMT device 100 and over the

sacrificial layers

1405 and 1410. In an example, the support layer 1420 may include silicon dioxide (SiO)₂) Silicon nitride (SiN), or other similar materials. In a specific example, the support layer 1420 may be deposited to a thickness of about 2-3 um. In the case of a PSG sacrificial layer, other support layers (e.g., siNx) may be used. The upper surface of the support layer 1420 may then be polished. The polishing support layer 1420 forms a polished support layer. In an example, the polishing process may include a chemical mechanical planarization process or the like.

According to fig. 15, the polishing surface 1421 of the support layer is coupled to the carrier substrate 115 via a bonding layer. In an example, the carrier substrate 115 may include overlay Si, al₂O₃Bonding support layer 2220 (SiO) of carrier substrate 115 of silicon dioxide, silicon carbide (SiC) or other similar material₂Or similar material). In a particular embodiment, the bond support layer 2220 of the carrier substrate 115 is physically coupled to the polished surface 1421. Furthermore, the physical coupling process may include a room temperature bonding process after a 300 degree celsius annealing process.

As shown in FIG. 16, growth substrate 1610 is removed to expose Sc_xAl_1-xThe lower surface of the N piezoelectric layer 110, which is opposite to the surface on which the HEMT device 100 and the resonator device 105 are formed, is shown in fig. 3A to 14. In an example, the removal process may include a grinding process, a maskless etching process, a film transfer process, an ion implantation transfer process, a laser crack transfer process, and the like, and combinations thereof. It will be understood that further processing of the HEMT device 100 and resonator device 105 is shown, with the carrier substrate 115 invertedAnd (7) turning.

According to fig. 17A-17D, the bottom electrode 135 may comprise molybdenum (Mo), ruthenium (Ru), tungsten (W), or other similar materials. In a specific example, bottom electrode 135 can be subjected to dry etching to have a sloped electrode, thereby covering Sc of bottom electrode 135_xAl_1-xContact vias 2410 are opened within the N piezoelectric layer 110 and at Sc_xAl_1-xThe N piezoelectric layer 110 and one or more release holes 2420 in the first passivation layer 1810 covering the sacrificial layer 1405. The via formation process may include various types of etching processes. As further shown in FIG. 17, etching may also be used in Sc_xAl_1-xVias 2415 are formed in the N-piezoelectric layer 110 to expose metallization coupled to the source and drain regions of the HEMT device 100. For example, the slope may be about 60 degrees.

18A-18D, a top electrode 140 may be formed overlying the ScxA11-xN piezoelectric layer 110. In an example, the forming of the top electrode 140 includes: depositing a metal such as molybdenum (Mo), ruthenium (Ru), tungsten (W), or other similar materials; and then the top electrode 140 is etched to form an electrode cavity 2511 and a portion 2511 is removed from the top electrode 140 to form a top metal 2520 in the via 2410 to contact the bottom electrode 135. As further shown in fig. 18A-18D, metal can also be deposited in the vias 2415 on the HEMT device 105 to provide the electrodes 1811.

According to fig. 19A-19D, a first contact metal 2610 can be shaped to cover a portion of the top electrode 140 and Sc_xAl_1-xA portion of the N piezoelectric layer 110, and a second contact metal 2611 is formed overlying a portion of the top metal 2520 and Sc_xAl_1-xA portion of the N piezoelectric layer 110. In an example, the first contact metal and the second contact metal may include gold (Au), aluminum (Al), copper (Cu), nickel (Ni), aluminum bronze (AlCu), or related alloys of these or other similar materials. As further shown in fig. 19A-19D, metal can also be deposited on the electrode 1811 on the HEMT device 105 to form the contact 1905. In some embodiments according to the invention, alN heat sink 1910 may also form Sc between contacts 1905_xAl_1-xOn the N piezoelectric layer 110。

From FIGS. 20A-20D, a cap top electrode 140, a top metal 2520, and Sc may be formed_xAl_1-xA second passivation layer 2710 of the N piezoelectric layer 110. In an example, the second passivation layer 2710 may include silicon nitride (SiN), silicon oxide (SiOx), or other similar materials. In a specific example, the second passivation layer 2710 may have a thickness ranging from about 50nm to about 100 nm.

According to fig. 21A-21D, the sacrificial layer 1405 is removed to form the resonator cavity 145, and the sacrificial layer 1410 is removed to form the HEMT cavity 150. In an example, the removal process may include a polysilicon etch or an a-Si etch, or the like.

According to fig. 22A-22D, the top electrode 140 and the top metal 2520 may be processed to form a processed top electrode 2910 and a processed top metal 2920. This step may be after the top electrode 140 and top metal 2520 are formed. In an example, processing of the two components includes depositing molybdenum (Mo), ruthenium (Ru), tungsten (W), or other similar materials; and then this material is etched (e.g., dry etched, etc.) to form the processed top electrode 2910 with the top electrode cavity 2912 and the processed top metal 2920. The treated top metal 2920 is kept separated from the treated top electrode 2910 by the removal of the portion 2911. In a particular example, the treated top electrode 2910 is characterized by the addition of an energy-limiting structure configured on the treated second electrode 2910 to increase Q.

23A-23D, the bottom electrode 135 can be processed to form a processed bottom electrode 3010. This step may be after the formation of bottom electrode 135. In an example, processing of the two components includes depositing molybdenum (Mo), ruthenium (Ru), tungsten (W), or other similar materials; and then this material is etched (e.g., dry etched, etc.) to form a processed bottom electrode 3010 having electrode cavities, similar to the processed top electrode. The resonator cavity 2811 shows a change in cavity shape due to the processed bottom electrode 3010. In a specific example, the processed bottom electrode 3010 is characterized by the addition of an energy-limiting structure configured on the processed second electrode 3010 to increase Q.

As shown in fig. 24A-24D, the bottom electrode 135 can be processed to form a processed bottom electrode 2310, and the top electrode 140/top metal 2520 can be processed to form a top electrode 2910/processed top metal 2920. These steps may be after each respective electrode is formed, as described with respect to fig. 22A-22D and 23A-23D. One of ordinary skill in the art would recognize other variations, modifications, and alternatives.

FIGS. 25A-36D are cross-sectional views illustrating the use of a transfer structure (carrier substrate) instead of a sacrificial layer to form a resonator cavity and a HEMT parasitic capacitance cavity to form a cavity including a common Sc in some embodiments according to the invention_xA1_1-xMonolithic RF BAW piezoelectric resonators of N layers and transfer process of HEMT devices. In the series of figures described below, the "a" diagram shows a diagram illustrating top cross-sectional views of a BAW piezoelectric resonator and HEMT device according to various embodiments of the present invention. The "B" diagram shows a diagram illustrating a longitudinal cross-sectional view of the same device in the "a" diagram. Similarly, figure "C" shows a diagram illustrating a lateral cross-sectional view of the same device in figure "a". Similarly, the "D" diagram shows a simplified diagram of a top cross-sectional view of the HEMT device 100 showing a lateral cross-sectional view of the same device in the "a" diagram. In some cases, some features may be omitted to highlight other features and relationships between such features. Those of ordinary skill in the art will recognize variations, modifications, and alternatives to the examples shown in the series of figures.

It will be understood that the monolithic RF BAW piezoelectric resonator and HEMT device shown in fig. 33-36 can be provided using the processes described in fig. 3-13 to provide a structure as shown in fig. 25-36 that is further processed using a transfer process, but without the need for a sacrificial layer on the resonator device 105 or the HEMT device 100, in accordance with embodiments of the present invention.

As shown in FIGS. 25A-25D, at the bottom electrode 135 and the common Sc_xAl_1-x A support layer 1420 is formed on the N layer 110 and on the HEMT device 100. In an example, the support layer 1420 may include silicon dioxide (SiO 2), silicon nitride (SiN), or other similar materials. In the specific example of the above-described embodiment,the support layer 1420 may be deposited to a thickness of about 2-3 um. As described above, in the case of the PSG sacrificial layer, other support layers (e.g., siNx) may be used.

As shown in fig. 26A-26D, the support layer 1420 is processed to form a support layer 3511 including a recessed portion 3610 on the resonator device 105. In an example, the processing may include partial etching of the support layer 1420 to create a planar bonding surface. In a particular example, the process may include a cavity region. In other embodiments, this step may be replaced with a polishing process, such as a chemical mechanical planarization process or the like.

As shown in fig. 27A-27D, a recess for the air cavity 3710 is formed within a portion of the support layer 3511 (to form the support layer 3512). In an example, the recess formation may include an etching process stopped at the first passivation layer 3410. It will be understood that the first passivation layer 3410 may also be formed on the HEMT device 100 so that the etching process may stop at the first passivation layer 3410 on the HEMT device 100 so that the parasitic capacitance cavity 2715 may be formed on the HEMT device 100.

As shown in fig. 28A-28D, the Sc can be shared by the first passivation layer 3410_xAl_1-xOne or more cavity vents 3810 are formed in a portion of the N layer 110. In an example, the cavity vents 3810 may be connected to the air cavity 3710.

As shown in fig. 29A-29D, the growth substrate 1610 and the structures formed therein are shown upside down to demonstrate the bonding of the support layer 1420 overlaying the carrier substrate 115. In an example, the carrier substrate 115 may include a bond support layer 3920 (SiO) overlying the substrate₂Or similar material). It will be understood that the carrier substrate 115 may be Si, al₂O₃Silicon dioxide (SiO)₂) Silicon carbide (SiC), or other similar materials. In a particular embodiment, the bond support layer 3920 of the carrier substrate 115 is physically coupled to the polished support layer. Further, the physical coupling process may include a room temperature bonding process after the 300 degree celsius annealing process.

30A-30D, the growth substrate 1610 is removed, resulting in a common Sc_xAl_1-x The N layer 110 is transferred to a carrier substrate 115 anda resonator cavity 3710 and a parasitic capacitance cavity 3715 are formed. In an example, the removal of the growth substrate 1610 may be performed using a grinding process, a maskless etching process, a film transfer process, an ion implantation transfer process, a laser crack transfer process, and the like, and combinations thereof.

31A-31D, electrode contact vias 4110 are common Sc covering bottom electrode 135_xAl_1-xWithin N layer 110. Vias 3110 are also formed in common Sc_xA1_1-x The N layer 110 to expose metallization layers of the HEMT device 100 that are coupled to the source and drain regions and the gate of the HEMT device 100. The via formation process may include various types of etching processes.

As shown in FIGS. 32A-32D, the top electrode 140 is shaped to cover the common Sc_xAl_1-xN layers 110. In an example, the formation of the top electrode 140 may be formed by depositing molybdenum (Mo), ruthenium (Ru), tungsten (W), or other similar material, and then etching the top electrode 140 to form the electrode cavity 4211 and removing portions 4211 from the top electrode 140 to form the top metal 4220. In addition, the top metal 4220 is physically coupled to the bottom electrode 135 through an electrode contact via 4110. As further shown in fig. 32A-32D, metal can also be deposited in the via 3110 to contact metallization on the HEMT device 105 to the electrode 3111.

As shown in FIGS. 33A-33D, a first contact metal 4310 is shaped to cover a portion of the top electrode 140 and Sc_xAl_1-xA portion of the N piezoelectric layer 110, and a second contact metal 4311 is formed, the second contact metal covering a portion of the top metal 4220 and Sc_xAl_1-xA portion of the N piezoelectric layer 110. A first contact metal and a second contact metal can also be deposited in the vias 3110 on the HEMT device 100 to provide the illustrated contacts 1810, 1815, and 1820a. In an example, the first contact metal and the second contact metal may include gold (Au), aluminum (Al), copper (Cu), nickel (Ni), aluminum bronze (AlCu), or other similar materials. The figure also shows the method steps of forming a second passivation layer 4320 covering the second electrode 4210, the top metal 4220 and Sc_xAl_1-xOn the N piezoelectric layer 110. In an example, the second passivation layer 4320 may include silicon nitride (SiN), silicon oxide (SiOx), or other similar materials. In a specific example, the second passivation layer 4320 may have a thickness in a range of about 50nm to about 100 nm.

As shown in fig. 34A-34D, the top electrode 140 and top metal 4220 may be processed to form a processed top electrode 4410 and a processed top metal 4420. This step may be after the top electrode 140 and top metal 4220 are formed. This step may also include forming an AlN heat sink 3421 on the HEMT device 100. In an example, the processing of the two components includes depositing molybdenum (Mo), ruthenium (Ru), tungsten (W), or other similar materials; and then etching (e.g., dry etching, etc.) this material to form a processed top electrode 4410 with an electrode cavity 4412 and a processed top metal 4420. The processed top metal 4420 remains separated from the processed top electrode 141 by removing portion 4411. In a specific example, the processed second electrode 4410 is characterized by the addition of an energy-limiting structure configured on the processed top electrode 141 to increase Q.

As shown in fig. 35A-35D, the bottom electrode 135 may be formed by processing the bottom electrode 135. In an example, the processing of the two components includes depositing molybdenum (Mo), ruthenium (Ru), tungsten (W), or other similar materials; and then this material is etched (e.g., dry etched, etc.) to form a processed bottom electrode 4510 with electrode cavities 3711, similar to the processed top electrode 4410. The air cavity 4511 illustrates the change in cavity shape due to the processed bottom electrode 4510. In a specific example, the processed bottom electrode 4510 is characterized by the addition of an energy-limiting structure configured on the processed bottom electrode 4510 to increase Q.

As shown in fig. 36A-36D, the bottom electrode 135 is processed to form a processed bottom electrode 4510 and the top electrode 4210/top metal 4220 is processed to form a processed top electrode 4410/processed top metal 4420. These steps may be after the formation of each respective electrode, as depicted in fig. 34A-34D and fig. 35A-35C. One of ordinary skill in the art would recognize other variations, modifications, and alternatives.

FIGS. 37A-37D all show the use of transfer structures (carrier substrates) to fabricate devices including common Sc_xAl_1-xA monolithic RF BAW piezoelectric resonator 105 of N layer 110 and a method of HEMT device 100, the monolithic RF BAW piezoelectric resonator 105 having a multilayer mirror structure. In the series of figures described below, the "a" diagram shows a diagram illustrating a top cross-sectional view of the resonator device 105 and HEMT device 100 according to various embodiments of the present invention. The "B" diagram shows a diagram illustrating a longitudinal cross-sectional view of the same device in the "a" diagram. Similarly, figure "C" shows a diagram illustrating a lateral cross-sectional view of the same device in figure "a". Similarly, the "D" diagram shows a simplified diagram of a top cross-sectional view of the HEMT device 100 showing a lateral cross-sectional view of the same device in the "a" diagram. In some cases, some features are omitted to highlight other features and relationships between such features. Those of ordinary skill in the art will recognize variations, modifications, and alternatives to the examples shown in the series of figures.

It will be understood that the monolithic RF BAW piezoelectric resonator and HEMT device shown in fig. 37-47 can be provided using the process described in fig. 3-13 to provide a structure that is further processed using a transfer process as shown in fig. 37-47, but without the need for a sacrificial layer on the resonator device 105, and instead a cavity can be formed on the HEMT device 100 using a sacrificial layer as shown in fig. 14 or by forming a recess in a support layer before bonding the structure to the carrier substrate 115, for example, in fig. 27-29, in accordance with embodiments of the present invention.

As shown in FIGS. 37A to 37D, sc in common_xA1_1-xA multilayer mirror or reflector structure is formed on the bottom electrode 4810 on the N piezoelectric layer 110. In an example, the multilayer mirror includes at least one pair of layers having a low impedance layer 4910 and a high impedance layer 4920. In fig. 37A-37D, two pairs of low impedance/high impedance layers (low: 4910 and 4911; high: 4920 and 4921) are shown. In an example, the mirror/reflector region may be larger than the resonator region and may surround the resonator region. In a specific embodiment, each layer thickness is about 1/4 of the wavelength of the acoustic wave at the target frequency. The layers may be deposited sequentially and thereafterEtching is performed or each layer may be deposited and etched separately. In another example, the bottom electrode 4810 can be patterned after the mirror structure is patterned.

As shown in FIGS. 38A-38D, the support layer 5010 is formed to cover the mirror structure (

layers

4910, 4911, 4920, and 4921), the bottom electrode 135, the common Sc_xAl_1-x An N layer 110, and a HEMT device 100. In an example, the support layer 5010 can include silicon dioxide (SiO 2), silicon nitride (SiN), or other similar materials. In a specific example, the support layer 5010 can be deposited to a thickness of about 2-3 um. As described above, other support layers (e.g., siNx) may be used.

As shown in fig. 39A-39D, recesses 5012 are formed in the support layer 5010 over the HEMT stack a, and the support layer 5010 can be polished to form a polished support layer 5011 to improve the bonding strength provided by subsequent transfer. In an example, the polishing process may include a chemical mechanical planarization process or the like.

As shown in fig. 40A to 40D, the structure formed in fig. 39A to 39D is inverted and shown with the support layer 5011 polished before transfer positioned opposite to the carrier substrate 115. In an example, the carrier substrate 115 can include a bonding support layer 5220 (SiO)₂Or the like) of silicon (Si), sapphire (Al 2O 3), silicon dioxide (SiO) and the like, in combination with a support layer 5220₂) A substrate carrier substrate of silicon carbide (SiC), or other similar material.

As shown in fig. 41A-41D, the carrier substrate 115 is brought into contact with and bonded to the polished support layer 5011 so that the recesses 5012 and the carrier substrate 115 form a HEMT parasitic capacitance cavity 5103. Further, the physical coupling process may include a room temperature bonding process after the 300 degree celsius annealing process.

As shown in FIGS. 42A-42D, the growth substrate 1610 is removed to expose the common Sc_xAl_1-xThe lower surface of the N piezoelectric layer 110. Removal of the growth substrate 1610 may be performed using a grinding process, a maskless etching process, a film transfer process, an ion implantation transfer process, a laser crack transfer process, and the like, and combinations thereof.

As in FIGS. 42A-42DFurther shown, through the shared Sc_xAl_1-xThe N piezoelectric layer 110 forms electrode contact vias 5410 to form at Sc_xAl_1-xThe bottom electrode 135 is exposed on the opposite side of the N piezoelectric layer 110. As shown, additional vias 3110 may be formed through the common ScxA11-xN piezoelectric layer 110 to expose the metallization of the HEMT device 100. The via formation process may include various types of etching processes.

As shown in FIGS. 43A-43D, metal can be deposited to form a cap over Sc_xAl_1-xThe top electrode 140 on the N piezoelectric layer 110 and the top metal 5520 is formed in the via 3110. In an example, metal deposition in the via may be performed by depositing molybdenum (Mo), ruthenium (Ru), tungsten (W), or other similar materials. The top electrode 140 may be etched to form the electrode cavity 5511 by removing a portion of the top electrode 140 to form the top metal 5520. Further, the top metal 5520 is physically coupled to the bottom electrode 135 through an electrode contact via 5410.

44A-44D, a first contact metal 5610 is shaped to cover a portion of the top electrode 140 and the common Sc_xAl_1-xA portion of the N piezoelectric layer 110, and a second contact metal 5611 may cover a portion of the top metal 5520 and the common Sc_xAl_1-xA portion of the N piezoelectric layer 110. Further, a metal contact 1905 may be formed on the electrode 3112. Further, a heat sink portion 1910 can be formed on the surface of the HEMT device 100 between the contacts 1810 and 1815. In some embodiments, the heat sink portion 41401 may be polycrystalline AlN.

In an example, the first contact metal and the second contact metal may include gold (Au), aluminum (Al), copper (Cu), nickel (Ni), aluminum bronze (AlCu), or other similar materials. The figure also shows forming a top electrode 5510, top metal 5520, and common Sc_xAl_1-xMethod steps of the second passivation layer 5620 of the N piezoelectric layer 110. In an example, the second passivation layer 5620 may include silicon nitride (SiN), silicon oxide (SiOx), or other similar materials. In a particular example, the second passivation layer 5620 may have a thickness ranging from about 50nm to about 100 nm.

As shown in fig. 45A-45D, the top electrode 140 and top metal 5520 may be processed to form a processed top electrode 5710 and a processed top metal 5720. This step may be after the top electrode 140 and top metal 5520 are formed. In an example, processing of the two components includes depositing molybdenum (Mo), ruthenium (Ru), tungsten (W), or other similar materials; and then this material is etched (e.g., dry etched, etc.) to form processed top electrode 5710 and processed top metal 5720 with electrode cavity 5712. The treated top metal 5720 remains separated from the treated top electrode 5710 by the removal of portion 5711. In a specific example, this process gives the top electrode and top metal a greater thickness while creating an electrode cavity 5712. In a specific example, the processed top electrode 5710 is characterized by the addition of an energy-limiting structure configured on the processed top electrode 5710 to increase Q.

As shown in fig. 46A-46D, the bottom electrode 4810 can be processed to form a processed bottom electrode 135. This step may be after the bottom electrode 4810 is formed. In an example, processing of the two components includes depositing molybdenum (Mo), ruthenium (Ru), tungsten (W), or other similar materials; and then this material is etched (e.g., dry etched, etc.) to form a processed bottom electrode 5810 with an electrode cavity, similar to the processed top electrode 5710. In a specific example, the processed bottom electrode 5810 is characterized by the addition of an energy-limiting structure configured on the processed top electrode 5810 to increase Q.

As shown in fig. 47A-47D, the bottom electrode 135 can be processed to form a processed bottom electrode 5810, and the top electrode 140/top metal 5520 can be processed to form a processed top electrode 5710/processed top metal 5720. These steps may be after each respective electrode is formed, as described with respect to fig. 45A-45D and 46A-46C. One of ordinary skill in the art would recognize other variations, modifications, and alternatives.

In each of the foregoing examples relating to transfer processes, the energy-confining structure may be formed on the bottom electrode, the top electrode, or both. In an example, the energy-confining structures are around resonanceMass loading region of the device region. The resonator region is a first electrode, and is shared by Sc_xAl_1-xThe region where the N piezoelectric layer and the top electrode overlap. The larger mass loading in the energy-limiting structure lowers the cutoff frequency of the resonator. The cutoff frequency is a lower or upper limit of the frequency at which an acoustic wave can propagate in a direction parallel to the surface of the piezoelectric layer. Therefore, the cutoff frequency is a resonance frequency in which a wave travels in the thickness direction, and is thus determined by the overall stacked structure of the resonator in the vertical direction.

As used herein, unless otherwise defined, the term "substrate" includes any ternary compound, or functional region, combination, etc., overlying a growth structure, such as aluminum, gallium, or an epitaxial region containing aluminum, gallium, and nitrogen.

In the piezoelectric layer (e.g., scAlN), an acoustic wave having a frequency lower than the cutoff frequency can propagate in the parallel direction along the film surface, i.e., the acoustic wave exhibits a high-band-cutoff dispersion characteristic. In this case, the mass-loaded region around the resonator provides a barrier that prevents acoustic waves from propagating outside the resonator. By doing so, the features increase the quality factor of the resonator and improve the performance of the resonator and thus the filter.

FIG. 48 is a cross-sectional view of a monolithic Surface Acoustic Wave (SAW) resonator device 4800 integrated with a HEMT device 4805 including a shared Sc in some embodiments according to the invention_xAl_1-xN piezoelectric layer 110. Specifically, sc in common_xAl_1-xThe N piezoelectric layer 110 provides a piezoelectric layer for the SAW resonator 4800 and a buffer layer for the HEMT device 4805. It should be understood that the materials described herein in relation to BAW resonators may be applicable to the SAW configuration of fig. 48.

Fig. 49 is a schematic diagram of a transmit module 4900 in some embodiments according to the invention, the transmit module 4900 including a BAW filter 4910 assembled in an integrated manner, an amplifier 4915 implemented using at least one HEMT device, and a switch 4805 implemented using at least one HEMT device, as described herein.

Fig. 50 is a schematic diagram of a partial full front end module (CFE) high band device 5000 in some embodiments according to the invention, the partial full front end module (CFE) high band device 5000 including a BAW filter 5010, an amplifier 5015 implemented using at least one HEMT device, and a switch 5005 implemented using at least one HEMT device assembled in an integrated manner, as described herein.

Fig. 51 is a schematic illustration of a switched-duplex bank 5100 in some embodiments according to the invention, the switched-duplex bank 5100 including at least one BAW filter 5110 and at least one switch 5105 (implemented using at least one HEMT device, such as a bypass switch or a multi-throw switch) assembled in an integrated manner.

Fig. 52 is a schematic diagram of an antenna switch module 5200 in some embodiments according to the invention, the antenna switch module 5200 including at least one BAW filter 5210 and at least one switch 5205 (implemented using at least one HEMT device, such as a bypass switch or a multi-throw switch) assembled in an integrated manner.

Fig. 53 is a schematic diagram of a diversity reception FEM 5300 in some embodiments according to the invention, the diversity reception FEM 5300 including at least one low noise amplifier 5315 implemented using at least one HEMT device, at least one BAW filter 5310, and at least one switch 5305 implemented using at least one HEMT device assembled in an integrated manner.

Fig. 54 is a schematic diagram of a Power Amplifier (PA) duplexer 5400 in some embodiments according to the invention, the Power Amplifier (PA) duplexer 5400 including at least one power amplifier 5415 and at least one BAW filter 5410 implemented using at least one HEMT device assembled in an integrated manner.

In this specification, similar components have been given the same reference numerals regardless of whether they are shown in different examples. To illustrate examples in a clear and concise manner, the drawings may not necessarily be to scale and some features may be shown in somewhat schematic form. Features that are described and/or illustrated with respect to one example may be used in the same way or in a similar way in one or more other examples and/or in combination with or instead of the features of the other examples.

As used in the specification and the claims, the terms "about" and "substantially" are used to represent the inherent degree of uncertainty that may be attributed to any quantitative comparison, value, measurement, or other representation, for the purposes of describing and defining the present disclosure. The terms "about" and "substantially" are also utilized herein to represent the degree by which a quantitative representation may vary from a stated reference without resulting in a change in the basic function of the subject matter at issue. Each of the forms including (comprises), including (include), and/or multiple forms is open-ended and includes the listed parts and may include additional parts not listed. And/or is open ended and includes one or more of the listed parts and combinations of the listed parts.

While this document includes many specifics, these should not be construed as limitations on the scope of the invention as claimed or on the scope of what is claimed, but rather as descriptions of features of particular embodiments. Some features that are described in this document in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination. Furthermore, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination. Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results.

Only a few examples and implementations are disclosed. Variations, modifications, and optimizations may be made to the described examples and implementations, as well as other implementations, based on the disclosure. Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. Moreover, the separation of various system components in the embodiments described in this patent document should not be understood as requiring such separation in all embodiments.

While the above is a complete description of specific embodiments, various modifications, alternative constructions, and equivalents may be used. As an example, a packaged device may include any combination of the elements described above and outside of this specification. Accordingly, the above description and illustrations should not be taken as limiting the scope of the invention, which is defined by the appended claims.

Claims

1. An RF integrated circuit device, comprising:

a substrate;

a High Electron Mobility Transistor (HEMT) device on the substrate, the HEMT device including a ScAlN layer configured to provide a buffer layer of the HEMT device to define formation of a 2DEG channel region of the HEMT device; and

an RF piezoelectric resonator device on the substrate, the RF piezoelectric resonator device comprising the ScAlN layer sandwiched between a top electrode and a bottom electrode of the RF piezoelectric resonator device to provide a piezoelectric resonator for the RF piezoelectric resonator device.

2. The RF integrated circuit device of claim 1, further comprising:

an RF piezoelectric resonator cavity between the bottom electrode and the substrate.

3. The RF integrated circuit device of claim 1, wherein the HEMT device further comprises:

a GaN channel layer on the ScAlN layer;

a barrier layer on the GaN channel layer to provide the 2DEG channel region in the GaN channel layer;

a GaN drain region recessed into the GaN channel layer at a first end of the 2DEG channel region;

a GaN source region recessed into the GaN channel layer at a second end of the 2DEG channel region opposite the first end of the 2DEG channel region; and

a gate electrode between the GaN drain region and the GaN source region opposite the blocking layer, and configured to modulate the 2DEG channel region in the GaN channel layer.

4. The RF integrated circuit device of claim 1, wherein the ScAlN layer is stress balanced with respect to a GaN channel layer of the HEMT device on the ScAlN layer.

5. The RF integrated circuit device of claim 4 wherein the ScAlN layer comprises Sc_0.18Al_0.82N。

6. The RF integrated circuit device of claim 4 wherein the HEMT device further comprises:

a GaN channel layer on the ScAlN layer; and

an ScAlN barrier layer on the GaN channel layer to provide the 2DEG channel region in the GaN channel layer.

7. The RF integrated circuit device of claim 4 wherein the HEMT device further comprises:

a GaN channel layer on the ScAlN layer; and

an AlGaN barrier layer on the GaN channel layer to provide the 2DEG channel region in the GaN channel layer.

8. The RF integrated circuit device of claim 4 wherein the HEMT device further comprises:

a GaN channel layer on the ScAlN layer;

an AlN sub-barrier layer on the GaN channel layer; and

a barrier layer comprising AlN on the AlN sub-barrier layer to provide the 2DEG channel region in the GaN channel layer.

9. The RF integrated circuit device of claim 1, wherein the ScAlN layer comprises single crystal ScAlN material.

10. The RF integrated circuit device of claim 9 wherein the single crystal ScAlN material has a crystal structure characterized by an XRD rocking curve FWHM value in a range between about less than 1.0 degrees and about 0.001 degrees as measured by about 2 theta (2 theta) scan angles.

11. The RF integrated circuit device of claim 1, wherein the substrate comprises a silicon <100> substrate.

12. The RF integrated circuit device of claim 1, wherein the ScAlN layer includes Sc having a thickness of about 2 microns to about 0.01 microns_0.18Al_0.82An N layer, the HEMT device further comprising:

in the above-mentioned Sc_0.18Al_0.82A GaN channel layer on the N layer, the GaN channel layer having a thickness of about 0.1 microns to about 1.0 microns; and

an ScAlN barrier layer on the GaN channel layer, the ScAlN barrier layer having a thickness of about 200nm to about 0.01 microns.

13. The RF integrated circuit device of claim 3, further comprising:

a GaN or SiN passivation layer between the gate electrode and the barrier layer.

14. The RF integrated circuit device of claim 3, further comprising:

a passivation layer grown directly on the barrier layer.

15. The RF integrated circuit device of claim 3 wherein the GaN channel layer comprises an epitaxial GaN channel layer on the ScAlN layer.

16. The RF integrated circuit device of claim 3 wherein the barrier layer further comprises Sc, ga or In.

17. The RF integrated circuit device of claim 16, wherein the epitaxial GaN channel layer further includes In and Al.

18. The RF integrated circuit device of claim 3 wherein the GaN channel layer includes In_xGa_(1-x)N, wherein x is in a range between greater than about 0.08 and about 0.12.

19. The RF integrated circuit device of claim 3 wherein a spacing between the GaN drain region and the GaN source region is less than 5 microns, and a breakdown electric field of the HEMT device is at least about 1.0MV/cm to about 6.0MV/cm.

20. The RF integrated circuit device of claim 3 wherein the upper surface of the barrier layer is located about 2nm or less from the upper surface of the HEMT device.

21. The RF integrated circuit device of claim 3, further comprising:

and the amorphous AlN passivation layer is positioned between the gate electrode and the barrier layer.

22. The RF integrated circuit device of claim 1, wherein the HEMT device further comprises:

a III-N channel layer lattice-matched to and on the ScAlN layer;

a group III-N barrier layer on the group III-N channel layer, the group III-N barrier layer having a stress in a range between about-400 MPa to about +400MPa and providing a channel region in the group III-N channel layer;

a group III-N drain region recessed into the group III-N channel layer at a first end of the channel region;

a III-N group source region recessed into the III-N channel layer at a second end of the channel region opposite the first end of the channel region; and

a gate electrode located between the group III-N drain region and the group III-N source region.

23. The RF integrated circuit device of claim 23 wherein the III-N barrier layer has a band gap of about 6eV at room temperature.

24. The RF integrated circuit device of claim 23 wherein a spacing between the group III-N drain region and the group III-N source region is less than 3 microns and the HEMT device has a breakdown electric field of at least about 1.0MV/cm to about 6.0MV/cm.

25. The RF integrated circuit device of claim 23, wherein an upper surface of the group III-N barrier layer is located about 2nm or less from an upper surface of the HEMT device extending between the gate electrode and the group III-N drain region.

26. The RF integrated circuit device of claim 23 wherein the III-N barrier layer comprises ScAlN.

27. The RF integrated circuit device of claim 1, wherein the HEMT device further comprises:

a III-N channel layer on the ScAlN layer;

a III-N barrier layer on the III-N channel layer to provide a channel region in the III-N channel layer;

a III-N cap layer on the III-N barrier layer; and

wherein at least one of the III-N channel layer, III-N barrier layer, and III-N cap layer is configured to provide strain balancing to the ScAlN.

28. An RF integrated circuit device, comprising:

a substrate;

a piezoelectric resonator cavity on the substrate;

a ScAlN piezoelectric resonator on the substrate extending across the piezoelectric resonator cavity;

a bottom electrode on the ScAlN piezoelectric resonator in the piezoelectric resonator cavity;

a GaN channel layer grown on the ScAlN piezoelectric resonator above the piezoelectric resonator cavity;

a barrier layer on the GaN channel layer for providing a 2DEG channel region in the GaN channel layer defined by the ScAlN piezoelectric resonator;

a GaN source region recessed into the GaN channel layer at a second end of the 2DEG channel region opposite the first end of the channel region; and

a gate electrode between the GaN drain region and the GaN source region opposite the blocking layer, and configured to modulate the 2DEG channel region in the GaN channel layer;

29. an RF integrated circuit device, comprising:

a silicon substrate; and

a ScAlN layer providing a buffer layer for an epitaxially grown material stack included in an RF High Electron Mobility Transistor (HEMT) device on the silicon substrate and providing a piezoelectric resonator structure included in an RF filter on the silicon substrate.

30. The RF integrated circuit device of claim 30 wherein the ScAlN layer is configured to define the formation of a 2DEG channel region in a GaN channel layer in the epitaxially grown material stack of the HEMT device.

31. The RF integrated circuit device of claim 30 wherein the HEMT device comprises a first HEMT device providing an amplified output signal in response to an input signal, the amplified output signal coupled to an input of the RF filter, the RF filter configured to provide a filtered output signal, the device further comprising:

a switch coupled to the filtered output signal, the switch including a second HEMT device on the substrate including the ScAlN layer, the switch configured to direct the filtered output signal or the input signal to a switch output.

32. The RF integrated circuit device of claim 30 wherein the HEMT device comprises a first HEMT device providing a switch configured to direct a signal received from an antenna to an input of the RF filter to provide a filtered output, the device further comprising:

a second HEMT device providing an amplifier configured to output an amplified signal.

33. The RF integrated circuit device of claim 30 wherein the HEMT device comprises a power amplifier configured to provide an amplified signal to the RF filter.

34. The RF integrated circuit device of claim 30 wherein the ScAlN layer includes Sc_xAl_1-xN layer, wherein x is in the range of about 0.18 to about 0.4.

35. The RF integrated circuit device of claim 35 wherein the Sc_xAl_1-xThe N-layer has a crystal structure characterized by an XRD rocking curve FWHM value in a range between about less than 1.0 degrees to about 0.001 degrees as measured by about a 2 theta (2 theta) scan angle.

36. The RF integrated circuit device of claim 30, wherein the piezoelectric resonator structure comprises a Bulk Acoustic Wave (BAW) resonator or a surface acoustic wave resonator.

37. The RF integrated circuit device of claim 30, wherein the silicon substrate comprises a carrier silicon <100> substrate bonded to the ScAlN layer during fabrication.

38. The RF integrated circuit device of claim 30, wherein the ScAlN layer includes an epitaxially grown ScAlN layer.

39. The RF integrated circuit device of claim 39 wherein the stack of epitaxially grown material is formed without vacuum break.

40. A method of forming an RF integrated circuit device, the method comprising:

formation of Sc on a substrate_xAl_1-xN layer of said Sc_xAl_1-xThe N layer comprises a piezoelectric resonator area and an HEMT device area;

in the said Sc_xAl_1-xForming a High Electron Mobility Transistor (HEMT) channel layer on the N layerA channel layer and the Sc_xAl_1-xThe N layers of lattice match to provide a 2DEG channel region;

forming a HEMT barrier layer on the HEMT channel layer, the HEMT barrier layer and the Sc_xAl_1-xMatching N layers of crystal lattices; and

piezoelectric resonator electrodes are formed on the piezoelectric resonator area.

41. The method of claim 41, wherein the Sc is formed_xAl_1-xThe N layer includes forming the Sc_xAl_1-xN layers, wherein x =0.18; and

wherein, in the Sc_xAl_1-xForming the HEMT channel layer on the N layer includes forming a GaN channel layer.

42. The method of claim 41, wherein the Sc is formed_xAl_1-xThe N layer includes forming the Sc_xAl_1-xN layers, wherein x =0.3; and

wherein in the Sc_xAl_1-xForming the HEMT channel layer on the N layer includes forming an InGaN channel layer.

43. The method of claim 41, wherein the Sc is being formed_xAl_1-xBefore N layers:

an AlN seed layer is formed directly on the substrate.

44. The method of claim 41, wherein the Sc is being formed_xAl_1-xBefore N layers:

a GaN seed layer is formed directly on the substrate.

45. The method of claim 41, wherein forming the HEMT barrier layer comprises forming Sc_xAl_1-xAn N barrier layer or an AlGaN barrier layer.

46. The method of claim 46, wherein, prior to forming the HEMT barrier layer:

and forming an AlN sub-barrier layer directly on the HEMT channel layer.

47. The method of claim 41, wherein the Sc is formed_xAl_1-xThe operation of forming the N layer to the HEMT barrier layer includes performing an epitaxial growth operation without vacuum break.

48. The method of claim 41, wherein the Sc is formed_xAl_1-xN layers comprising said Sc_xAl_1-xThe N layer is formed to a thickness in a range between about 200nm and 800 nm.

49. The method of claim 41 wherein forming the HEMT channel layer includes forming the HEMT channel layer to a thickness in a range between about 0.5 microns and about 1.0 microns.

50. The method of claim 41 wherein forming the HEMT barrier layer comprises forming the HEMT barrier layer to a thickness in a range between about 50nm to about 2 nm.

51. The method of claim 41, wherein the Sc_xAl_1-xThe N layer comprises single crystal Sc_xAl_1-xAnd (3) N material.

52. The method of claim 52, wherein the Sc is formed_xAl_1-xThe N layer further includes:

providing Sc precursor into the reaction chamber via a heated precursor line to form the single crystal Sc on the substrate_xAl_1-xAnd (3) N material.

53. The method of claim 53, wherein the single crystal Sc_xAl_1-xThe N material has a crystal structureCharacterized by an XRD rocking curve FWHM value in a range between about less than 1.0 degree to about 0.001 degree as measured by about a 2 theta (2 theta) scan angle.

54. The method of claim 53, wherein the heated precursor line is heated to a temperature in a range between about 60 degrees Celsius and about 120 degrees Celsius.

55. The method of claim 55, wherein the heated precursor line is between the source of Sc precursor and the reaction chamber.

56. The method of claim 41, wherein the substrate comprises silicon<111>Substrate, siC substrate, or Al₂O₃A substrate.

57. The method of claim 41, further comprising:

in the formation of the Sc_xAl_1-xBefore N layer, NH is added₃Is provided to a surface of the substrate at a temperature in a range between about 700 degrees celsius and about 1200 degrees celsius.

58. The method of claim 41, wherein the RF integrated circuit device comprises a surface acoustic wave resonator device.

59. The method of claim 41, wherein the RF integrated circuit device comprises a bulk acoustic wave resonator device.

60. A method of forming an RF integrated circuit device, the method comprising:

formation of single crystal Sc on a substrate_xAl_1-xN layers;

in the single crystal Sc_xAl_1-xForming a High Electron Mobility Transistor (HEMT) device on the N layer, the HEMT device including a channel layer and a barrier layer of the HEMT device(ii) a And

from said single crystal Sc_xAl_1-xN layer forming an RF piezoelectric resonator device, the single crystal Sc_xAl_1-xAn N layer is sandwiched between the top and bottom electrodes of the RF piezoelectric resonator device to provide a piezoelectric resonator for the RF piezoelectric resonator device.

61. The method of claim 61, wherein forming the single crystal Sc is performed without vacuum break_xAl_1-xAn N layer, the channel layer and the barrier layer of the HEMT device.

62. The method of claim 61, wherein the single crystal Sc is formed_xAl_1-xThe N layer includes forming the single crystal Sc_xAl_1-xN layer, wherein x is in a range between about 0.18 to about 0.4.

63. The method of claim 63, wherein the channel layer comprises Sc and the single crystal_xAl_1-xAnd N layers of GaN channel layers with matched crystal lattices.

64. The method of claim 61, wherein the channel layer strain is set to the single crystal Sc in equilibrium with respect to the channel layer stress_xAl_1-xAnd N layers.

65. The method of claim 65 wherein the stress on the channel layer ranges between about-400 MPa to about +400 MPa.

66. The method of claim 61, wherein the substrate comprises a growth substrate, the method further comprising:

epitaxially forming the single crystal Sc on a first side of the growth substrate_xAl_1-xN layers;

the single crystal Sc over a first side of the growth substrate_xAl_1-xForming a channel layer and a barrier layer of the HEMT device on the first surface of the N layer;

the single crystal Sc over a first side of the growth substrate_xAl_1-xForming the bottom electrode on the first surface of the N layer;

forming a sacrificial layer on the bottom electrode and on the barrier layer of the HEMT device;

coupling the bottom electrode of the RF piezoelectric resonator device and the HEMT device over the first side of the growth substrate to a carrier substrate; and

treating a second side of the growth substrate opposite the first side of the growth substrate to expose the single crystal Sc_xAl_1-xA second surface of the N layer, the second surface and the single crystal Sc_xAl_1-xThe first surface of the N layer is opposite.

67. The method of claim 67, further comprising:

in the single crystal Sc_xAl_1-xForming a recess in the N layer to expose the bottom electrode;

depositing a first metal on the single crystal Sc_xAl_1-xA second surface of the N layer to form a top electrode for the RF piezoelectric resonator device and deposited in the recess to contact the bottom electrode; and

single crystal Sc in the HEMT device_xAl_1-xA heat spreading layer is formed on a second surface of the N layers, the heat spreading layer being spaced apart from the top electrode.

68. The method of claim 68, further comprising:

removing the sacrificial layer from the bottom electrode and the barrier layer of the HEMT device to form a resonator cavity and a HEMT parasitic capacitance cavity, respectively.

69. The method of claim 68, further comprising:

depositing a second metal on the top electrode and on the first metal in the recess to form a top electrode contact and a bottom electrode contact, respectively.

70. The method of claim 70, further comprising:

depositing the second metal on the barrier layer to provide a source contact and a drain contact for the HEMT device.

71. The method of claim 67, wherein the single crystal Sc over the first side of the growth substrate_xAl_1-xAfter forming a channel layer and a barrier layer of the HEMT device on the first surface of the N layer:

forming a HEMT protective layer on the HEMT device; then the

The single crystal Sc over a first side of the growth substrate_xAl_1-xThe bottom electrode is formed on the first surface of the N layer.

72. The method of claim 72, wherein the single crystal Sc over the first side of the growth substrate_xAl_1-xAfter forming the bottom electrode on the first surface of the N layer:

forming a resonator protection layer on the sacrificial layer and the bottom electrode;

polishing the upper surface of the resonator protection layer and the upper surface of the HEMT protection layer; then the

Coupling an upper surface of the resonator protection layer and an upper surface of the HEMT protection layer to the carrier substrate.

73. The method of claim 73, further comprising:

depositing a first metal on the single crystal Sc_xAl_1-xN layers on the second surface to form a dielectric layer for the RF piezoelectric resonatorA top electrode of the device and deposited in the recess to contact the bottom electrode; and

74. A method of forming a monolithic RF HEMT/resonator integrated circuit device, the method comprising:

epitaxially forming a single crystal Sc on a substrate_xAl_1-xN layers;

in the single crystal Sc_xAl_1-xEpitaxially forming a HEMT III-N channel layer on the N layer, wherein the HEMT III-N channel layer is in contact with the single crystal Sc_xAl_1-xMatching N layers of crystal lattices;

epitaxially forming a HEMT III-N barrier layer on the HEMT III-N channel layer;

forming a source recess in the HEMT III-N barrier layer and in the HEMT III-N channel layer;

forming a drain recess in the HEMT III-N barrier layer and in the HEMT III-N channel layer;

forming a III-N material in the source recess and in the drain recess to provide a HEMT source region and a HEMT drain region, respectively;

forming a gate recess in the HEMT III-N barrier layer between the source recess and the drain recess; and

depositing a metal on the single crystal Sc_xAl_1-xAn N layer, on the HEMT source region, and on the HEMT drain region to form a bottom electrode for the resonator, a HEMT source contact, and a HEMT drain contact, respectively.

75. The method of claim 75, wherein epitaxially forming the single crystal Sc is performed without vacuum break_xAl_1-xAn N layer, epitaxially forming the HEMT III-N channel layer, and epitaxially forming the HEMT III-N barrier layer.

76. The method of claim 75, wherein, after epitaxially forming the HEMT III-N barrier layer:

and forming a III-N HEMT cover layer on the HEMT III-N barrier layer.

77. The method of claim 75, wherein, after epitaxially forming the HEMT III-N barrier layer:

and forming a SiN cover layer on the HEMT III-N barrier layer.

78. The method of claim 75, wherein, after epitaxially forming the HEMT III-N barrier layer:

and forming an amorphous AlN cover layer on the HEMT III-N barrier layer.

79. The method of claim 75, wherein the single crystal Sc_xAl_1-xThe N layer comprises the single crystal Sc_xAl_1-xA N layer, wherein x is in a range between about 0.18 and about 0.4, and the single crystal Sc_xAl_1-xThe N-layer has a crystal structure characterized by an XRD rocking curve FWHM value in a range between about less than 1.0 degrees to about 0.001 degrees as measured by about a 2 theta (2 theta) scan angle.

80. The method of claim 75, further comprising:

a sacrificial layer is formed on the bottom electrode, on the HEMT source contact, and on the HEMT drain contact.