DE112021000325T5 - POWER SUPPLY CIRCUIT AND SHIFT CONTROL CIRCUIT - Google Patents

Abstract

A power supply circuit is provided which is set up to generate an output voltage at the level of a desired value from an input voltage. The power supply circuit includes a variable resistor provided between wiring configured to receive the input voltage and a predetermined node, a voltage generating circuit configured to apply a voltage of a predetermined level to the predetermined node based on a current from the variable resistor, an output circuit configured to output the output voltage of the target value when the voltage of the predetermined level is applied to the predetermined node, and a matching circuit configured to do so is to increase a resistance value of the variable resistor due to a predetermined period of time elapsed from the start of generation of the output voltage.

Description

[Technical Field]

The present invention relates to a power supply circuit and a switching control circuit.

[Background knowledge]

An integrated circuit may include a power supply circuit that generates a power supply voltage Vreg for operating circuits within the integrated circuit based on an externally supplied power supply voltage Vcc.

[citation list]

[patent literature]

[PTL 1] Japanese Patent Application Publication no. 2006-159472

[Summary of the Invention]

[Technical problem]

In general, in order to shorten the period of time between when the power supply voltage Vcc is applied to the power supply circuit and when the power supply voltage Vreg reaches a set value, i.e. the start-up time of the power supply circuit, the current flowing from the power supply voltage Vcc to the power supply circuit must be increased. However, when the current flowing from the power supply voltage Vcc to the power supply circuit increases, the level of the power supply voltage Vreg is likely to be affected by a change in the power supply voltage Vcc.

The present invention aims to provide a power supply circuit in which the start-up time is short and a stable power supply voltage can be generated.

[The solution of the problem]

A first aspect of the present invention is a power supply circuit configured to generate an output voltage at a desired value from an input voltage, the power supply circuit including a variable resistor connected between wiring configured to receive the input voltage and a predetermined node is provided; a voltage generation circuit configured to apply a voltage of a predetermined level to the predetermined node based on a current from the variable resistor; and an output circuit configured to output the output voltage of the target value when the voltage of the predetermined level is applied to the predetermined node; and an adjustment circuit configured to increase a resistance value of the variable resistor in response to a predetermined period of time elapsed from the start of generation of the output voltage.

Switching control circuit configured to control switching of a first switching device on a power supply side and a second switching device on a ground side, the first and second switching devices being configured to control a load, wherein the switching control circuit includes a signal output circuit configured to do so is arranged, in response to one of its input signals, to output a set signal to turn on the first switching device and a reset signal to turn off the first switching device; a level conversion circuit configured to shift a level of each of the set signal and the reset signal; a drive circuit configured to drive the first switching device in response to an output signal from the level conversion circuit; and a power supply circuit that is set up to generate an output voltage at the level of a desired value from a corresponding input voltage and to provide the output voltage as a power supply voltage of the signal output circuit. The power supply circuit includes a variable resistor connected between wiring that is configured to turn on an output voltage is provided, and a predetermined node, a voltage generating circuit arranged to apply a voltage of a predetermined level based on a current from the variable resistor to the predetermined node, an output circuit arranged to do so outputting the output voltage of the target value when the voltage of the predetermined level is applied to the predetermined node, and an adjustment circuit configured to increase a resistance value of the variable resistor as a result of a predetermined period of time elapsing since has elapsed from the start of generation of the output voltage.

[Advantageous Effects of the Invention]

According to the present invention, it is possible to provide a power supply circuit in which a start-up time is short and a stable power supply voltage can be generated.

character list

• 1 FIG. 12 is a diagram illustrating an example of a power module 10. FIG.
• 2 FIG. 12 is a diagram illustrating an example of a signal output circuit 42. FIG.
• 3 FIG. 12 is a diagram illustrating an example of a driving circuit 45. FIG.
• 4 12 shows a diagram for describing the operation of a circuit control IC 20.
• 5 FIG. 12 shows an example of a semiconductor substrate in which a circuit control IC 20 is formed.
• 6 FIG. 12 is a diagram illustrating an example of a power supply circuit 40a.
• 7 12 shows an example of the operation of a power supply circuit 40a.
• 8th 12 is a diagram for describing a start-up time of a power supply circuit 40a.
• 9 12 is a diagram for describing line regulation of a power supply circuit 40a.
• 10 shows an example of a power supply circuit 40b.
• 11 shows an example of a power supply circuit 40c.
• 12 FIG. 12 is a diagram showing an example of the operation of the power supply circuits 40a and 40c.

[Description of the Embodiments]

REFERENCE TO RELATED APPLICATIONS

This application claims priority from Japanese Patent Application No. 2020-134007 , filed August 6, 2020, the entire contents of which are incorporated herein by reference.

At least the following points will become apparent from the explanations of the present specification and the accompanying drawings.

=====Embodiments=====

1 FIG. 12 is a diagram illustrating a configuration of a power module 10 according to a present embodiment of the present invention. The power module 10 is a semiconductor device that drives a load 11 in response to an instruction from a microcomputer (not illustrated), and includes a circuit control IC 20, a half-bridge circuit 21, and a capacitor 22.

The circuit control IC 20 is a high-voltage integrated circuit (HVIC) that controls an operation of the half-bridge circuit 21 in response to an input signal Sin from the microcomputer (not illustrated). The circuit control IC 20 has terminals VCC, IN, GND, B, S, HO and LO. Details of the circuit control IC 20 will be described later.

The half-bridge circuit 21 drives a motor coil of an air conditioner, which is the load 11, for example, and includes an insulated gate bipolar transistor (IGBT) 30 and an IGBT 31.

The IGBT 30 is a high-side switching device having a gate electrode connected to the terminal HO, an emitter electrode connected to the terminal S, and a collector electrode having a predetermined voltage Vdc ( for example "400 V").

IGBT 31 is a low-side switching device having a gate electrode connected to terminal LO, a collector electrode connected to terminal S, and an emitter electrode grounded.

In a present embodiment of the present invention, an IGBT is used as a switching device, but a metal oxide semiconductor (MOS) field effect transistor or a bipolar transistor, for example, can also be used. The IGBT 30 corresponds to a “first switching device on a power supply side”, and the IGBT 31 corresponds to a “second switching device on a ground side”.

The capacitor 22 is connected to the connection B on the one hand and to the connection S on the other hand. The capacitor 22 is charged with a bootstrap voltage Vb applied to the terminal B from a charge pump circuit 41 which will be described later. As a result, the bootstrap voltage Vb is generated across the capacitor 22. The bootstrap voltage Vb is used to turn on the high-side IGBT 30 .

For example, when a voltage Vs at the terminal S is "0 (zero) V", the IGBT 30 is turned on due to the voltage at the gate electrode of the IGBT 30 exceeding a threshold voltage of the IGBT 30 . However, as a result of the turn-on of the IGBT 30, the voltage Vs at the terminal S approaches the voltage Vdc (e.g. "400 V"), so the IGBT 30, with reference to the voltage Vs at the terminal S to which the emitter electrode of the IGBT 30 connected, must be driven to keep the IGBT 30 on.

In an embodiment of the present invention, with reference to the voltage Vs at the terminal S, a voltage is generated at the terminal B that is higher than the voltage Vs by an amount corresponding to the bootstrap voltage Vb. Accordingly, the circuit control IC 20 can turn on the IGBT 30 using the bootstrap voltage Vb. Details of this will be described later.

<<<Configuration of circuit control IC 20>>>

The circuit control IC 20 includes a power supply circuit 40, the charge pump circuit 41, a signal output circuit 42, a level conversion circuit 43, and drive circuits 44 and 45.

The power supply circuit 40 generates a power supply voltage Vreg used within the circuit control IC 20 based on a power supply voltage Vcc (for example, “20V”) applied to the VCC terminal. The power supply circuit 40 according to a present embodiment of the present invention is configured to generate a stable power supply voltage Vreg even when the IGBT 31 is turned on. Details of this will be described later.

The charge pump circuit 41 generates the bootstrap voltage Vb that charges the capacitor 22 based on the power supply voltage Vcc, for example.

The signal output circuit 42 outputs a signal to control the switching of the IGBTs 30 and 31 in response to the input signal Sin of a logic level input through the terminal IN. Specifically, as a result of the input signal Sin, the signal output circuit 42 outputs a set pulse signal S1 to turn on the high-side IGBT 30, a reset pulse signal S2 to turn off the IGBT 30, and a control signal SO to turn on the low-side IGBT 31 Taxes.

As in 2 As illustrated, the signal output circuit 42 includes an input detection circuit 50, a filter circuit 51 and a pulse generation circuit 52. The input detection Circuit 50, the filter circuit 51 and the pulse generating circuit 52 operate based on the power supply voltage Vreg of the power supply circuit 40 with respect to a ground voltage Vgnd. Thus, the respective nodes for grounding of the input detection circuit 50, the filter circuit 51 and the pulse generating circuit 52 are connected to the grounded terminal GND.

The input detection circuit 50 detects the level of the input signal Sin and outputs a signal Sa having the same logic level as the logic level of the input signal Sin. Specifically, the input detection circuit 50 outputs the high signal Sa as a result of the input signal Sin reaching a high level (hereinafter referred to as high or peak level), and as a result of the input signal Sin reaching a low level (hereinafter referred to as low or bottom level) the input detection circuit 50 outputs the low signal Sa. The input detection circuit 50 includes, for example, a comparator (not illustrated).

The filter circuit 51 is a low-pass filter to remove high-frequency noise of the signal Sa, and includes, for example, an operational amplifier (not illustrated) and the like. The filter circuit 51 according to a present embodiment of the present invention outputs a signal obtained by removing noise from the signal Sa as a control signal SO.

The pulse generation circuit 52 outputs the target pulse signal S1 and the reset pulse signal S2 based on a change point of the control signal S0. Specifically, the pulse generating circuit 52 outputs the high set pulse signal S1 in response to a low-to-high transition of the control signal S0, and the pulse generating circuit 52 outputs the reset pulse signal S2 high in response to a high-to-low transition of the control signal S0. According to a present embodiment of the present invention, each of the set pulse signal S1 and the reset pulse signal S2 is a pulse signal whose amplitude level changes in a range from 0V to the power supply voltage Vreg level (for example, 5V).

The level conversion circuit 43 levels-shifts each of the set pulse signal S1 and the reset pulse signal S2 to a level at which a logic circuit (described later) of the drive circuit 45 is operable. Concretely, the level conversion circuit 43 level-shifts the target pulse signal S1 and outputs a target pulse signal S3 having an amplitude level of several tens of volts with respect to the voltage Vs serving as a high-side reference potential, for example. The level conversion circuit 43 level-shifts the reset pulse signal S2 and outputs a reset pulse signal S4 having an amplitude value of, for example, several tens of volts with respect to the voltage Vs.

The drive circuit 44 drives the low-side IGBT 31 in response to the control signal S0. Specifically, the drive circuit 44 outputs a high drive signal Vdr1 to the gate electrode of the IGBT 31 through the terminal LO in response to the low control signal S0. As a result, the IGBT 31 is turned on. On the other hand, the drive circuit 44 outputs a low drive signal Vdr1 to the gate electrode of the IGBT 31 through the terminal LO due to the high control signal S0. As a result, the IGBT 31 is turned off. The drive circuit 44 operates in response to the power supply voltage Vcc.

The drive circuit 45 turns on the high-side IGBT 30 in response to the set pulse signal S3 and turns off the IGBT 30 in response to the reset pulse signal S4. 3 FIG. 12 is a diagram showing an example of the driving circuit 45. FIG. The drive circuit 45 includes a logic circuit 60 and inverters 61 and 62.

The logic circuit 60 outputs a high signal upon receiving the set pulse signal S3, and outputs a low signal upon receiving the reset pulse signal S4. The logic circuit 60 includes, for example, a MOS transistor and a latch circuit, which are not illustrated.

The inverter 61 is a circuit that inverts the logic level of a signal from the logic circuit 60 and outputs a resultant signal. It contains an NMOS transistor 70 and a PMOS transistor 71.

Inverter 62 is a circuit that inverts the logic level of the signal from inverter 61 and outputs a resultant signal as drive signal Vdr2, and includes an NMOS transistor 72 and a PMOS transistor 73.

Thus, upon receiving the adjusted pulse signal S3, the drive circuit 45 outputs the high drive signal Vdr2 to the gate electrode of the IGBT 30 via the terminal HO. On the other hand, upon receiving the reset pulse signal S4, the drive circuit 45 outputs the low drive signal Vdr2 to the gate electrode of the IGBT 30 through the terminal HO.

In this case, the drive signal Vdr2 changes its logic level with respect to the voltage Vs at the terminal S. Thus, the IGBT 30 is turned on due to the high drive signal Vdr2 and turned off due to the low drive signal Vdr2. The drive circuit 45 corresponds to a “drive circuit”, the set pulse signal S3 corresponds to a “set signal”, and the reset pulse signal S4 corresponds to a “reset signal”.

<<<Operation of Circuit Control IC 20>>>

4 12 is a diagram for describing an operation of the circuit control IC 20. The signal output circuit 42 according to an embodiment of the present invention is designed such that a delay time of a signal therein is sufficiently short.

First, the input detection circuit 50 in 2 as a result of the input signal Sin going low at time t0, the signal Sa also going low. The filter circuit 51 then removes the noise (not illustrated) of the signal Sa and outputs the control signal S0 having the same logic level as the signal Sa.

Due to the fall of the control signal S0, the pulse generating circuit 52 outputs the high reset pulse signal S2. As a result, the level-shifted high reset pulse signal S4 is output from the level conversion circuit 43. FIG.

The low-side driver circuit 44 then causes the drive signal Vdr1 to go high in response to the low control signal S0, and the high-side driver circuit 45 causes the drive signal Vdr2 to go low in response to the high reset pulse signal S4 becomes.

As a result, the IGBT 30 is turned off and the IGBT 31 is turned on, thereby lowering the voltage Vs from the voltage Vdc (for example, “400V”) to the voltage Vgnd (in this case, “0V”). As described above, wiring for power supply of the load 11 connected between the terminal S and the load 11 is provided. The load 11 is, for example, a motor coil with a large inductance value. Therefore, when the IGBT 31 turns on, ringing occurs in the voltage Vs, and the voltage Vs becomes a negative voltage smaller than the voltage Vgnd.

As a result of the input signal Sin going high at time t1, the input detection circuit 50 outputs the signal Sa which is also high. The filter circuit 51 then removes the noise (not illustrated) of the signal Sa and outputs the control signal S0 having the same logic level as the signal Sa.

In response to the control signal S0 going high, the pulse generating circuit 52 outputs the high-set pulse signal S1. As a result, the level-shifted high-set pulse signal S3 is output from the level conversion circuit 43. FIG.

The low-side driver circuit 44 causes the drive signal Vdr1 to go low in response to the high control signal S0, and the high-side driver circuit 45 causes the drive signal Vdr2 to go high in response to the high set pulse signal S3.

As a result, the IGBT 30 is turned on and the IGBT 31 is turned off, thereby boosting the voltage Vs from the voltage Vgnd (“0 V” in this case) to the voltage Vdc (“400 V” for example). As described above, the load 11 is connected to the terminal S via the wiring, so when the IGBT 30 is turned on, the voltage Vs rings and the voltage Vs exceeds the voltage Vdc. The process from time t0 to time t1 is repeated from time t2.

«<Semiconductor substrate 100»>

As described above, in an embodiment of the present invention, when the IGBT 31 turns on, the voltage Vs falls below the voltage Vgnd, resulting in a negative voltage ("Vs"<"0V") voltage, a “leakage current” flows from the GND terminal to the S terminal through a semiconductor substrate in which the circuit control IC 20 is formed.

5 FIG. 12 is a diagram for describing a semiconductor substrate 100 in which the circuit control IC 20 is formed. 5 12 illustrates only a partial configuration for describing the “leakage current” in the circuits and terminals of the circuit control IC 20 for simplicity. Specifically illustrated 5 the GND and S terminals and the NMOS transistor 70 of the high-side drive circuit 45.

The semiconductor substrate 100 is, for example, a p-type silicon substrate, with terminals GND and S and a gate electrode 110, a source electrode 111, a drain electrode 112 and a substrate electrode 113 of the NMOS transistor 70 being on the front side of the substrate educated.

In this case, the GND and S terminals and the electrodes of the NMOS transistor 70 are made of, for example, a conductive material such as polysilicon and a metal electrode.

The electrodes of the NMOS transistor 70 are provided with reference numerals which, for the sake of simplicity, are in FIGS 3 and 5 differ, however, the gate electrode 110 of the NMOS transistor 70 corresponds to a "gate electrode Gx", the source electrode 111 thereof to a "source electrode Sx", the drain electrode 112 thereof to a "drain electrode Dx", and the substrate electrode 113 thereof to a "substrate electrode Bx". “.

Within the semiconductor substrate 100 are a semiconductor region 120, a p-type well region 140, an n-type well region 130, p+-type contact regions 150, 160 and 161, an n+-type source region 170 and an n+-type drain region 171. type formed on the semiconductor substrate 100 . If an n+ type or a p+ type is mentioned below, this means that the doping concentration is higher than that of an n type or a p type.

Well region 130 and contact region 150 are formed on an end face of semiconductor region 120 . The connection GND is formed on an end face of the contact area 150 .

The well region 130 contains n-type impurities such as phosphorus, and the p-type well region 140 is formed at an end face of the well region 130 .

The well region 140 contains p-type impurities, and the contact regions 160 and 161, the source region 170 and the drain region 171 are formed on an end face of the well region 140. FIG.

The terminal S is formed in the contact area 160, and the substrate electrode 113 ("Bx") of the NMOS transistor 70 is formed in the contact area 161. FIG.

The source electrode 111 ("Sx") is formed in the source region 170 and the drain electrode 112 ("Dx") is formed in the drain region 171. FIG. The gate electrode 110 ("Gx") is formed on the front side of the well region 140 between the source region 170 and the drain region 171 .

In one embodiment of the present invention, the GND terminal (corresponding to a first terminal) is electrically connected to the semiconductor region 120 via the contact region 150, the S terminal (corresponding to a second terminal) is electrically connected to the well region 140 via the contact region 160, and the substrate electrode 113 ("Bx") is also electrically connected to the well region 140 via the contact region 161 .

In the semiconductor substrate 100 as such, a diode 190 is formed between the p-type semiconductor region 120 and the n-type well region 130 as a parasitic diode. A diode 191 is formed between the p-type well region 140 and the n+-type source region 170 as a parasitic diode.

For example, as a result of the voltage Vs dropping below the voltage Vgnd ("0 V"), resulting in a negative voltage when the IGBT 31 is turned on, the source electrode 111 ("Sx") of the NMOS transistor 70 connected to the terminal S is also connected to a negative voltage. As a result, the diodes 190 and 191 are turned on, and the “leakage current” flows from the GND terminal to the S terminal through a distance indicated by the dot-dash line in 5 is pictured.

As a result of such a “leakage current” flowing from the GND terminal to the S terminal, a current flowing to the signal output circuit 42 also increases, such as in FIG 1 which is connected to the GND terminal so that the voltage Vgnd is a ground voltage. As a result, the power supply voltage Vreg drops sharply, and the signal output circuit 42 may not operate normally.

Preferably, after receiving the power supply voltage Vcc from the external circuit control IC 20, the power supply circuit 40 starts up in a very short time and outputs a stable power supply voltage Vreg regardless of a change in the power supply voltage Vcc. Thus, in one embodiment of the present invention, the power supply circuit 40 has a short start-up time and stably outputs the power supply voltage Vreg even when the voltage Vs becomes a negative voltage or when the power supply voltage Vcc fluctuates.

The semiconductor region 120 according to an embodiment of the present invention corresponds to a “first region”, and the well region 130 corresponds to a “second region”. The well region 140 corresponds to a “third region” and the source region 170 corresponds to a “fourth region”. In this case, the path of the “leakage current” is described using the NMOS transistor 70 as an example, but another device of the driving circuit 45 (e.g., the NMOS transistor 72) generates the “leakage current” in a similar manner.

<<<Example of power supply circuit 40a>>>

6 12 is a diagram illustrating a power supply circuit 40a according to an embodiment of the configuration of the power supply circuit 40. FIG. The power supply circuit 40a generates a temperature-compensated power supply voltage Vreg1 (e.g., “5V”) based on the power supply voltage Vcc. The power supply circuit 40a includes a variable resistor 200, a voltage generating circuit 201, an output circuit 202 and a matching circuit 203. The power supply voltage Vcc according to a present embodiment of the present invention corresponds to an "input voltage", and the power supply voltage Vreg1 corresponds to an "output voltage".

==Variable resistor 200==

The variable resistor 200 determines a value of an inrush current for turning on the power supply circuit 40a and is provided between a wiring L receiving the power supply voltage Vcc and an input node N1 of the output circuit 202 . The variable resistor 200 is a circuit whose resistance value changes in response to an output of the matching circuit 203, and includes resistors 210 and 211 and a PMOS transistor 212.

One end of the resistor 210 is connected to the wiring L, the other end is connected to the input node N1. The resistor 211 and the series-connected PMOS transistor 212 are provided with the resistor 210 in leakage current parallel connection. Thus, the resistance value of the variable resistor 200 increases due to the PMOS transistor 212 turning off, and the resistance value of the variable resistor 200 decreases due to the PMOS transistor 212 turning on.

In a present embodiment of the present invention, the resistance value of variable resistor 200 when PMOS transistor 212 is off (ie, a resistance value 210) is referred to as a resistance value Ra, and the resistance value of variable resistor 200 when PMOS transistor 212 is on (ie, a combined resistance of resistors 210 and 211) is referred to as a resistance Rb. In this case, an on-resistance of the PMOS transistor 212 is sufficiently smaller than the resistance value of the resistor 211, and the resistance value of the resistor 211 is sufficiently smaller than the resistance value of the resistor 210. Accordingly, in a present embodiment, the resistance value Ra is the resistance value of the resistor 210, and the resistance Rb is essentially the resistance of resistor 211.

The input node N1 corresponds to a "predetermined node", the resistor 210 corresponds to a "first resistor", the resistor 211 corresponds to a "second resistor", and the PMOS transistor 212 corresponds to a "switch".

==Voltage generating circuit 201==

The voltage generating circuit 201 applies a voltage V1 of a predetermined level to the input node N1 after receiving a current from the variable resistor 200, and includes five diodes D1 to D5 and a zener diode 220. It should be noted that the diodes D1 to D5 correspond to a "second diode".

wobei „Vz“ eine Durchschlagspannung der Zenerdiode 220 ist und „Vf“ eine Durchlassspannung der Dioden D1 bis D5 ist.The variable resistor 200, the diodes D1 to D5 and the zener diode 220 are connected in series. That is, when the supply voltage Vcc is applied to the wiring L and the current flows out of the variable resistor 200, the voltage V1 at the input node N1 is given by the following formula (1) as follows.
$$\text{V1}=\text{Vz}+5\times \text{vf}$$

where “Vz” is a breakdown voltage of the zener diode 220 and “Vf” is a forward voltage of the diodes D1 to D5.

==Output Circuit 202==

The output circuit 202 outputs the power supply voltage Vreg1 based on the voltage V1 at the input node N1 and includes a bias voltage generation circuit 230, a withstand voltage circuit 231, NPN transistors 232 and 233, and a resistor 234.

The bias voltage generating circuit 230 generates a bias voltage V3 based on the voltage V1 at the input node N1 and includes an NPN transistor 240, resistors 241 and 242, and three diodes D6 to D8.

wobei „Vbe“ eine Basis-Emitter-Spannung des NPN-Transistors 240 ist. In der Vorspannungserzeugungsschaltung 230 wird eine Spannungsdifferenz zwischen einer Durchlassspannung „3×Vf“ der drei Dioden D6 bis D8 und der Spannung V2 durch eine Spannungsteilerschaltung geteilt, die mit den Widerständen 241 und 242 eingerichtet ist. Die Vorspannung V3 an einem Knoten, mit dem die Widerstände 241 und 242 verbunden sind, wird also durch die folgende Formel (3) angegeben.
$$\begin{array}{l}\text{V3}=3\times \text{Vf}+\left(\text{V2}-3\times \text{Vf}\right)\times \left(\text{R2}/\left(\text{R1}+\text{R2}\right)\right)\\ =3\times \text{Vf}+\left(\text{Vz}+2\times \text{Vf}-\text{Vbe}\right)\times \left(\text{R2}/\left(\text{R1}+\text{R2}\right)\right)\end{array}$$

wobei „R1“ ein Widerstandswert des Widerstands 241 ist und „R2“ ein Widerstandswert des Widerstands 242 ist.The NPN transistor 240 has a base electrode which receives the voltage V1 and an emitter electrode to which the diodes D6 to D8 are connected via the resistors 241 and 242. Thus, a voltage V2 given by the following formula (2) is output from the emitter electrode of the NPN transistor 240 .
$$\text{v2}=\text{V1}-\text{Vbe}=\text{Vz}+5\times \text{vf}-\text{Vbe}$$

where "Vbe" is a base-emitter voltage of NPN transistor 240 . In the bias voltage generating circuit 230, a voltage difference between a forward voltage “3×Vf” of the three diodes D6 to D8 and the voltage V2 is divided by a voltage dividing circuit configured with the resistors 241 and 242. Thus, the bias voltage V3 at a node to which the resistors 241 and 242 are connected is given by the following formula (3).
$$\begin{array}{l}\text{V3}=3\times \text{vf}+\left(\text{v2}-3\times \text{vf}\right)\times \left(\text{R2}/\left(\text{R1}+\text{R2}\right)\right)\\ =3\times \text{vf}+\left(\text{Vz}+2\times \text{vf}-\text{Vbe}\right)\times \left(\text{R2}/\left(\text{R1}+\text{R2}\right)\right)\end{array}$$

where "R1" is a resistance value of the resistor 241 and "R2" is a resistance value of the resistor 242.

The withstand voltage circuit 231 protects the NPN transistors 232 and 233 from an overvoltage and includes four diodes D9 to D12 connected in series.

An emitter electrode of NPN transistor 232 is connected to a base electrode of NPN transistor 233 and a collector electrode of NPN transistor 232 is connected to a collector electrode of NPN transistor 233 . Accordingly, according to a present embodiment of the present invention, the NPN transistors 232 and 233 are provided as a Darlington circuit and thus can drive a larger load. Note that each of NPN transistors 232 and 233 corresponds to a "second transistor".

As described above, the voltage V3 is applied to the base electrode of the NPN transistor 232 in a first stage, and thus the supply voltage Vreg1 indicated by the following formula (4) is output from the emitter electrode of the NPN transistor 233.
$$\begin{array}{l}\text{Reg1}=\text{V3}-2\times \text{Vbe}\\ =\left(3\times \text{vf}+\left(\text{Vz}+2\times \text{vf}-\text{Vbe}\right)\times \left(\text{R2}/(\text{R1}+\text{R2}\right)\right)-2\times \text{Vbe}\end{array}$$

The resistor 234 is an element for uniformly generating the supply voltage Vreg1. When there is no resistor 234, the current flowing through the NPN transistors 232 and 233 becomes zero due to the no-load state of the power supply circuit 40a. Thus, the generation of the supply voltage Vreg1 is stopped.

In this state, when the current starts flowing through the load of the power supply circuit 40a, it takes a while for the power supply circuit 40a to generate the power supply voltage Vreg1.

In a present embodiment of the present invention, current continues to flow through resistor 234 even when the load condition of power supply circuit 40a is no load. Thus, the power supply circuit 40a can stably generate a predetermined power supply voltage Vreg1 regardless of the state of the load of the power supply circuit 40a.

A temperature coefficient of breakdown voltage “Vz” of zener diode 220 is positive, and a temperature coefficient of forward voltage “Vf” of diodes D1 to D12 is negative. A temperature coefficient of the base-emitter voltage "Vbe" is negative.

In a present embodiment of the present invention, as resistors 241 and 242, resistors of the same type (e.g. polysilicon) with the same temperature coefficient are used. Accordingly, the temperature coefficient of the term “R2/(R1+R2)” in Formula (4) can be largely ignored.

For example, in an embodiment of the present invention, the number of diodes D1 to D12 is adjusted based on the formula (4) so that the power supply voltage Vreg1 is temperature-compensated. Accordingly, the level of the power supply voltage Vreg1 is constant regardless of the temperature. In an embodiment of the present invention, by changing the resistance ratio of the resistors 241 and 242, it is possible to adjust the power supply voltage Vreg1 to a desired level.

For example, the power supply circuit 40a includes the NPN transistors 232 and 233 in Darlington connection, so that the output current capability is high. In addition, the power supply circuit 40a may provide the temperature-compensated power supply voltage Vreg1 at a predetermined level (e.g., “5V”).

==Matching circuit 203==

The adjusting circuit 203 adjusts the resistance value of the variable resistor 200 based on the power supply voltage Vreg1. In particular, the adjustment circuit 203 reduces the resistance value of the variable resistor 200 as a result of stopping generation of the power supply voltage Vreg1. On the other hand, the adjustment circuit 203 increases the resistance value of the variable resistor 200 as a result of a predetermined period of time T that has elapsed from the start of generation of the power supply voltage Vreg1.

The matching circuit 203 includes a detection circuit 250 and a control circuit 251. The detection circuit 250 detects whether the predetermined time T has elapsed from the start of generation of the power supply voltage Vreg1, and includes resistors 260 and 271, a capacitor 261, an NMOS transistor 270 and a diode 272. In a present embodiment of the present invention, resistor 260 corresponds to a "third resistor", NMOS transistor 270 corresponds to a "first transistor", and diode 272 corresponds to a "first diode".

The resistor 260 and the capacitor 261 form an integrator circuit that integrates the power supply voltage Vreg1. A gate of NMOS transistor 270 is connected to a node to which resistor 260 and capacitor 261 are connected. The NMOS transistor 270 and the resistor 271 form an inverter. When a charged voltage Vx1 of the capacitor 261 is smaller than a threshold voltage Vth of the NMOS transistor 270, a voltage Vx2, which is an output value of the inverter, becomes high. On the other hand, due to the charging voltage Vx1 exceeding the threshold voltage Vth of the NMOS transistor 270, the voltage Vx2 becomes low.

The diode 272 discharges the capacitor 261 as a result of stopping generation of the power supply voltage Vreg1 and lowering the power supply voltage Vreg1, for example. Details of an operation of the diode 272 will be described later.

The control circuit 251 controls the on and off of the PMOS transistor 212 in the variable resistor 200 depending on the voltage Vx2. The control circuit 251 includes a PMOS transistor 280 and a resistor 281 configuring an inverter. For example, the control circuit 251 causes a voltage Vx3, which is an output of the inverter, to go low as a result of stopping the generation of the power supply voltage Vreg1 and going high the voltage Vx2. As a result, the PMOS transistor 212 is turned on, and the resistance value of the variable resistor 200 becomes a value corresponding to the combined resistance of the resistors 210 and 211.

On the other hand, the control circuit 251 causes the voltage Vx3 to be high due to the predetermined time T elapsed from the start of generation of the power supply voltage Vreg1 and the lowering of the voltage Vx2. As a result, the PMOS transistor 212 is turned off, and the resistance value of the variable resistor 200 becomes the large resistance value Ra(>Rb).

For example, the values of the resistor 260 and the capacitor 261 are selected so that the predetermined period of time T is longer than a period of time from when generation of the power supply voltage Vreg1 is started to when the power supply voltage Vreg1 is started to be generated, according to an embodiment of the present invention. at which the level of the power supply voltage Vreg1 reaches a target value (e.g. 5 V). Accordingly, in an embodiment of the present invention, it is possible to reliably increase the starting current of the power supply circuit 40a so that the power supply voltage Vreg1 reaches a target value.

<<<Example of operation of power supply circuit 40a>>>

7 FIG. 12 is a diagram for describing an operation when the power supply voltage Vcc is supplied to thereby operate the power supply circuit 40a. First, at time t10, due to the application of the power supply voltage Vcc from the outside of the circuit control IC 20, the level of the power supply voltage Vcc of the wiring L rises, and generation of the power supply voltage Vreg1 is also started. In a present embodiment of the present invention, “timing when generation of power supply voltage Vreg1 is started” means, for example, timing when power supply voltage Vcc is applied to wiring L (in this case, the wiring L) to operate power supply circuit 40a Time t10).

From time t10, the level of power supply voltage Vreg1 gradually rises. However, since the charged voltage Vx1 of the capacitor 261 is lower than the threshold voltage Vth of the NMOS transistor 270, the NMOS transistor 270 is turned off. In this state, when the level of the power supply voltage Vcc rises, the voltage Vx2 at the node where the NMOS transistor 270 and the resistor 271 are connected also rises gradually.

For example, at time t11, as a result of the supply voltage Vcc reaching a target value (e.g. 20 V), the voltage Vx2 also rises. At this point, PMOS transistor 280 is the Control circuit 251 is off and voltage Vx3 is low. Accordingly, the PMOS transistor 212 of the variable resistor 200 is turned on due to an increase in the power supply voltage Vcc, and the resistance value of the variable resistor 200 becomes the small resistance value Rb.

Since a large current flows from the variable resistor 200 to the NPN Darlington-connected transistors 232 and 233 via the input node N1, the power supply voltage Vreg1 rises rapidly. As a result, the level of the power supply voltage Vreg1 reaches a target value (for example, 5 V) at time t12, for example.

In a present embodiment of the present invention, it is assumed that, for example, a period from the start of generation of the power supply voltage Vreg1 until the level of the power supply voltage Vreg1 reaches the target value (period from time t10 to t12) is a “startup time” of the power supply circuit 40a. It is also assumed that the current flowing through the variable resistor 200 from the wiring L to the input node N1 at the start-up time of the power supply circuit 40a is “start-up current”.

At time t13 when the predetermined time T has elapsed from time t10, the level of voltage Vx1 reaches the threshold voltage Vth of NMOS transistor 270, and thus NMOS transistor 270 is turned on. As a result, the voltage Vx2 of the detection circuit 250 becomes low and the control circuit 251 causes the voltage Vx3 to become high. As a result of turning off the PMOS transistor 212, the resistance value of the variable resistor 200 becomes the large resistance value Ra(>Rb). This improves the conduction regulation of the power supply circuit 40a compared to the case of the resistance value Rb. Details of this will be described later.

As a result of stopping the supply of the power supply voltage Vcc at time t14, the level of the power supply voltage Vreg1 also falls rapidly, and eventually the generation of the power supply voltage Vreg1 also stops. As a result, the level of the supply voltage Vreg1 also drops rapidly. In this case, the diode 272 has a cathode electrode connected to the emitter electrode of the NPN transistor 233, which is an output node of the power supply circuit 40a, and an anode electrode connected to the capacitor 261. Accordingly, when the power supply voltage Vreg1 decreases, the diode 272 is turned on to thereby discharge the capacitor 261. FIG.

Due to the discharge of the capacitor 261, the charging voltage Vx1 drops to a voltage lower than the threshold voltage Vth (for example, substantially 0 V), and thus the NMOS transistor 270 is turned off. As a result, the node at which the NMOS transistor 270 and the resistor 271 are connected is boosted to the power supply voltage Vcc via the resistor 271, and thus the PMOS transistor 280 is turned off.

In this state, due to the resumption of the supply voltage Vcc, for example, the voltage Vx2 becomes high and the voltage Vx3 becomes low, and thus the PMOS transistor 212 of the variable resistor 200 is turned on. Therefore, the matching circuit 203 in 7 at time t14, which is a time when the supply of the power supply voltage Vcc is stopped, set the resistance value of the variable resistor 200 to the small resistance Rb. Accordingly, in an embodiment of the present invention, the starting current of the power supply circuit 40a can be increased while maintaining the power supply voltage Vcc.

<<<start-up time>>>

8th FIG. 12 is a graph for describing a relationship between the resistance value of the variable resistor 200 and the rise time. As described above, in an embodiment of the present invention, the resistance value of the variable resistor 200 when the power supply circuit 40a is turned on is the small resistance value Rb, and thus a waveform of the power supply voltage Vreg1 indicated by the solid line in 8th is shown.

For example, when the resistance value of the variable resistor 200 is the large resistance value Ra(>Rb) when the power supply circuit 40a starts up, the value of the starting current decreases. As a result, in the power supply circuit 40a, in decreases 6 also the current flowing from the wiring L through the variable resistor 200, the input node N1, the NPN transistor 240 and the resistor 241 to the NPN transistor 232 in Darlington configuration. In such a case, the start-up time of the supply increases voltage Vreg1, as can be seen from the waveform indicated by the dot-dash line in 8th is shown. In an embodiment of the present invention, the resistance value of the variable resistor 200 at the start-up of the power supply circuit 40a is the small resistance value Rb, whereby the start-up time of the power supply circuit 40a can be reduced.

«<Line control»>

9 12 is a graph showing a relationship between the resistance value of the variable resistor 200 and the conduction regulation of the power supply circuit 40a. As described in the above formulas (1) to (4), the power supply voltage Vreg1 is affected by the voltage V1 applied to the input node N1 of the output circuit 202. FIG. The theoretical formula for the voltage V1 at the input node N1 is V1 = Vz + 5 x Vf according to the formula (1). However, the diodes D1 to D5 and the zener diode 220 contain a parasitic resistance. The smaller the resistance of the variable resistor 200 becomes, the more the actual voltage V1 is affected by the parasitic resistance of the diode D1 and the like.

As can be seen from the dashed line in 9 shows, when the resistance value of the variable resistor 200 is the small resistance value Rb, the power supply voltage Vreg1 increases sharply with an increase in the power supply voltage Vcc. On the other hand, when the resistance value of the variable resistor 200 is a large resistance value Ra(>Rb), the effects of the parasitic resistance of the diode D1 and the like decrease. As a result, as indicated by the solid line in 9 1, the power supply voltage Vreg1 is substantially constant (V1=Vz+5×Vf) even when the power supply voltage Vcc increases.

In a present embodiment of the present invention, the resistance value Ra is set to be sufficiently larger than the value of the parasitic resistance of the diode D1 and the like so that the effects of the parasitic resistance of the diode D1 and the like can be ignored. Accordingly, as a result of the power supply circuit 40a starting up and the variable resistor 200 reaching the large resistance value Ra, such as at time t13 in FIG 7 specified, reduce the fluctuation (ie, line regulation) of the power supply voltage Vreg1.

<<<Example of power supply circuit 40b>>>

10 12 is a diagram illustrating a power supply circuit 40b according to another embodiment of the configuration of the power supply circuit 40. FIG. Like the power supply circuit 40a, the power supply circuit 40b generates a temperature-compensated power supply voltage Vreg2 (e.g., “5V”) based on the power supply voltage Vcc. The power supply circuit 40b includes a variable resistor 500, a voltage generating circuit 501, an output circuit 502 and a matching circuit 503. The elements shown in FIG 6 and 10 are identical have the same reference numbers.

==Variable resistor 500==

The variable resistor 500 determines a value of starting current for starting the power supply circuit 40b and is provided between the wiring L receiving the power supply voltage Vcc and an input node N2 of the output circuit 502. FIG. The variable resistor 500 is a circuit whose resistance value changes in response to an output from the matching circuit 503, and includes resistors 510 to 512 and a PMOS transistor 513.

The resistors 510 and 511 are connected in series and provided between the wiring L and the input node N2. The resistor 512 and the series-connected PMOS transistor 513 are provided with the resistors 510 and 511 connected in parallel. Thus, the resistance value of the variable resistor 500 increases due to the PMOS transistor 513 turning off, and the resistance value of the variable resistor 500 decreases due to the PMOS transistor 513 turning on.

In an embodiment of the present invention, the resistance value of the variable resistor 500 when the PMOS transistor 513 is turned off is referred to as a resistance value Rc, and the resistance value of the variable resistor 500 when the PMOS transistor 513 is turned on is referred to as a resistance value Rd denoted. In this case, an on-resistance of the PMOS transistor 513 is sufficiently less than the resistance of resistor 512, and the resistance of resistor 512 is sufficiently less than the resistance of the combined resistance of resistors 510 and 511. Accordingly, in a present embodiment, the resistance Rc corresponds to the resistance of the combined resistance of resistors 510 and 511 , and the resistance value Rd essentially corresponds to the resistance value of the resistor 512.

The input node N2 corresponds to a "predetermined node", the combined resistance of the resistors 510 and 511 corresponds to a "first resistance", the resistor 512 corresponds to a "second resistance", and the PMOS transistor 513 corresponds to a "switch".

==Voltage Generation Circuit 501==

The voltage generating circuit 501 generates a voltage V10, V11 of a predetermined level with the variable resistor 500 to operate the output circuit 502. FIG. The voltage generating circuit 501 includes the four diodes D1 to D4 and the zener diode 220. The PMOS transistor 513 of the variable resistor 500 is turned off at a time after the power supply circuit 40b is operated and the power supply voltage Vreg2 reaches a set value (for example, 5 V). has reached. Details of this will be described later. Therefore, a state where the PMOS transistor 513 is off and the variable resistor 500 is the combined resistance of the resistors 510 and 511 will be mainly described here.

wobei „R10“ ein Widerstandswert des Widerstands 510 ist und „R11“ ein Widerstandswert des Widerstands 511 ist. Die Spannung V10 an einem Knoten, an dem die Widerstände 510 und 511 verbunden sind, ist somit durch die Formel (6) angegeben: $$\text{V10}=\text{Vcc}-\text{R10}\times \text{I}\text{.}$$

The resistors 510 and 511 of the variable resistor 500, the diodes D1 to D4 and the zener diode 220 are connected in series. In a state where the power supply voltage Vcc is applied to the wiring L, a current I flowing through the resistors 510 and 511 is given by the formula (5) as follows.
$$\text{I}=\left(\text{Vcc}-\left(\text{Vz}+4\times \text{vf}\right)\right)/\left(\text{R10}+\text{R11}\right)$$

where “R10” is a resistance value of the resistor 510 and “R11” is a resistance value of the resistor 511. The voltage V10 at a node where resistors 510 and 511 are connected is thus given by formula (6): $$\text{V10}=\text{Vcc}-\text{R10}\times \text{I}\text{.}$$

The voltage V11 at the input node N2, where the resistor 511 and the diode D1 are connected, is given by the formula (7): $$\text{V11}=\text{Vz}+4\times \text{vf}$$

The voltage generating circuit 501 according to an embodiment of the present invention includes the four diodes D1 to D4. However, as the number of diodes increases, the level of voltage V11 exceeds the level of power supply voltage Vcc. Accordingly, in the voltage generating circuit 501, the number of diodes must be adjusted so that the level of the voltage V11 is lower than the level of the power supply voltage Vcc.

==Output circuit 502==

The output circuit 502 outputs the power supply voltage Vreg2 based on the voltage V11 at the input node N2, and includes a bias voltage generation circuit 520, a withstand voltage circuit 521, the NPN transistors 232 and 233, and the resistor 234.

Bias voltage generating circuit 520 generates a voltage V12, V14 of a predetermined level and includes NPN transistors 530 and 531, resistors 241 and 242, and three diodes D6 to D8.

NPN transistor 530 has a base electrode that receives voltage V10 and an emitter electrode to which NPN transistor 531 is connected. The NPN transistor 530 thus operates as an emitter follower. Accordingly, the emitter electrode of the NPN transistor 530 is represented by the following Formula (8) given voltage V12 output. Hereinafter, a base-emitter voltage of NPN transistors 530 and 531 is denoted as “Vbe”: $$\text{V12}=\text{V10}-\text{Vbe}$$

The NPN transistor 531 has a base electrode which receives the voltage V11 and an emitter electrode to which the diodes D6 to D8 are connected via the resistors 241 and 242. The NPN transistor 531 also works as an emitter follower. Accordingly, a voltage V13 given by the following formula (9) is output from the emitter electrode of the NPN transistor 531 .
$$\text{V13}=\text{V11}-\text{Vbe}=\text{Vz}+4\times \text{vf}-\text{Vbe}$$

In the bias voltage generating circuit 520, a voltage difference between the forward voltage "3xVf" of the three diodes D6 to D8 and the voltage V13 is divided by the voltage dividing circuit configured with the resistors 241 and 242. Thus, the bias voltage V14 at a node to which the resistors 241 and 242 are connected is given by the following formula (10): $$\begin{array}{l}\text{V14}=3\times \text{vf}+\left(\text{v2}-3\times \text{vf}\right)\times \left(\text{R2}/\left(\text{R1}+\text{R2}\right)\right)\\ =3\times \text{vf}+\left(\text{Vz}+2\times \text{vf}-\text{Vbe}\right)\times \left(\text{R2}/\left(\text{R1}+\text{R2}\right)\right)\end{array}$$

The number of diodes in the voltage generating circuit 501 is four. However, as the number of diodes decreases, voltages across voltages V10 and V11 decrease, and consequently a collector-emitter voltage Vce1 of NPN transistor 530 and a collector-emitter voltage Vce2 of NPN transistor 531 increase.

wobei die Spannungen Vce1m und Vce2m in der Formel (11) Spannungswerte sind, die die Stehspannungen der Spannungen Vce1 bzw. Vce2 angeben.In order to prevent the voltages Vce1 and Vce2 from exceeding their respective withstand voltages, the number (x) of diodes in the voltage generating circuit 501 must satisfy the following condition: $$\text{Vcc}\le \text{Vz}+\text{x}\times \text{vf}+\left(\text{Vce1m}+\text{Vce2m}\right)-\text{Vbe}$$

where the voltages Vce1m and Vce2m in the formula (11) are voltage values indicating the withstand voltages of the voltages Vce1 and Vce2, respectively.

The withstand voltage circuit 521 protects the NPN transistors 232 and 233 from an overvoltage and includes an NPN transistor 540 and two diodes D9 and D10 connected in series. NPN transistor 540 has a base electrode that receives voltage V12 and an emitter electrode to which diodes D9 and D10 are connected. Thus, NPN transistor 540 operates as an emitter follower.

The arrangement formed by the NPN transistors 232 and 233 in Darlington connection, and the resistor 234 is the same as in FIG 6 , and thus it is possible to operate a large load. As described above, the voltage V14 is applied to the base electrode of the NPN transistor 232 in the first stage, and thus the supply voltage Vreg2 given by the formula (12) below is output from the emitter electrode of the NPN transistor 233.
$$\text{Reg2}=\text{V14}-2\times \text{Vbe}\left(3\times \text{vf}-\text{Vbe}\right)\times \left(\text{R2}/\text{R1}+\text{R2}\right)))-2\times \text{Vbe}$$

Since the resistor 234 is an element for continuously generating the power supply voltage Vreg2, the power supply circuit 40b can continuously generate a predetermined power supply voltage Vreg2, like the power supply circuit 40a, regardless of the state of the load.

For example, in an embodiment of the present invention, the numbers of diodes D1 to D4 and D6 to D8 are adjusted based on the formula (12) so that the power supply voltage Vreg2 is temperature-compensated. Accordingly, the level of the supply voltage Vreg2 is constant regardless of the temperature. Furthermore, it is possible, for example, the supply voltage Set Vreg2 to a predetermined level by changing the resistance ratio between resistors 241 and 242.

For example, like the power supply circuit 40a, the power supply circuit 40b includes the NPN transistors 232 and 233 in Darlington connection, so that the output current capability is high and it is possible to output the temperature-compensated power supply voltage Vreg2 at a predetermined level (e.g., “5 V”).

wobei Vce3m die Emitter-Kollektor-Stehspannung des NPN-Transistors 530 ist, Vce4m die Emitter-Kollektor-Stehspannung des NPN-Transistors 233 ist und y die Anzahl der Dioden ist, die in der Stehspannungsschaltung 521 enthalten sind.Furthermore, in an embodiment of the present invention, the following condition must be met: $$\text{Vcc}\le \text{vf}\times \text{y}+\text{Vce3m}+\text{Vce4m}+\text{Reg2}$$

where Vce3m is the emitter-collector withstand voltage of NPN transistor 530, Vce4m is the emitter-collector withstand voltage of NPN transistor 233, and y is the number of diodes included in withstand voltage circuit 521.

In an embodiment of the present invention, it is possible to properly protect the NPN Darlington-connected transistors 232 and 233 even at a high level of the power supply voltage Vcc by adjusting the number of diodes in the withstand voltage circuit 521, for example.

==Matching Circuit 503==

The adjusting circuit 503 adjusts the resistance value of the variable resistor 500 based on the power supply voltage Vreg2. In particular, the adjustment circuit 503 reduces the resistance value of the variable resistor 500 as a result of stopping generation of the power supply voltage Vreg2. On the other hand, the adjustment circuit 503 increases the resistance value of the variable resistor 500 as a result of the predetermined time T that has elapsed from the start of generation of the power supply voltage Vreg2.

The matching circuit 503 uses a later-described current mirror circuit that uses the capacitor 261 in place of the resistor 260 of the matching circuit 203 in 6 charges, and includes a detection circuit 550 and the control circuit 251.

The detection circuit 550 detects whether the predetermined time T has elapsed from the start of generation of the power supply voltage Vreg2, and includes PMOS transistors 600 and 601, resistors 271 and 602, the capacitor 261, an NMOS transistor 270 and a diode 272. Compares Considering the matching circuit 203 and the matching circuit 503, their configurations except for the PMOS transistors 600 and 601 and the resistor 602 are identical. Therefore, the PMOS transistors 600 and 601 and the resistor 602 will be mainly described here.

The PMOS transistors 600 and 601 and the resistor 602 configure the “current mirror circuit” that operates based on the power supply voltage Vreg2. Accordingly, the PMOS transistor 601 outputs a predetermined current as a result of the rise in the supply voltage Vreg2, for example to a target value. In a present embodiment of the present invention, the size ratio between the PMOS transistors 600 and 601 is adjusted so that a current of the PMOS transistor 601 is smaller than a current of the PMOS transistor 600.

The value of the current of the PMOS transistor 601 is adjusted so that the predetermined length of time T from the charging of the capacitor 261 until the charging voltage Vx1 reaches the threshold voltage of the NMOS transistor 270 is longer than the start-up time of the Power supply voltage Vreg2. Accordingly, in an embodiment of the present invention, it is possible to reliably increase the starting current of the power supply circuit 40b so that the power supply voltage Vreg2 reaches a target value.

As with the matching circuit 203, when the power supply circuit 40b starts up, the matching circuit 503 sets the resistance value of the variable resistor 500 to the small resistance value Rc, and when the predetermined time T has elapsed from the start of generation of the power supply voltage Vreg2, the matching circuit 503 sets the resistance value of variable resistor 500 to the large resistance value Rd. Accordingly, like the power supply circuit 40a, it is possible to improve the conduction regulation of the power supply circuit 40b.

<<<Example of power supply circuit 40c>>>

11 12 is a diagram illustrating an example of a power supply circuit 40c according to another embodiment of the power supply circuit 40. FIG. In this case, the power supply circuit 40c has an output current capability that is smaller than the output current capability of the power supply circuit 40a. The power supply circuit 40c includes an NMOS transistor 800 and a current source 801.

The NMOS transistor 800 and the current source 801 form a source follower. Thus, from a source electrode of the NMOS transistor 800, a supply voltage Vreg3 corresponding to a bias voltage Vbias applied to a gate electrode of the NMOS transistor 800 is output.

<<<Example of waveform when IGBT 31 turns on>>>

12 FIG. 12 is a diagram illustrating a result of comparison between a case of using the power supply circuit 40a and a case of using the power supply circuit 40c in the circuit control IC 20. FIG.

«Case of using the power supply circuit 40a»

First, a change in the power supply voltage Vreg1 when the circuit control IC 20 uses the power supply circuit 40a will be described.

As a result of operating the circuit control IC 20 to thereby turn on the low-side IGBT 31 at time ta, for example, the voltage Vs becomes a negative voltage as described above. As a result, the “leakage current” flows from the GND terminal to the S in terminal 1 , and thus the current flowing to the signal output circuit 42 increases. It should be noted that the power supply circuit 40a includes the NPN transistors 232 and 233 in Darlington configuration as described above. Thus, the power supply circuit 40a can supply a large current while raising the supply voltage Vreg1 to a target value.

As a result, the power supply circuit 40a, as indicated by the solid line in FIG 12 shown, the power supply voltage Vreg1 can be prevented from dropping sharply, whereby the operation of the circuit control IC 20 can be stabilized.

«Case of using the power supply circuit 40c»

Next, a change in the power supply voltage Vreg3 when the circuit control IC 20 uses the power supply circuit 40c will be described. In this case, it is assumed that the circuit control IC 20 using the power supply circuit 40c is activated to thereby turn on the low-side IGBT 31 at a timing of the above time ta.

As a result of the IGBT 31 turning on, the “leakage current” flows from the GND terminal to the S terminal, and thus the current flowing to the signal output circuit 42 increases.

The output stability of the power supply circuit 40c is poor compared to that of the power supply circuit 40a. For this reason, the power supply voltage Vreg3 of the power supply circuit 40c drops sharply with an increase in the current flowing to the signal output circuit 42, as shown by the chain line in FIG 12 shown. Depending on the magnitude of the power supply voltage Vreg3, malfunctions occur in the signal output circuit 42, which, for example, outputs the set pulse signal S1 at an incorrect timing.

Accordingly, in the circuit control IC 20 in which the voltage Vs is a negative voltage and the “leakage current” flows through the semiconductor region 120 to the terminal S, it is preferable to use the power supply circuit 40a excellent in output stability. With the Using the power supply circuit 40a, the circuit control IC 20 can stabilize the operation of the circuit control IC 20.

The case of using the power supply circuit 40a in the circuit control IC 20 has been described here, but the power supply circuit 40b also includes the plurality of Darlington-connected transistors. Accordingly, it is also possible to stabilize the operation of the circuit control IC 20 even when the power supply circuit 40b is used.

===Summary===

The power module 10 according to an embodiment of the present invention has been described above. The resistance value of the variable resistor 200 of the power supply circuit 40a becomes the small resistance value Rb when the power supply circuit 40a starts up, and thereafter becomes the large resistance value Ra. Accordingly, with the power supply circuit 40a, it is possible to generate a stable power supply voltage Vreg1 while reducing the start-up time.

The adjusting circuit 203 increases the resistance value of the variable resistor 200 after the level of the output voltage Vreg1 becomes a target value. That is, in an embodiment of the present invention, the variable resistor 200 does not increase before the output voltage Vreg1 reaches a target value, whereby the start-up time can be reduced more reliably.

The matching circuit 203 decreases the resistance value of the variable resistor 200 as a result of stopping generation of the output voltage Vreg1. Thereby, it is possible to shorten the start-up time when the output voltage Vreg1 is generated after the generation of the output voltage Vreg1 is stopped.

The variable resistor 200 may include, for example, the resistor 210 and the PMOS transistor 212 provided with the resistor 210 in parallel. Even with such a configuration, it is possible to shorten the start-up time and also improve line regulation.

For example, when the resistor 211 is not used in the variable resistor 200, a voltage substantially equal to the power supply voltage Vcc is applied to the input node N1 when the power supply circuit 40a starts up. This may cause the power supply voltage Vreg1 to exceed a target value. In an embodiment of the present invention, when the power supply circuit 40a starts up, the power supply voltage Vcc is applied through the resistor 211 of the variable resistor 200 to the input node N1. In this way, the power supply voltage Vreg1 can be prevented from overshooting when the power supply circuit 40a starts up.

The matching circuit 203 may include, for example, the detection circuit 250 that detects whether the predetermined time T has elapsed from the start of generation of the output voltage Vreg1, and the control circuit 251 that controls the PMOS transistor 212 based on the detection result of the detection circuit 250 controls.

An integrator circuit, for example, can be used as a circuit for measuring the predetermined period of time T. However, in case of an increase in the predetermined time T, a resistance and the like of the integrator circuit must be increased. The detection circuit 550 charges the capacitor 261 to measure the predetermined time T with a small current from the current mirror circuit, whereby the area to be occupied by the detection circuit 550 in the circuit control IC 20 can be reduced.

Furthermore, as a circuit for measuring the predetermined length of time T, an integrator circuit of the detection circuit 250 can be used.

The voltage generating circuit 201 includes the zener diode 220 and the diodes D1 to D5, whereby the power supply voltage Vreg1 can be temperature-compensated.

The output circuit 202 includes the two-level NPN transistors 232 and 233 in Darlington connection, whereby the current driving capability can be increased.

In one embodiment of the present invention, the two-stage Darlington-connected transistors are NPN transistors 232 and 233, respectively; however, PNP transistors, for example, can also be used. Note that similar effects as in an embodiment of the present invention can also be obtained when the power supply circuit 40a has a configuration including Darlington-connected transistors in three or more stages, for example.

It is possible to reduce the start-up time and improve the conduction regulation even if a common source-follower circuit and emitter-follower circuit are used instead of the output circuit 202, 502.

In the power supply circuit 40b, the matching circuit 203 can be used instead of the matching circuit 503, and in the power supply circuit 40a, the matching circuit 503 can be used instead of the matching circuit 203.

The above-described embodiments of the present invention are only intended to facilitate understanding of the present invention and are not to be construed as limiting the present invention in any way. The present invention can be variously changed or modified without departing from the essential characteristics thereof, and includes equivalents thereof.

Reference List

10

power module

20

Circuit Control IC

21

half-bridge circuit

22.261

capacitor

30.31

IGBT

40:40a-40c

power supply circuit

41

charge pump circuit

42

signal output circuit

43

level converter circuit

44.45

drive circuit

50

input detection circuit

51

filter circuit

52

pulse generation circuit

60

logic circuit

61, 62

inverters

70, 72, 270, 800

NMOS transistor

71, 73, 212, 280, 513, 600, 601

PMOS transistor

100

semiconductor substrate

110

gate electrode

111

source electrode

112

drain electrode

113

substrate electrode

120

semiconductor area

130, 140

tub area

150, 160, 161

contact area

170

source area

171

drain area

190, 191, 272, D1-D12

diode

200, 500

variable resistance

201,501

voltage generating circuit

202,502

output circuit

203,503

matching circuit

210, 211, 234, 241, 242, 260, 271,

Resistance

281, 510, 511, 512, 602, 621, 701 220

zener diode

232, 233, 240, 530, 531, 540

NPN transistor

231,521

withstand voltage circuit

250,550

detection circuit

251,551

control circuit

801

power source

L

wiring

N1, N2

input node

QUOTES INCLUDED IN DESCRIPTION

This list of documents cited by the applicant was generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Patent Literature Cited

• JP 2006159472 [0003]
• JP 2020134007 [0009]

Claims (11)

Power supply circuit that is set up to generate an output voltage at the level of a desired value from an input voltage, the power supply circuit comprising: a variable resistor provided between wiring configured to receive the input voltage and a predetermined node; a voltage generation circuit configured to apply a voltage of a predetermined level to the predetermined node based on a current from the variable resistor; an output circuit configured to output the output voltage of the target value when the voltage of the predetermined level is applied to the predetermined node; and an adjustment circuit configured to increase a resistance value of the variable resistor as a result of a predetermined time elapsed from the start of generation of the output voltage. Power supply circuit according to claim 1 , wherein the predetermined period of time is longer than a period of time from the start of generation of the output voltage until the point at which the output voltage reaches the target value. Power supply circuit according to claim 1 or 2 , wherein the matching circuit is further configured to decrease the resistance value of the variable resistor as a result of stopping generation of the output voltage. Power supply circuit according to one of Claims 1 until 3 , wherein the variable resistor comprises: a first resistor provided between the wiring and the predetermined node, and a switch provided in parallel with the first resistor, the matching circuit switching the switch as a result of the start of generation of the output voltage turns on and turns off as a result of the predetermined amount of time elapsed from the start of output voltage generation. Power supply circuit according to claim 4 , wherein the variable resistor further includes a second resistor connected in series with the switch, the second resistor having a resistance less than that of the first resistor. Power supply circuit according to claim 5 , wherein the matching circuit comprising: a detection circuit configured to detect whether the predetermined period of time has elapsed from the start of generation of the output voltage; and a control circuit configured to determine a state of the switch based on a To control the detection result of the detection circuit. Power supply circuit according to claim 6 , wherein the detection circuit comprising: a current mirror circuit configured to receive the output voltage and generate a current, a capacitor configured to absorb the current generated by the current mirror circuit, a transistor configured to detecting whether the predetermined period of time has elapsed from the start of generation of the output voltage based on a charging voltage of the capacitor and a predetermined threshold voltage, and a diode provided between a node for obtaining the output voltage and the capacitor. Power supply circuit according to claim 6 , wherein the detection circuit comprising: an integrator circuit comprising a third resistor and a capacitor, the integrator circuit being arranged to integrate the output voltage, a transistor arranged to detect whether the predetermined period of time since the beginning generation of the output voltage has elapsed based on a charging voltage of the capacitor and a predetermined threshold voltage, and a diode provided between a node for receiving the output voltage and the capacitor. Power supply circuit according to one of Claims 1 until 8th wherein the voltage generating circuit includes a zener diode and a plurality of diodes connected in series with the zener diode. Power supply circuit according to one of Claims 1 until 9 wherein the output circuit includes a plurality of Darlington-connected transistors configured to generate the output voltage based on the voltage at the predetermined level. A switching control circuit configured to control switching of a first switching device on a power supply side and a second switching device on a ground side, the first and second switching devices being configured to control a load, the switching control circuit comprising: a signal output circuit configured to output, in response to an input signal thereof, a set signal to turn on the first switching device and a reset signal to turn off the first switching device; a level conversion circuit configured to shift a level of each of the set signal and the reset signal; a drive circuit configured to drive the first switching device in response to an output signal from the level conversion circuit; and a power supply circuit that is set up to generate an output voltage at the level of a desired value from a corresponding input voltage and to provide the output voltage as a power supply voltage of the signal output circuit, the power supply circuit comprising the following: a variable resistor provided between wiring configured to receive the input voltage and a predetermined node, a voltage generating circuit configured to apply a voltage of a predetermined level to the predetermined node based on a current from the variable resistor, an output circuit configured to output the output voltage of the target value when the voltage of the predetermined level is applied to the predetermined node, and an adjustment circuit configured to increase a resistance value of the variable resistor as a result of a predetermined time elapsed from the start of generation of the output voltage.

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