DE112017007753T5 - A METHOD AND SYSTEM FOR CALIBRATING A PHASE NON-LINEARITY OF A DIGITAL-TIME CONVERTER - Google Patents

Abstract

A method for calibrating a phase non-linearity of a digital-time converter is provided. The method includes generating a reference signal based on a control word using a phase locked loop. A frequency of the reference signal is equal to a frequency of an output signal of the digital-time converter. The method further includes measuring a temporal order of a transition of the output signal from a first signal level to a second signal level and a transition of the reference signal from the first signal level to the second signal level. The method additionally includes adapting a first entry of a lookup table based on the measured temporal order.

Description

Territory

The present disclosure relates to the correction of phase non-linearities of digital-time converters ( DTC ). In particular, the present disclosure relates to a method and system for calibrating a phase non-linearity of a DTC .

background

DTCs are used to generate fractional shifted frequencies or modulated signals from a constant reference frequency. For example, you can use it for carrier frequency shifting and phase modulation in digital polar transmitters ( DPTX ), for frequency synthesis in receivers ( RX ) or for digital clock generation in clocking applications.

Some applications (eg digital clock generation) have relaxed specifications, ie they are tolerant of DTC phase non-linearity. In particular, applications for DPTX and RX require highly linear DTCs. Because no attractive or competitive architecture for an ideally linear one DTC is known, the DTC non-linearity is calibrated on-chip and the digital DTC data is predistorted with the information from the DTC calibration.

Several calibration machines have been proposed and implemented. Your main disadvantage is the calibration of a specific DTC operating case (e.g. calibration of the quasi-static DTC programming or calibration of a specific code ramp).

However, the DTC non-linearity changes for different operating modes (e.g. different code ramps or modulation), so that a set of calibration data is not sufficient for all operating modes.

There is thus a need for improved calibration of DTC non-linearities.

Figure list

• 1 stellt ein Flussdiagramm eines Beispiels eines Verfahrens zum Kalibrieren einer Phasen-Nichtlinearität eines DTC dar;
• 2 stellt ein Beispiel eines Systems zum Kalibrieren einer Phasen-Nichtlinearität eines DTC dar;
• 3 stellt ein anderes System zum Kalibrieren einer Phasen-Nichtlinearität eines DTC dar;
• 4 stellt einen Vergleich zwischen idealen und kalibrierten Nachschlagtabelleneinträgen dar;
• 5 stellt einen Vergleich von Fehlern bei Nachschlagtabelleneinträgen für verschiedene Kalibrierparameter dar; und
• 6 stellt ein Beispiel einer mobilen Vorrichtung umfassend einen DTC und eines Systems zum Kalibrieren einer Phasen-Nichtlinearität eines DTC dar.

Some examples of devices and / or methods are described below by way of example only and with reference to the accompanying figures, in which:

• 1 FIG. 14 illustrates a flow diagram of an example of a method for calibrating a phase non-linearity of a DTC dar;
• 2nd provides an example of a system for calibrating a phase non-linearity of a DTC dar;
• 3rd represents another system for calibrating a phase non-linearity of a DTC dar;
• 4th provides a comparison between ideal and calibrated lookup table entries;
• 5 represents a comparison of errors in lookup table entries for different calibration parameters; and
• 6 provides an example of a mobile device including one DTC and a system for calibrating a phase non-linearity of a DTC represents.

Detailed description

Various examples will now be described in more detail with reference to the accompanying drawings, in which some examples are shown. In the figures, the strengths of lines, layers and / or regions may be exaggerated for clarity.

Accordingly, while other examples of various modifications and alternative forms are suitable, some specific examples thereof are shown in the figures and are described in detail below. However, this detailed description does not limit further examples to the particular forms described. Other examples may cover all modifications, equivalents, and alternatives that fall within the scope of the disclosure. Throughout the description of the figures, the same reference numerals refer to the same or similar elements, which when compared with one another can be implemented identically or in a modified form, while providing the same or a similar functionality.

It is understood that when an element is referred to as “connected” or “coupled” to another element, the elements can be connected or coupled directly, or via one or more intermediate elements. If two elements A and B combined using an “or”, this is to be understood as revealing all possible combinations, ie only A , just B such as A and B . An alternative formulation for the same combinations is “at least one of A and B ". The same applies to combinations of more than 2 elements.

The terminology used to describe certain examples is not intended to limit other examples. If a singular form, e.g. For example, "a, one" and "the one that is used" and the use of only a single element is neither explicitly nor implicitly defined as mandatory, other examples can also use plural elements to implement the same function. If a function is described below as being implemented using multiple elements, further examples may implement the same functionality using a single element or processing entity. It is further understood that the terms “comprises”, “comprising”, “has” and / or “having”, when used, specify the presence of the specified features, integers, steps, operations, processes, elements and / or components thereof, but does not exclude the presence or addition of one or more other characteristics, integers, steps, operations, processes, elements, components and / or a group thereof.

Unless otherwise defined, all terms (including technical and scientific terms) are used here in their usual meaning of the area to which the examples belong.

1 provides a flowchart of a method 100 for calibrating a phase non-linearity of a DTC The process 100 involves creating 102 , based on a control word, a reference signal using a phase locked loop (phase locked loop; PLL ). A frequency of the reference signal is (essentially) equal to a frequency of an output signal of the DTC . The method further comprises 100 a measuring 104 a temporal order of a transition of the output signal from a first signal level to a second signal level and a transition of the reference signal from the first signal level to the second signal level. The procedure 100 also includes customization 106 a first entry of a lookup table ( LUT ; Look-Up Table) based on the measured temporal order.

Of the DTC the output signal can be based on the first entry of the LUT produce. The first entry is a first tax code for the DTC assigned, which is based on a control word for controlling a frequency of the output signal.

The procedure 100 can make it possible to compensate for the DTC phase non-linearity by the first entry in the LUT (assigned to the first code word) based on the temporal order of the DTC output signal and the reference signal. Because the procedure 100 It is not a function of the specific time difference between the output signal and the reference signal, but only of the temporal order that a detector with a comparatively low resolution can measure 104 the temporal order of the output signal and the reference signal can be used. In addition, the programming of the DTC cannot be changed during calibration. Accordingly, background calibration can be performed. That is, the DTC can be operated regularly during calibration, so that downtime of a device that the DTC stored, can be avoided. For example, the DTC non-linearity can change after a temperature change. In order to compensate for the temperature-dependent change in the DTC non-linearity, a background calibration can be carried out according to the method 100 be performed.

Of the DTC can receive an oscillating input signal, for example. Based on the control word, a frequency and / or a phase shift of the output signal can be adjusted relative to the oscillating input signal. If the DTC for example, used in a receiver, the output signal can be provided to a mixer circuit which uses the output signal to downconvert a radio frequency received signal. That is, the process 100 may also enable calibration of the specific non-linearity of each RX carrier generated (including both static and dynamic DTC non-linearity).

The first signal level of a signal is a level related to a first logic state, while the second signal level of a signal is a level related to a different second logic state. That is, a signal indicates the first logic state when it is at the first signal level, while the signal indicates the second logic state when the signal is at the second signal level. For example, the first signal level can indicate "1" or "high" and the second signal level can indicate "0" or "low" and vice versa. The signal level can e.g. B. be a voltage of the signal. In some examples, the transition from the first signal level to the second signal level may be a falling signal edge. In other examples, the transition from the first signal level to the second signal level can be a rising signal edge.

The temporal order indicates which of the output signal and the reference signal first switches from the first signal level to the second signal level. For example, a Bang-Bang phase detector ( BBPD ; Bang-Bang Phase Detector) can be used to order the time to eat 104 . The output signal (ie the DTC output) switches either earlier or later than the reference signal depending on the DTC non-linearity for a specific control code. Because the procedure 100 (which can be understood as a calibration machine) does not depend on the measurement of the specific time difference between the two signals, one can BBPD be used. The use of a time-to-digital converter ( TDC ; Time-to-Digital Converter) can be avoided as the higher time resolution of the TDC is not needed. Accordingly, the TDC non-linearity can be avoided as complexity in the calibration machine. In some examples, however, a TDC to measure 104 the temporal order can be used.

The first tax code for the DTC can be part of a continuously increasing or decreasing code sequence (code ramp) that is generated based on the control word. For example, the first and further control codes can be generated by continuously integrating the control word. Accordingly, a series of continuously increasing or decreasing control codes for the DTC be generated.

The LUT can include one entry for each tax code. For example, for N Tax codes for the DTC the LUT N Entries include, each of the N Entries a specific one of the N Tax codes for the DTC assigned. The LUT can initially be filled with any data (e.g. zeros, data from an earlier calibration, random data). The entries in the LUT can be used as the result of predistortion of the control codes for the DTC can be understood to compensate for DTC non-linearity. That is, an entry in the LUT is a customized tax code for the DTC derived from the tax code to which it is assigned. By customizing one of the entries in the LUT can the nonlinearity of the DTC be calibrated for the specific code. For example, the entry in the LUT be incremented or decremented based on the temporal order of the output signal and the reference signal.

Before the first entry in the LUT is calibrated, the reference signal and the output signal can be aligned. Hence the procedure 100 additionally include adjusting a phase of the reference signal to be (substantially) equal to a phase of that DTC generated output signal based on a second entry in the LUT . The second entry is a second control code for the DTC assigned for whom the DTC is phase linear. Of the DTC has no phase non-linearity for all control codes. For one or more control codes of the code sequence, the DTC According to the definition phase linear. These control codes can be used to align the reference signal with the output signal.

In addition to the control word, generation can 102 of the reference signals continue to be based on a frequency control word. Adjusting the phase of the reference signal may then further include measuring, for the second entry, a time shift between a transition of the output signal from the first signal level to the second signal level and a transition of the reference signal from the first signal level to the second signal level. Alternatively, the adaptation of the phase of the reference signal can then further comprise measuring, for the second entry, a third temporal order of a transition of the output signal from a first signal level to the second signal level and the transition of the reference signal from the first signal level to the second signal level. Furthermore, adapting the phase of the reference signal can include generating the frequency control word based on the time shift or the third temporal order. Accordingly, the phase of the reference signal can be set to be equal to the phase of that of the DTC generated output signal is based on the second entry in the LUT , by adjusting the frequency control word. In other words, the reference signal is adapted so that there is no phase shift with respect to the output signal of the DTC has, the output signal of DTC is generated based on a code word for which the DTC is phase linear.

For example, adapting the frequency control word may include calculating a phase error of the reference signal with respect to the output signal based on the time shift or the third temporal order. Furthermore, adapting the frequency control word can include adapting the frequency control word based on the phase error.

The time shift between the third temporal order of the reference signal and the output signal for the second entry in the LUT can be measured by the same or a different circuit arrangement than the temporal order of the reference signal and the output signal for the first entry in the LUT . For example, the time shift between the reference signal and the output signal for the second entry in the LUT using a TDC be measured and the third temporal order of the reference signal and the output signal for the second entry in the LUT can be done using a BBPD be measured.

Alternatively, the output signal of the DTC be calibrated to the reference signal. Then can the procedure 100 further measuring a phase error of the reference signal with respect to a phase of the output signal generated by the DTC , based on a second entry in the LUT include. Furthermore, the method 100 comprise generating a correction code based on the phase offset, the first control code further being based on the correction code. That is, the control codes of the code sequence can be adjusted based on the correction code. For example, the control codes of the code sequence can be incremented or decremented by the correction code in order to adapt the phase of the DTC output signal to the phase of the reference signal. Accordingly, a phase of the DTC output signal for code words of the code sequence for which the DTC is phase linear, be equal to the phase of the reference signal.

The above measurement of the temporal order to calibrate the first entry in the LUT a predetermined number of times can be performed so that a predetermined number of temporal orders is measured. Accordingly, the adaptation of the first entry can be based on the predetermined number of temporal orders. For example, a BBPD used to measure the temporal order and a PLL used with a comparatively high jitter to generate the reference signal, the measured temporal orders can be averaged in order to achieve a high calibration accuracy. For example, the temporal order can be measured 16 times or more, 64 times or more, 256 times or more, 1024 times or more or 4096 times or more. In some examples, at least part of the predetermined number of temporal orders can be measured in parallel. Accordingly, a calibration time can be reduced by the multiple simultaneous measurements of the temporal order.

Adjusting the first entry based on the predetermined number of time orders may e.g. B. deriving an indicator value from the predetermined number of temporal orders, which indicates whether the transition of the output signal from the first signal level to the second signal level or the transition of the reference signal from the first signal level to the second signal level more often than the predetermined one Number of temporal orders precedes. For example, a counter can be used to derive the indicator value. The counter can e.g. be increased if the output signal precedes the reference signal and decreased if the reference signal precedes the output signal. Accordingly, a counter value greater than zero indicates that the transition of the output signal from the first signal level to the second signal level more often precedes the transition of the reference signal from the first signal level to the second signal level under the predetermined number of time orders, and vice versa. Adjusting the first entry based on the predetermined number of temporal orders may then further include adjusting the first entry based on the indicator value.

In some examples, the first entry can only be adjusted if the absolute value of the indicator value is greater than a threshold value. The threshold can allow the first entry in the LUT only to be calibrated if it has not yet been calibrated with sufficient accuracy. That is, the adjustment of the first entry in the LUT can be omitted if the first entry has already been calibrated with sufficient accuracy. The desired level of accuracy can be adjusted by selecting the threshold.

The calibration of the entries in the LUT can be done iteratively in some examples. For example, measuring the predetermined number of time orders and adjusting the first entry based on the predetermined number of time orders can be performed iteratively. Through the iterative calibration of the entries in the LUT high calibration accuracy can be achieved.

As indicated above, the DTC not limited to the output signal based on the first entry in the LUT to generate, which is assigned to a first control code of the code sequence. Of the DTC can the output signal based on further entries in the LUT generate, with the further entries further control codes for the DTC (ie other control codes of the code sequence) are assigned. The procedure 100 can thus also have the measurement for the further entries, a respective temporal order of the transition of the output signal from the first signal level to the second signal level and the transition of the reference signal from the first signal level to the second signal level. The procedure can also 100 further include adapting the further entries based on the respective chronological order. Accordingly, all entries in the LUT can be adjusted to compensate for the DTC non-linearity on the control codes of the code sequence.

The calibration can be carried out iteratively. That is, the measurement of the respective temporal order for the further entries can be carried out a predetermined number of times, so that a corresponding predetermined number of temporal orders is measured for each of the further entries, and the adaptation of the further entries is based on the respective one predetermined number of time orders. Thus, for the other entries in the LUT high calibration accuracy can be achieved.

In some examples, measuring the respective predetermined number of time orders for the first and subsequent entries of the LUT and adapting the first and the further entries iteratively until a maximum number of iterations is reached or until each of the first and the further entries fulfills a quality criterion. The maximum number of iterations is a hard termination criterion. The quality criterion can be any quantity that indicates a desired accuracy of the calibration of the LUT entries. The quality criterion can be, for example, that the respective indicator value for each LUT entry is less than the threshold value. Accordingly, a number of iterations that are required to achieve the quality criterion for all entries can be smaller than the maximum number of iterations.

In the above examples, the calibration of an entry in the LUT only the temporal order used in relation to one type of signal edge. The procedure 100 can, however, use other signal edges, ie falling and rising edges. In some examples, the method 100 thus further comprising measuring, for the first entry, a second temporal order of a transition of the output signal from the second signal level to the first signal level, and a corresponding transition of the reference signal from the second signal level to the first signal level. The adaptation of the first entry can then also be based on the second chronological order. Accordingly, for the other entries in the LUT the respective second time orders are measured and the further LUT entries are adjusted on the basis of the respective second time orders. Like the first time orders, the second time orders can be measured a predetermined number of times (ie, multiple times) as described above.

The LUT entries can be adjusted in different ways. For example, customizing 106 of the first entry include incrementing or decrementing the first entry based on the first temporal order. For example, the first entry can be incremented when the output signal of the DTC precedes the reference signal and vice versa.

Instead of that LUT To fill incrementally, other approaches such as a binary search can also be used. For example, iteratively adjusting the first entry, as mentioned above, may include incrementing or decrementing the first entry in the first iteration by a first value based on the predetermined number of temporal orders of the first iteration. Furthermore, iteratively adjusting the first entry may include incrementing or decrementing the first entry in the second iteration by a second value based on the predetermined number of temporal orders of the second iteration, the second value being (substantially) half of the first value . That means, for each iteration n (eg iteration n from the total N iterations) the first entry in the LUT incremented or decremented by a value that is 2- ^(n-1) times the first value (ie, the value of the first iteration) based on the temporal order of the output signal and the reference signal for the nth iteration. This can allow a defined calibration time and reduce the required calibration iterations compared to the incremental approach above.

Below are various examples of how to implement the method 100 discussed. 2nd represents a system 200 for calibrating a phase non-linearity of a DTC 210 The system 200 includes one PLL 230 that is configured to based on the control word 205 a reference signal 231 to create. A frequency of the reference signal 231 is (essentially) equal to a frequency of an output signal 211 of DTC 210 . The system also includes a detection circuit 240 , which is configured to a temporal order of a transition of the output signal 211 from a first signal level to a second signal level and a transition of the reference signal 231 to measure from the first signal level to the second signal level. A processing circuit 250 of the system 200 is trained to make a first entry 221 one LUT 220 based on the measured temporal order.

Of the DTC can the output signal 211 based on the first entry 221 of the LUT 220 produce. The first entry 211 is a first tax code for the DTC 210 assigned to that on a control word 205 for controlling a frequency of the output signal 211 based.

Like the procedure 100 can the system 200 allow the first entry 221 of the LUT to calibrate without programming the DTC 210 change during calibration. A background calibration can be carried out accordingly (eg after a temperature change). Furthermore, since the adjustment of the first entry 221 also not by the specific time difference between the output signal 211 and the reference signal 231 depends, but only on the temporal order, the detection circuit 240 just one provide comparatively low time resolution. For example, the detection circuit 240 a BBPD be.

Before the first entry 221 the system can be configured 200 the reference signal 231 and the DTC output signal 211 align. For example, the PLL 230 be designed to adapt a phase of the reference signal 231 so that it (essentially) equals a phase of the output signal 211 is generated by that DTC , based on a second entry in the LUT 220 . The second entry is a second control code for the DTC 210 assigned for whom the DTC 210 is phase linear.

The PLL 230 can, for example, also be designed to generate the reference signal 231 further based on a frequency control word. That is, the PLL 230 can the reference signal 231 based on the control word 205 and generate the frequency control word. Furthermore, the detection circuit 240 (e.g. implemented as TDC ) also be designed for measuring, for the second LUT Entry, a time shift between a transition of the output signal 211 from the first signal level to the second signal level and a transition of the reference signal 231 from the first signal level to the second signal level. Alternatively, the detection circuit 240 (e.g. implemented as BBPD ) can also be designed for a third temporal order of the transition of the output signal for the second LUT entry 211 from the first signal level to the second signal level and the transition of the reference signal 231 to measure from the first signal level to the second signal level.

The system may further include a conversion circuit (not shown) configured to generate the frequency control word based on the time shift or the third order in time.

For example, the conversion circuit can be designed to calculate a phase error of the reference signal 231 in relation to the output signal 211 based on the time shift or the third temporal order. Furthermore, the conversion circuit can be designed to adapt the frequency control word based on the phase error.

In some examples, the system 200 additionally include a filter (not shown) connected between the detection circuit 240 and the conversion circuit is coupled. The filter can be designed to receive only filtered data from the detection circuit 240 to the conversion circuit when a control signal input to the filter indicates that the DTC 210 the output signal based on an entry in the LUT 220 generates a control code for the DTC 210 for which the DTC 210 is phase linear. That is, the filter routes data from the detection circuit 240 to the conversion circuit when the DTC the output signal based on the second entry in the LUT generates but does not pass data from the detection circuit 240 to the conversion circuit when the DTC the output signal based on the first entry in the LUT generated. Accordingly, the filter can ensure that the frequency control word is only adjusted if the DTC generates the output signal based on a control word for which the DTC 210 (by definition) is phase linear.

As indicated above, the detection circuit can 240 a BBPD be. In addition, the PLL 230 have a comparatively high jitter (e.g. the PLL 230 be without inductance). This can affect the accuracy of the measured temporal order. In order to achieve high calibration accuracy, several temporal orders can be measured and averaged. Therefore, the detection circuit 240 be further configured to measure the temporal order a predetermined number of times, so that a predetermined number of temporal orders is measured. Furthermore, the processing circuit 250 further be trained to the first entry 221 based on the predetermined number of temporal orders.

For example, the detection circuit can also be designed to measure at least part of the predetermined number of temporal orders in parallel. The detection circuit 250 can therefore comprise a plurality of measuring cells. For example, each of the measuring cells can be designed to measure the temporal order of the output signal and the reference signal. Accordingly, the temporal order can be measured simultaneously. For example, the detection circuit 240 have a plurality of BBPD cells.

The processing circuit can be used to process the many temporal orders 250 be further configured to derive an indicator value from the predetermined number of temporal orders, which indicates whether the transition of the output signal 211 from the first signal level to the second signal level or the transition of the reference signal 231 from the first signal level to the second signal level the other more often precedes the predetermined number of time orders. Furthermore, the processing circuit 250 be trained to the first entry 221 based on the indicator value. For example, a counter for deriving the Indicator value by the processing circuit 250 be carried out.

In some examples, the processing circuitry 250 further be trained to the first entry 221 only to be adjusted if the absolute value of the indicator value is greater than a threshold value. The threshold can allow the first entry in the LUT only to be calibrated if it has not yet been calibrated with sufficient accuracy. The desired level of accuracy can be adjusted by selecting the threshold.

Like the procedure 100 can the system 200 be trained to the first entry 221 in the LUT 220 calibrate iteratively. For example, the system 200 be designed to the detection circuit 240 to control to iteratively measure the predetermined number of temporal orders. The system 200 can also be configured to the processing circuit 250 to control the first entry 221 iteratively adjust based on the predetermined number of temporal orders.

The system 200 however, it is not limited to the calibration of the first entry 221 in the LUT . As explained above, the DTC 210 the output signal based on further entries in the LUT 220 produce. The other entries are additional tax codes for the DTC 210 assigned. Therefore, the detection circuit 240 furthermore be formed in order for the further entries a respective temporal order of the transition of the output signal 211 from the first signal level to the second signal level and the transition of the reference signal 231 to measure from the first signal level to the second signal level. Accordingly, the processing circuit 250 further be trained to the other entries in the LUT 220 adapt based on the respective temporal order.

Like the first entry 221 in the LUT 220 can the detection circuit 240 be further configured to measure the respective temporal order for the further entries a predetermined number of times, so that a corresponding predetermined number of temporal orders is measured for each of the further entries. Similarly, the processing circuit 250 further be trained to the other entries in the LUT 220 based on the respective predetermined number of temporal orders. Accordingly, the entries in the LUT 220 high calibration accuracy can be achieved.

The calibration can also be carried out iteratively for the other entries. That is, the system 200 can be designed to the detection circuit 240 to control the respective predetermined number of temporal orders for the first and the further entries of the LUT 220 measure iteratively. The system can also 200 be designed to the processing circuit 250 to control the first and further entries in the LUT 220 adjust iteratively until a maximum number of iterations is reached or each of the first and further entries in the LUT 220 fulfills a quality criterion. The quality criterion can be any quantity that indicates a desired accuracy of the calibration of the LUT entries. The quality criterion can be, for example, that for each LUT entry the respective absolute value of the indicator value is less than the threshold value. Accordingly, a number of iterations required to achieve the quality criterion for all entries can be less than the maximum number of iterations.

In the examples above, the system 200 trained to adjust the LUT entries based on only one type of signal edge. The system 200 However, it can also be designed to use more signal edges, ie rising and falling signal edges. Therefore, the detection circuit 240 in some examples, be further trained to for the first entry 221 a second temporal order of a transition of the output signal 211 from the second signal level to the first signal level and a corresponding transition of the reference signal 231 to measure from the second signal level to the first signal level. Accordingly, the processing circuit 250 further be trained to the first entry 221 in the LUT 220 further adapt based on the second temporal order. Also for the other entries in the LUT 220 can the detection circuit 240 be configured to measure one or more corresponding second temporal orders, and the processing circuit 250 can be designed to the respective entry in the LUT 220 adapt based on the one or more measured second temporal orders.

As above in connection with the method 100 has been explained, the entries in the LUT 220 be adjusted in a plurality of ways based on the one or more measured temporal orders. For example, the processing circuit 250 further be trained to the first entry 221 by incrementing or decrementing the first entry 221 based on the first temporal order.

Furthermore, the processing circuit 250 further be trained to the first entry 211 based on a binary search iteratively adapt. That is, for each iteration n (eg iteration n from the total N iterations) the processing circuit can 250 be configured to increment or decrement by a value that is 2- ^(n-1) times the value of the first iteration, based on the temporal order of the output signal and the reference signal for the nth iteration. For example, the processing circuit 250 be further configured to increment or decrement the first entry 221 in the first iteration by a first value based on the predetermined number of temporal orders of the first iteration, and for incrementing or decrementing the first entry 221 in the second iteration by a second value based on the predetermined number of temporal orders of the second iteration. The second value is (essentially) half of the first value. This can allow a defined calibration time and reduce the required calibration iterations compared to the incremental approach above.

3rd represents another system 300 for calibrating a phase non-linearity of a DTC 210 In the 3rd the example shown is the DTC 210 Part of a recipient. Of the DTC 210 delivers its output signal 211 to a mixer circuit (not shown) of the receiver that receives a radio frequency signal using the output signal 211 down converted.

The system 300 comprises the circuitry used to generate the RX signal (ie the output signal 211 ) is required for the mixing circuit. RX generation includes one RX PLL 275 for generating the oscillating input signal 276 for the DTC 210 (ie a reference local oscillator signal). RX generation also includes DTC 210 with (based on) a control code n ∈ [0, N] (with max. DTC control code N ) to generate the desired RX frequency f _{DTC, out} is programmed. RX generation also includes one LUT 220 to correct DTC non-linearity. The LUT 220 includes one entry for each tax code. Every entry in the LUT 220 is based on the assigned control code and is adjusted based on the DTC non-linearity for the respective control code (ie the entries in the LUT 220 can be used as predistorted control codes for the DTC 210 can be understood to take DTC non-linearity into account). In addition, the RX generation includes a control circuit 260 (e.g. implemented as a digital part) for generating an RX control code sequence (control code ramp) 290 by integrating a control word (FCW) 205 to control the frequency f _{DTC, out} of the output signal 211 .

The calibration machine adds the (calibration) PLL 230 for generating a reference signal 231 at the same frequency as the output signal 211 of DTC 210 added, ie f _{RX, ideal} = f _{DTC, out} . The calibration PLL 230 uses the same FCW 205 , from which the DTC programming is derived. That is, the reference signal 231 is based on the control word 205 . f _{DTC, out} can have the ideal output frequency at the output of the DTC 210 is desired, but is distorted by the DTC non-linearity. In addition, the RX PLL 275 and the calibration PLL 230 the same reference frequency fref for generating the oscillating input signal 276 for the DTC 210 and the reference signal 231 based on the reference frequency fref.

The DTC output signal 211 and the reference signal 231 have an identical frequency, but their phase is initially not aligned. To determine their phase, compare one BBPD 240 which serves as a detection circuit f _{RX, ideal} and f _{DTC, out} . In the closed calibration DTC-PLL control loop, consisting of BBPD 240 , (Loop) filter (LF; loop filter) 270 and differentiator 280 (Serving as a conversion circuit for converting the phase error into a frequency for programming the calibration PLL 230 ), the phase error between the output signal 211 and the reference signal 231 reduced to zero.

However, only DTC edges (ie signal edges of the output signal 211 ) for control codes with zero integrated non-linearity (INL), ie control codes in which the DTC 210 is phase linear (eg by definition control code n = 0, which is the 0 ° phase reference of the output signal 211 is) used to phase the calibration PLL 230 on the DTC 210 ascertain.

The calibration PLL 230 may have poor signal quality. For example, the PLL 230 Be inductance-free or based on a ring oscillator.

The aim of the first step is to eliminate all phase offsets between the PLL 230 and the DTC 210 , ie every phase offset between the reference signal 231 and the output signal 211 to calibrate. Of the DTC 210 generates the output signal 211 (RX signal) according to an RX code ramp (sequence). The LUT can be filled with any data (zeros, data from previous calibrations, random data). The calibration can be initialized according to the following algorithm.

First the DTC-PLL control loop is opened. Then the calibration PLL 230 found on f _{RX, ideal} = f _{DTC, out} . That is, the frequency of the reference signal 231 is based on the frequency of the output signal 211 customized. Now the DTC-PLL control loop is closed. The LF 270 the DTC-PLL is only fed with data for DTC control codes with inherently zero INL (e.g. code n = 0 has by definition zero INL). The processing circuit 250 (ie the calibration machine) shows the LF 270 which entries are to be processed. That is, the filter 270 is trained to only read data from that BBPD 240 to process and the filtered data to the differentiator 280 forward when a control signal 251 that in the filter 270 is entered indicates that the (currently) measured edge of the DTC output signal 211 on an entry in the LUT 220 based on a tax code for the DTC 210 for which the DTC 210 is phase linear. The differentiator 280 converts the phase error into a frequency for programming the calibration PLL 230 around. In particular, the differentiator generates 280 a frequency control word for the calibration PLL 230 . The frequency control word is with the FCW 205 combined to create a control word for the calibration PLL 230 to create. The above processing can be repeated iteratively throughout the calibration process.

Since the DTC-PLL loop only works with the DTC codes with (by definition) ideal linearity, it is not affected by the LUT programming. Now the calibration algorithm can be started.

Each rising and / or falling DTC output signal is from the BBPD 240 compared to the ideal RX signal, which is phase detection at a rate of f _{DTC, out} allowed. The programmed DTC control code of the calibration machine is known for each measured edge (for example, the processing circuit 250 him out of the LUT 220 read). For example, if the measured DTC edge (ie the output signal 211 ) a positive time offset compared to the edge of the reference signal 231 has, the DTC 210 a positive non-linearity for the specific code. If so, the LUT entry is at that position by the processing circuitry 250 decremented. Conversely, in the event of a negative time offset, the LUT entry is incremented by the processing circuit.

1. 1) Messen, ob das ansteigende DTC-Ausgangssignal 211 oder das ansteigende ideale RX-Signal 231 zuerst ist. Das DTC-Signal 211 führt zunächst zu ‚-1‘ an dem BBPD-Ausgang 240, das RX-Signal 231 führt zunächst zu ‚1‘. Das DTC-Ausgangssignal 211 wird für einen ersten DTC-Steuercode n erzeugt (d.h. basierend auf einem ersten Eintrag in der LUT 220, der dem ersten Steuercode zugeordnet ist).
2. 2) Entsprechendes Programmieren der LUT:
   1. a. Wenn die BBPD 240 -Ausgabe ‚-1‘ ist: Inkrementieren des LUT-Eintrags bei Code n.
   2. b. Wenn die BBPD 240 -Ausgabe ‚1‘ ist: Dekrementieren des LUT-Eintrags bei Code n. 3) Gehen zu 1) und messen der nächsten DTC-Ausgangssignalflanke.

For example, the calibration can be implemented by:

1. 1) Measure whether the rising DTC output signal 211 or the rising ideal RX signal 231 is first. The DTC signal 211 initially leads to '-1' at the BBPD output 240 , the RX signal 231 initially leads to '1'. The DTC output signal 211 is generated for a first DTC control code n (ie based on a first entry in the LUT 220 assigned to the first control code).
2. 2) Programming the LUT accordingly:
   1. a. If the BBPD 240 - Output '-1' is: increment the LUT entry for code n.
   2. b. If the BBPD 240 -Output '1' is: Decrement the LUT entry for code n. 3) Go to 1) and measure the next DTC output signal edge.

Due to the required high calibration accuracy and the potentially high jitter of the calibration PLL 230 the measurements can be averaged. This can be done, for example, by measuring and storing several values per control code using the BBPD 240 -Output signal is accumulated in a counter within the digital part of the calibration machine (ie the processing circuit 250 performs a counting operation). After a desired averaging, the counter value can be evaluated and the LUT 220 be programmed accordingly. As indicated above, thresholds for the counter can be used to define a stop criterion for the calibration. For example, if an (essentially) equal number of measuring points for the same code has a positive and negative time offset to the reference (ie the counter is zero or almost zero), the calibration for this code can be stopped because it is ideally calibrated. If the DTC RX sequence 290 If a random dither is added, it can be averaged in the same way.

• 1) Definieren eines Mittelungsfaktors A, der bestimmt, wie viele Messungen gemittelt werden (d.h. A definiert die Genauigkeit). Weiterhin wird die maximale Anzahl der Iterationen definiert I_max .
• 2) Einstellen des Iterationszählers auf i = 0.
• 3) Einstellen des Mittelungszählers auf a = 0.
• 4) Messen, ob das ansteigende DTC-Ausgangssignal 211 oder das ansteigende ideale RX-Signal 231 zuerst ist. Der DTC-Ausgang 211 führt zunächst zu ‚-1‘ am BBPD 240 -Ausgang, wobei das RX-Signal 231 zunächst zu ‚1‘ führt. Mit Kenntnisnahme des aktiven DTC-Steuercodes n.
• 5) Programmierung des internen Kalibrierzählers c[n]:
  • a. Wenn die BBPD -Ausgabe ‚-1‘ ist: Inkrementieren des Zählers c[n]
  • b. Wenn die BBPD-Ausgabe ‚1‘ ist: Dekrementieren des Zählers c[n]
• 6) Inkrementieren des Mittelungszählers a.
• 7) Bei a = A - N gehe zu 8), ansonsten gehe zu 4) und Messen des nachfolgenden ansteigenden DTC-Ausgangssignals 211.
• 8): ∀n ∈ [0,N] Inkrementieren des entsprechenden LUT-Eintrags wenn c[n] > c_thres, Dekrementieren des entsprechenden LUT-Eintrags wenn c[n] < -c_thres, oder Markieren des Kontrollcodes n als kalibriert wenn -c_thres ≤ c[n] ≤ c_thres.
• 9) Erhöhen des Iterationszählers i.
• 10) Wenn der Steuercode n als kalibriert markiert ist, ∀n ∈ [0, N] ODER i = I_max gehe zu 11), andernfalls gehe zu 3).
• 11) Kalibrierung stoppen.

For example, for each DTC control code (ie for each entry in the LUT 220 ) a number of A Measurements performed, and the output of the BBPD 240 is summarized in a counter c [n] (ie one counter is used for each of the N + 1 DTC control codes to speed up the calibration). If the majority of the measured edges at the output of the BBPD 240 '-1' indicates the corresponding LUT value is incremented, otherwise it is processed by the processing circuit 250 decremented. A counter threshold c _thres can indicate whether the calibration has been completed with sufficient accuracy. A maximum number of iterations I _max is further defined to be a hard termination criterion. The complete algorithm (procedure) can look like this:

• 1) Define an averaging factor A , which determines how many measurements are averaged (i.e. A defines the accuracy). The maximum number of iterations is also defined I _max .
• 2) Set the iteration counter to i = 0.
• 3) Set the averaging counter to a = 0.
• 4) Measure whether the rising DTC output signal 211 or the rising ideal RX signal 231 is first. The DTC output 211 leads first to '-1' on BBPD 240 -Output, the RX signal 231 first leads to '1'. With knowledge of the active DTC control code n.
• 5) Programming the internal calibration counter c [n]:
  • a. If the BBPD output is '-1': increment the counter c [n]
  • b. If the BBPD output is '1': decrement the counter c [n]
• 6) increment the averaging counter a.
• 7) At a = A - N go to 8), otherwise go to 4) and measure the subsequent rising DTC output signal 211 .
• 8): ∀n ∈ [0, N] increment the corresponding LUT entry if c [n]> c _thres , decrement the corresponding LUT entry if c [n] <-c _thres , or mark the control _code n as calibrated if -c _thres ≤ c [n] ≤ c _thres .
• 9) Increase the iteration counter i.
• 10) If the control code n is marked as calibrated, ∀n ∈ [0, N] OR i = I _max go to 11), otherwise go to 3).
• 11) Stop calibration.

As indicated above, the above rising edge calibration can be changed to a falling edge or a double edge calibration. Instead of that LUT to fill incrementally, other algorithms, such as a binary search, can also be used. A binary search can allow a defined calibration time and further reduce the number of calibration iterations required. With a binary search, the stop criteria (quality criteria) of the algorithm can be adjusted accordingly.

The implementation of the BBPD 240 can be of any complexity. As already mentioned, several parallel BBPD cells can be used to reduce the influence of mismatches, to increase the accuracy and to shorten the calibration time by several simultaneous measurements.

In other words, 3rd can illustrate a calibration machine that relates to the RX DTC operations concentrated. An eg inductance-free calibration PLL 230 generates an ideal RX signal 231 , and the DTC edition 211 is with a BBPD 240 compared for that. The LUT 220 of DTC 210 is then filled incrementally with calibration data, for example, until an accuracy threshold between the ideal RX and DTC-generated RX signal is reached. The architecture of the calibration machine enables it to be recalibrated if necessary during DTC operation.

As indicated above, an inductance-less calibration PLL 230 used to the reference signal f _{RX, ideal} for the RX-DTC calibration, the reference signal being determined on the DTC output phase. The two signals 1) DTC output signal at f _{DTC, out} (generated by RX control code ramp) and 2) calibration PLL signal at f _{RX, ideal} can with BBPD 240 can be compared to extract the direction of DTC non-linearity compared to the ideal RX signal. Compared to other detection circuits like one TDC can he BBPD up to the rate of the oscillating input signal 276 for the DTC run and thus reduce the calibration time. The LUT 220 can be filled incrementally based on the extracted information. The averaging of the measurements can be used to increase the resolution and the influence of DTC and reduce calibration PLL jitter.

The accuracy of the proposed calibration scheme can be seen from the explanation of the 4th and 5 be obvious. 4th represents a comparison between ideal and calibrated lookup table entries. The abscissa denotes the control code for the DTC and the ordinate denotes the entry in the LUT for the respective tax code.

The round dots 410 show the ideal entries for the control codes, ie the entry assigned to each control code for the best compensation of the DTC non-linearity on the respective control code.

The diamond-shaped data points 420 show the entries of the LUT after a defined number of calibration iterations according to the proposed concept. For the diamond-shaped data points 420 became a first number A ₁ temporal order measured and averaged for each iteration.

The square data points 430 show the entries of the LUT according to the defined number of calibration iterations according to the proposed concept. For the quadratic data points 420 became a second number A ₂ temporal order measured and averaged for each iteration. A ₂ is bigger than A ₁ .

Out it can be seen that the accuracy of the calibration is better for a larger number of averaged measurements.

5 also represents a comparison of LUT entry errors for different calibration parameters. The abscissa gives the number of measured and averaged temporal orders. The ordinate denotes the average (eg root mean square, RMS; square mean) error of the LUT entries compared to the ideal LUT entries. The data points 510 denote the error of the LUT entries for a first jitter y der PLL used to generate the reference signal. The data points 520 denote the error of the LUT entries for a second jitter 3 · y PLL (ie the second jitter is three times the first jitter). The data points 530 denote the error of the LUT entries for a third jitter 5 y the PLL . The data points 540 denote the error of the LUT entries for a fourth jitter 7 y PLL . The data points 550 denote the error of the LUT entries for a fifth jitter 9 · y PLL .

Out again it can be seen that the accuracy of the calibration is better for a larger number of averaged measurements. Furthermore is off 5 it can be seen that the accuracy of the calibration is better if the jitter of the calibration PLL used to generate the reference signal is lower. To the LUT To calibrate with a desired accuracy, a compromise can be made between the jitter of the calibration PLL and the number of averaged temporal orders (ie the runtime of the calibration).

In general, some examples presented herein relate to a means for calibrating a phase non-linearity DTC . The means comprises means for generating a reference signal based on a control word using a PLL , wherein a frequency of the reference signal is equal to a frequency of an output signal of the DTC is. The means further comprises means for measuring a temporal order of a transition of the output signal from a first signal level to a second signal level and a transition of the reference signal from the first signal level to the second signal level. In addition, the means comprises means for adapting a first entry one LUT based on the measured temporal order.

Of the DTC the output signal can be based on the first entry of the LUT generate, the first entry a first control code for the DTC is assigned, which is based on the control word for controlling the frequency of the output signal.

In some examples, the means for generating the reference signal may further be configured to adjust a phase of the reference signal to be equal to a phase of the DTC generated output signal based on a second entry in the LUT , the second entry being a second control code for the DTC for which the DTC (by definition) is phase linear.

The means for calibrating a phase non-linearity of a DTC can be achieved by a system for calibrating a phase non-linearity of a DTC implemented as described above or below (for example 2nd ). The means for generating the reference signal can by a PLL implemented as described above or below (for example 2nd ). The means for measuring a temporal order can be implemented by a detection circuit which is described above or below (eg 2nd ). The means for adapting the first entry can be implemented by a processing circuit described above or below (for example 2nd ).

An example of an implementation involving a system for calibrating a phase non-linearity of a DTC used in accordance with one or more aspects of the proposed architecture or one or more examples described above is in 6 shown. 6 schematically illustrates an example of a mobile device 600 (e.g. a cell phone, smartphone, tablet computer or laptop), some DTC 610 comprising a radio frequency output signal based on entries in one LUT 620 generated. The mobile device 600 also includes a system 630 for calibrating a phase non-linearity of a DTC according to an example described herein.

For example, a recipient 670 the DTC 610 , the LUT 620 and the system 630 include.

For this purpose, a mobile device 600 be provided, which enables the completely digital generation of receiving media. Accordingly, a number of on-chip inductors can be reduced, so that a chip area can be reduced and crosstalk problems can be alleviated.

The recipient 670 may have one or more additional components. For example, the recipient includes 670 possibly a control circuit 640 , which is designed to generate a continuously increasing or decreasing code sequence based on the control word, the first control code for the DTC 610 Is part of the code sequence. The recipient 670 can also be a PLL 650 comprise, which is designed to an oscillating input signal for the DTC 610 to create. Furthermore, the recipient 670 a mixed circuit 660 which is configured to receive a radio frequency signal using the output signal of the DTC 610 to walk down.

For example, the recipient 670 be designed to work according to one of the 3GPP standardized mobile communication networks or systems. The mobile or wireless communication system can e.g. B. a long-term development (LTE-; LTE = Long Term Evolution), an advanced LTE- (LTE-A-; LTE-A- = LTE-Advanced), high-speed packet access (HSPA-; HSPA = High Speed Packet Access ), a universal mobile telecommunications system (UMTS system; UMTS = Universal Mobile Telecommunication) or a UMTS terrestrial radio access network (UTRAN; UTRAN = UMTS Terrestrial Radio Access Network), a developed UTRAN (e-UTRAN; e-UTRAN = evolved UTRAN), a global system for mobile communication (Global System for Mobile Communication = GSM) or increased data rates for GSM further development network (EDGE network; EDGE = Enhanced Data rates for GSM Evolution), a GSM / EDGE radio access network ( GSM EDGE Radio Access Network = GERAN), or mobile communication networks with different standards, e.g. B. A network for worldwide interoperability for microwave access (WIMAX network; WIMAX = Worldwide Interoperability for Microwave Access) IEEE 802.16 or wireless local area network (WLAN; WLAN = Wireless Local Area Network) IEEE 802.11, generally an orthogonal frequency division multiple access network (OFDMA -Network; OFDMA = Orthogonal Frequency Division Multiple Access), a time division multiple access network (TDMA network; TDMA = Time Division Multiple Access), a code division multiple access network (CDMA network; CDMA = Code Division Multiple Access), a broadband CDMA Network (WCDMA network; WCDMA = wideband CDMA), a frequency division multiple access network (FDMA network; FDMA = frequency division multiple access), a spatial multiplex access network (SDMA network; SDMA = spatial division multiple access) etc. .

At least one antenna element 680 the mobile device 600 can with the recipient 670 be coupled.

• Beispiel 1 ist ein Verfahren zum Kalibrieren einer Phasen-Nichtlinearität eines Digital-Zeit-Wandlers, umfassend: Erzeugen eines Referenzsignals basierend auf einem Steuerwort unter Verwendung einer Phasenregelschleife, wobei eine Frequenz des Referenzsignals im Wesentlichen gleich einer Frequenz eines Ausgangssignals des Digital-Zeit-Wandlers ist; Messen einer zeitlichen Ordnung eines Übergangs des Ausgangssignals von einem ersten Signalpegel zu einem zweiten Signalpegel und eines Übergangs des Referenzsignals von dem ersten Signalpegel zu dem zweiten Signalpegel; und Anpassen eines ersten Eintrags einer Nachschlagtabelle basierend auf der gemessenen zeitlichen Ordnung.

The examples as described herein can be summarized as follows:

• Example 1 is a method for calibrating a phase non-linearity of a digital-to-time converter, comprising: generating a reference signal based on a control word using a phase-locked loop, wherein a frequency of the reference signal is substantially equal to a frequency of an output signal of the digital-to-time converter is; Measuring a temporal order of a transition of the output signal from a first signal level to a second signal level and a transition of the reference signal from the first signal level to the second signal level; and adjusting a first entry of a lookup table based on the measured temporal order.

In Example 2, in the method of Example 1, the digital-to-time converter generates the output signal based on the first entry of the look-up table, the first entry being associated with a first control code for the digital-to-time converter that is based on the control word for controlling the Frequency of the output signal based.

In example 3, the method of example 1 or example 2 further comprises: adjusting a phase of the reference signal to be substantially equal to a phase of the output signal generated by the digital-time converter based on a second entry in the look-up table, the second Entry is assigned a second control code for the digital-time converter, for which the digital-time converter is phase-linear.

In Example 4, generating the reference signal in the method of Example 3 is also based on a frequency control word, and adjusting the phase of the reference signal includes: measuring, for the second entry, a time shift between a transition of the output signal from the first signal level to the second signal level and a transition of the reference signal from the first signal level to the second signal level; and generating the frequency control word based on the time shift.

In Example 5, adjusting the frequency control word in the method of Example 4 includes: calculating a phase error of the reference signal with respect to the output signal based on the time shift; and adjusting the frequency control word based on the phase error.

In Example 6, generating the reference signal in the method of Example 3 is further based on a frequency control word, and adjusting the phase of the reference signal includes: measuring, for the second entry, a third temporal order of a transition of the output signal from the first signal level to the second Signal level and a transition of the reference signal from the first signal level to the second signal level; and generating the frequency control word based on the third temporal order.

In Example 7, adjusting the frequency control word in the method of Example 6 includes: calculating a phase error of the reference signal with respect to the output signal based on the third temporal order; and Adjust the frequency control word based on the phase error.

In example 8, the method of example 2 further comprises: measuring a phase error of the reference signal with respect to a phase of the output signal generated by the digital-time converter based on a second entry in the look-up table, the second entry being a second control code for the digital Is assigned time converter for which the digital time converter is phase linear; and generating a correction code based on the phase offset, wherein the first control code is further based on the correction code.

In Example 9, measuring the temporal order in the method of one of the previous examples includes measuring a predetermined number of temporal orders, the adjustment of the first entry being based on the predetermined number of temporal orders.

In example 10, at least part of the predetermined number of temporal orders is measured in parallel in the method of example 9.

In Example 11, adjusting the first entry based on the predetermined number of time orders in the method of Example 9 or Example 10 includes deriving an indicator value from the predetermined number of time orders that indicates whether the transition of the output signal from the first signal level to the second signal level or the transition of the reference signal from the first signal level to the second signal level is more often preceded by the other under the predetermined number of temporal orders; and adjusting the first entry based on the indicator value.

In example 12, the first entry in the method of example 11 is only adjusted if the absolute value of the indicator value is greater than a threshold value.

In Example 13, measuring the predetermined number of orders and adjusting the first entry based on the predetermined number of orders are performed iteratively in the method of any of Examples 9-12.

In example 14, the digital-to-time converter in the method of example 13 generates the output signal based on further entries in the look-up table, the further entries being assigned to further control codes for the digital-to-time converter, the method further comprising: measuring, for the further entries, a respective temporal order of the transition of the output signal from the first signal level to the second signal level and the transition of the reference signal from the first signal level to the second signal level; and adapting the further entries based on the respective chronological order.

In Example 15, the measurement of the respective temporal order for the further entries is carried out a predetermined number of times in the method of Example 14, so that a corresponding predetermined number of temporal orders is measured for each of the further entries, the adjustment of the further entries based on the respective predetermined number of temporal orders.

In Example 16, measuring the respective predetermined number of temporal orders for the first and further entries of the lookup table and adjusting the first and further entries in the method of Example 15 is performed iteratively until a maximum number of iterations or each is reached of the first and further entries fulfills a quality criterion.

In example 17, the method of one of the preceding examples further comprises: measuring, for the first entry, a second temporal order of a transition of the output signal from the second signal level to the first signal level and a transition of the reference signal from the second signal level to the first signal level, wherein the adaptation of the first entry is further based on the respective chronological order.

In example 18, adapting the first entry in the method of one of the preceding examples comprises: incrementing or decrementing the first entry based on the first temporal order.

In Example 19, iteratively adjusting the first entry in the method of Example 13 includes: incrementing or decrementing the first entry in the first iteration by a first value based on the predetermined number of temporal orders of the first iteration; and incrementing or decrementing the first entry in the second iteration by a second value based on the predetermined number of temporal orders of the second iteration, the second value being substantially half of the first value.

In example 20, a bang-bang phase detector is used to measure the temporal order in the method of one of the preceding examples.

In example 21, the first control code for the digital-to-time converter in the method of example 2 is part of a continuously increasing or decreasing code sequence that is generated based on the control word.

Example 22 is a system for calibrating a phase non-linearity of a digital-time converter, comprising: a phase-locked loop designed to generate a reference signal based on a control word, wherein a frequency of the reference signal is substantially equal to a frequency of an output signal of the digital-time Converter is; a detection circuit configured to measure a temporal order of a transition of the output signal from a first signal level to a second signal level and a transition of the reference signal from the first signal level to the second signal level; and a processing circuit configured to adapt a first entry of a lookup table based on the measured temporal order.

In example 23, in the system of example 22, the digital-to-time converter generates the output signal based on the first entry of the lookup table, the first entry being associated with a first control code for the digital-to-time converter that is on the control word for controlling the Frequency of the output signal based.

In example 24, the phase locked loop in the system of example 22 or example 23 is adapted to adjust a phase of the reference signal to be substantially equal to a phase of the output signal generated by the digital-time converter, based on a second entry in the look-up table, wherein the second entry is assigned to a second control code for the digital-time converter, for which the digital-time converter is phase-linear.

In Example 25, the phase locked loop in the system of Example 24 is further configured to generate the reference signal based on a frequency control word, and the detection circuit is further configured to measure, for the second entry, a time shift between a transition of the output signal from the first signal level to that second signal level and a transition of the reference signal from the first signal level to the second signal level; and wherein the system further comprises a conversion circuit configured to generate the frequency control word based on the time shift.

In example 26, the conversion circuit in the system of example 25 is configured to: calculate a phase error of the reference signal with respect to the output signal based on the time shift; and adjusting the frequency control word based on the phase error.

In Example 27, the phase locked loop in the system of Example 24 is further configured to generate the reference signal based on a frequency control word, the detection circuit is further configured to measure, for the second entry, a third temporal order of a transition of the output signal from the first signal level to the second signal level, and a transition of the reference signal from the first signal level to the second signal level; and wherein the system further comprises a conversion circuit configured to generate the frequency control word based on the third temporal order.

In example 28, the conversion circuit in the system of example 27 is configured to: calculate a phase error of the reference signal with respect to the output signal based on the third temporal order; and adjusting the frequency control word based on the phase error.

In example 29, the system of one of examples 25 to 28 further comprises a filter coupled between the detection circuit and the conversion circuit, the filter being designed to pass filtered data from the detection circuit to the conversion circuit only when a control signal which is input to the Filter entered, indicates that the digital-to-time converter produces the output signal based on an entry in the look-up table associated with a control code for the digital-to-time converter for which the digital-to-time converter is phase-linear.

In example 30, the detection circuitry in the system of one of the preceding examples is further configured to measure a predetermined number of time orders, and the processing circuitry is further configured to adjust the first entry based on the predetermined number of time orders.

In example 31, the detection circuit in the system of example 30 is further configured to measure at least part of the predetermined number of temporal orders in parallel.

In example 32, the processing circuitry in the system of example 30 or example 31 is further configured to: derive an indicator value from the predetermined number of time orders that indicates whether the transition of the output signal from the first signal level to the second signal level, or the transition of the reference signal from the first signal level to the second signal level precedes the other more often under the predetermined number of temporal orders; and adjusting the first entry based on the indicator value.

In example 33, the processing circuitry in the system of example 32 is further configured to adapt the first entry only if the absolute value of the indicator value is greater than a threshold value.

In Example 34, the system of any of Examples 30 to 33 is configured to control the detection circuit to iteratively measure the predetermined number of orders of time and to control the processing circuit to determine the first entry based on the predetermined number of times Adjust orders iteratively.

In example 35, the digital-to-time converter in the system of example 34 also generates the output signal based on further entries in the look-up table, the further entries being assigned to further control codes for the digital-to-time converter; wherein the detection circuit is further configured to measure, for the further entries, a respective temporal order of the transition of the output signal from the first signal level to the second signal level and the transition of the reference signal from the first signal level to the second signal level; and wherein the processing circuit is further configured to adapt the further entries based on the respective temporal order.

In example 36, the detection circuit in the system of example 35 is further configured to measure the respective temporal order for the further entries a predetermined number of times, so that a corresponding predetermined number of temporal orders is measured for each of the further entries, the processing circuit is further configured to adapt the further entries based on the respective predetermined number of temporal orders.

In example 37, the system of example 36 is designed to control the detection circuit to iteratively measure the respective predetermined number of temporal orders for the first and the further entries of the look-up table and to control the processing circuit to iteratively adjust the first and the further entries, until a maximum number of iterations has been reached or until each of the first and further entries fulfills a quality criterion.

In example 38, the detection circuit in the system of one of the preceding examples is further configured to measure, for the first entry, a second temporal order of a transition of the output signal from the second signal level to the first signal level and a transition of the reference signal from the second signal level to the first signal level; and the processing circuit is further configured to adapt the first entry further based on the second temporal order.

In example 39, the processing circuitry in the system of one of the preceding examples is further configured to adjust the first entry by incrementing or decrementing the first entry based on the first temporal order.

In example 40, the processing circuitry in the system of example 34 is further configured to iteratively adjust the first entry by: incrementing or decrementing the first entry in the first iteration by a first value based on the predetermined number of temporal orders of the first iteration; and incrementing or decrementing the first entry in the second iteration by a second value based on the predetermined number of temporal orders of the second iteration, the second value being substantially half of the first value.

In example 41, the detection circuit of the system from one of the preceding examples is a bang-bang phase detector.

Example 42 is a receiver comprising a digital time converter and a system for calibrating a phase non-linearity of the digital time converter according to one of the examples 22 to 41.

In example 43, the receiver of example 42 further comprises: a control circuit that is configured to generate a continuously increasing or decreasing code sequence based on the control word, the first control code being part of the code sequence.

In example 44, the receiver of example 42 or example 43 further comprises: another phase locked loop configured to generate an oscillating input signal for the digital-time converter.

In Example 45, the receiver of any one of Examples 42 through 44 further includes: a mixer circuit configured to down-convert a radio frequency receive signal using the output signal.

Example 46 is a mobile device comprising a receiver according to one of Examples 42 to 45.

In example 47, the mobile device of example 46 further comprises: at least one antenna element coupled to the receiver.

Example 48 is a means for calibrating a phase non-linearity of a digital-to-time converter, comprising: means for generating a reference signal based on a control word using a phase-locked loop, wherein a frequency of the reference signal is equal to a frequency of an output signal of the digital-time Converter is; means for measuring a temporal order of a transition of the output signal from a first signal level to a second signal level and a transition of the reference signal from the first signal level to the second signal level; and means for adjusting a first entry of a lookup table based on the measured temporal order.

In Example 49, using the mean of Example 48, the digital-to-time converter generates the output signal based on the first entry of the lookup table, the first entry being associated with a first control code for the digital-to-time converter that is on the control word for controlling the Frequency of the output signal based.

In example 50, the means for generating the reference signal in the means of example 48 or example 49 is further configured to adjust a phase of the reference signal to be substantially equal to a phase of the output signal generated by the digital-time converter, based on a second Entry in the look-up table, the second entry being associated with a second control code for the digital-time converter, for which the digital-time converter is phase-linear.

The aspects and features mentioned and described together with one or more of the previously detailed examples and figures can also be combined with one or more of the other examples to replace a same feature of the other example or to change the feature into the other Introduce example in addition.

Examples may further be, or refer to, a computer program with program code for performing one or more of the above methods when the computer program is executed on a computer or processor. Steps, operations, or processes of various methods described above can be performed by programmed computers or processors. Examples may also cover program storage devices, such as digital data storage media, that are machine, processor, or computer readable and encode machine-executable, processor-executable, or computer-executable programs of instructions. The instructions perform or cause some or all of the steps in the procedures described above. The program storage devices may e.g. B. digital storage, magnetic storage media such as magnetic disks and tapes, hard drives or optically readable digital data storage media include or be. Other examples may include computers, processors, or control units that are programmed to perform the steps of the methods described above, or (field) programmable logic arrays ((F) PLAs = (Field) Programmable Logic Arrays) or (field) programmable Gate Arrays ((F) PGA = (Field) Programmable Gate Arrays) that are programmed to perform the steps of the methods described above.

The description and drawings only illustrate the principles of the disclosure. Furthermore, all examples listed here are intended to serve expressly only for teaching purposes in order to support the reader in understanding the principles of the disclosure and the concepts contributed by the inventor (s) for the further development of the technology. All statements here about principles, aspects and examples of the disclosure, as well as concrete examples thereof, are intended to include their equivalents.

A function block called "means for ..." that performs a specific function can refer to a circuit that is designed to perform a specific function. Thus, a "means for something" can be implemented as a "means trained for or suitable for something", e.g. B. a device or a circuit which is designed for or is suitable for the respective task.

Functions of various elements shown in the figures, including each function block referred to as “means”, “means for providing a sensor signal”, “means for generating a transmit signal”, etc., can be in the form of dedicated hardware, e.g. B "of a signal provider", "a signal processing unit", "a processor", "a controller" etc. as well as hardware capable of executing software in connection with associated software. When provided by a processor, the functions can be provided by a single dedicated processor, by a single shared processor, or by a plurality of individual processors, some or all of which can be shared. However, the term "processor" or "controller" is by no means limited to hardware capable of executing software only, but can be digital signal processor hardware (DSP hardware; DSP = digital signal processor), network processor, application-specific integrated circuit (ASIC = Application Specific Integrated Circuit), Field Programmable Gate Array (FPGA), Read Only Memory (ROM) for software storage, Random Access Memory (RAM) and non-volatile storage device. Other hardware, conventional and / or custom, can also be included.

For example, a block diagram may represent a detailed circuit diagram that implements the principles of the disclosure. Similarly, a flowchart, flowchart, state transition diagram, pseudocode, and the like may represent various processes, operations, or steps that are, for example, substantially represented in computer readable medium and thus performed by a computer or processor, whether or not such Computer or processor is shown explicitly. Methods disclosed in the description or in the claims can be implemented by an apparatus having means for performing each of the respective steps of these methods.

It is understood that the disclosure of several steps, processes, operations or functions disclosed in the description or claims should not be interpreted as being in the specific order unless this is explicitly or implicitly otherwise, e.g. B. for technical reasons. Therefore, by disclosing multiple steps or functions, these are not limited to any particular order unless these steps or functions are not interchangeable for technical reasons. Furthermore, in some examples, a single step, function, process, or operation may include and / or be broken up into multiple substeps, functions, processes, or operations. Such sub-steps can be included and can be part of the disclosure of this single step, unless they are explicitly excluded.

Furthermore, the following claims are hereby incorporated into the detailed description, where each claim may stand on its own as a separate example. While each claim may stand on its own as a separate example, it should be understood that although a dependent claim may refer to a particular combination in the claims with one or more other claims, other examples may also be a combination of the dependent claim with the subject matter of each other dependent or independent claim. Such combinations are explicitly suggested here unless it is stated that a particular combination is not intended. Features of a claim are also intended to be included for any other independent claim, even if that claim is not directly dependent on the independent claim.

Claims (25)

A method (100) for calibrating a phase non-linearity of a digital-time converter, comprising: Generating (102) a reference signal based on a control word using a phase locked loop, a frequency of the reference signal being substantially equal to a frequency of an output signal of the digital-time converter; Measuring (104) a temporal order of a transition of the output signal from a first signal level to a second signal level and a transition of the reference signal from the first signal level to the second signal level; and Adjusting (106) a first entry of a lookup table based on the measured temporal order. The procedure according to Claim 1 , wherein the digital-time converter generates the output signal based on the first entry of the look-up table, and wherein the first entry is associated with a first control code for the digital-time converter, which is based on the control word for controlling the frequency of the output signal. The procedure according to Claim 1 or Claim 2 , further comprising: adjusting a phase of the reference signal to be substantially equal to a phase of the output signal generated by the digital time converter based on a second entry in the lookup table, the second entry being a second control code for the digital time Assigned converter for which the digital-time converter is phase linear. The procedure according to Claim 3 , wherein the generation of the reference signal is further based on a frequency control word and wherein the adjustment of the phase of the reference signal comprises: measuring, for the second entry, a third temporal order of a transition of the output signal from the first signal level to the second signal level and a transition of the reference signal from the first signal level to the second signal level; and generating the frequency control word based on the third temporal order. The procedure according to Claim 4 comprising adjusting the frequency control word: calculating a phase error of the reference signal with respect to the output signal based on the third temporal order; and adjusting the frequency control word based on the phase error. The procedure according to Claim 2 , further comprising: measuring a phase error of the reference signal with respect to a phase of the output signal generated by the digital-time converter based on a second entry in the look-up table, the second entry being associated with a second control code for the digital-time converter, for which the digital-time converter is phase-linear; and generating a correction code based on the phase offset, wherein the first control code is further based on the correction code. The procedure according to Claim 1 or Claim 2 wherein measuring (104) the temporal order comprises measuring a predetermined number of temporal orders, and wherein adjusting (106) the first entry is based on the predetermined number of temporal orders. The procedure according to Claim 7 , wherein at least part of the predetermined number of temporal orders is measured in parallel. The procedure according to Claim 7 comprising adjusting (106) the first entry based on the predetermined number of time orders: deriving an indicator value from the predetermined number of time orders that indicates whether the transition of the output signal from the first signal level to the second signal level or the transition of the Reference signal from the first signal level to the second signal level more often precedes the other among the predetermined number of time orders; and adjusting the first entry based on the indicator value. The procedure according to Claim 9 , the first entry being adapted only if the absolute value of the indicator value is greater than a threshold value. The procedure according to Claim 7 wherein measuring (104) the predetermined number of time orders and adjusting (106) the first entry based on the predetermined number of time orders is performed iteratively. The procedure according to Claim 11 , wherein the digital-time converter generates the output signal based on further entries in the look-up table, the further entries being assigned to further control codes for the digital-time converter, and the method further comprising: measuring, for the further entries, a respective one temporal order of the transition of the output signal from the first signal level to the second signal level and the transition of the reference signal from the first signal level to the second signal level; and adapting the further entries based on the respective chronological order. The procedure according to Claim 12 , wherein the respective temporal order is measured for the further entries a predetermined number of times, so that a corresponding predetermined number of temporal orders is measured for each of the further entries, and wherein the adaptation of the further entries to the respective predetermined number of temporal orders based. The procedure according to Claim 13 , wherein the respective predetermined number of temporal orders for the first and the further entries of the look-up table and the adaptation of the first and the further entries are carried out iteratively until a maximum number of iterations is reached or each of the first and the further entries Quality criterion met. The procedure according to Claim 1 or Claim 2 , further comprising: measuring, for the first entry, a second temporal order of a transition of the output signal from the second signal level to the first signal level and a transition of the reference signal from the second signal level to the first signal level; wherein adapting the first entry is further based on the second temporal order. The procedure according to Claim 1 or Claim 2 , customizing the first entry comprehensively: Increment or decrement the first entry based on the first temporal order. The procedure according to Claim 11 comprising iteratively adjusting the first entry: incrementing or decrementing the first entry in the first iteration by a first value based on the predetermined number of temporal orders of the first iteration; and incrementing or decrementing the first entry in the second iteration by a second value based on the predetermined number of temporal orders of the second iteration, the second value being substantially half of the first value. A system (200) for calibrating a phase non-linearity of a digital-to-time converter (210), comprising: a phase locked loop (230) configured to generate a reference signal (231) based on a control word (205), a frequency of the reference signal (231) being substantially equal to a frequency of an output signal (211) of the digital-time converter (210) is a detection circuit (240) configured to measure a temporal order of a transition of the output signal (211) from a first signal level to a second signal level and a transition of the reference signal (231) from the first signal level to the second signal level; and a processing circuit (250) configured to adjust a first entry of a lookup table (220) based on the measured temporal order. The system according to Claim 18 , wherein the digital time converter (210) generates the output signal (211) based on the first entry (221) of the lookup table (220), the first entry (221) of a first control code for the digital time converter (210 ) which is based on the control word (205) for controlling the frequency of the output signal (211). The system according to Claim 18 or Claim 19 , wherein the phase locked loop (230) is adapted to adjust a phase of the reference signal (231) to be substantially equal to a phase of the output signal (211) generated by the digital time converter (210) based on a second entry in the Lookup table (220), the second entry being associated with a second control code for the digital time converter (210) for which the digital time converter (210) is phase linear. The system according to Claim 20 , wherein: the phase locked loop (230) is further configured to generate the reference signal (231) based on a frequency control word, wherein the detection circuit (240) is further configured to provide a third temporal order of a transition of the output signal for the second entry (211) measure from the first signal level to the second signal level and a transition of the reference signal (231) from the first signal level to the second signal level; and the system further comprises a conversion circuit (280) configured to generate the frequency control word based on the third temporal order. The system according to Claim 18 or Claim 19 , wherein the detection circuit (240) is further configured to measure a predetermined number of time orders, and wherein the processing circuit (250) is further configured to adapt the first entry (221) based on the predetermined number of time orders. The system according to Claim 22 , wherein the processing circuit (250) is further configured to: derive an indicator value from the predetermined number of temporal orders, which indicates whether the transition of the output signal (211) from the first signal level to the second signal level or the transition of the reference signal (231) from the first signal level to the second signal level, the other more often precedes the predetermined number of time orders; and adjusting the first entry (221) based on the indicator value. The system according to Claim 23 , wherein the processing circuit (250) is further configured to adapt the first entry (221) only if the absolute value of the indicator value is greater than a threshold value. A receiver (670) comprising a digital time converter (610) and a system (630) for calibrating a phase non-linearity of the digital time converter (610) according to one of the Claims 18 to 24th .

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