DE112016004400B4 - Array substrate, liquid crystal display panel and liquid crystal display device - Google Patents

Abstract

Array substrate (12), the array substrate (12) comprising:a plurality of scan lines (G) and a plurality of data lines (D), a plurality of first sub-pixel regions (P1) and a plurality of second sub-pixel regions (P2) being defined by the plurality of scan lines (G) and the plurality data lines (D) are defined;first pixel electrodes (34) located in the respective first sub-pixel area (P1);second pixel electrodes (35) located in the respective second sub-pixel area (P2);common electrodes each located between two adjacent first pixel electrodes ( 34) and in each case between the first pixel electrode (34) and the second pixel electrode (35) which are adjacent;first vias (32) which lie in the respective first sub-pixel region (P1) and in the respective second sub-pixel region (P2), wherein the first vias (32) are used to produce electrical connections between the first pixel electrodes (34) and the data lines (D) and the second pixel electrodes (35) and the data lines (D);second vias (33) which are located in the respective second sub-pixel region ( P2), the common electrodes receiving the voltage through the second vias (33), characterized in that a pixel area of the array substrate (12) comprises two first sub-pixel areas (P1) and a second sub-pixel area (P2), the second sub-pixel area ( P2) is one of the sub-pixel areas (P) R, G and B, in each pixel area the common electrode receiving the voltage through the second via (33) located in the second sub-pixel area (P2);wherein the respective first via (32) and the respective second vias (33) are located on two sides of the respective scanning lines, the respective first vias (32) being between the scanning lines (G) and the first pixel electrode (34) and between the respective scanning line and the corresponding second pixel electrode.

Description

field of invention

The present invention relates to the field of liquid crystal display technology, and more particularly to an array substrate and a liquid crystal display panel and a liquid crystal display device having the array substrate.

State of the art

With the continuous advancement of electronic technology, LCDs (Liquid Crystal Display) are widely used in various display fields. The array substrate, which is an important component of the LCD, includes a plurality of pixel areas arranged in a matrix, each pixel area including a plurality of sub-pixel areas. In the current pixel structure, a common via (com via) is provided in each sub-pixel region, so that the common electrode receives the scanning voltage through the respective via. However, there are a large number of via holes for the common electrodes, occupying a very large sub-pixel area, which will undoubtedly lead to a reduction in the area of the display region, so that the pixel aperture ratio and the light transmission rate of the pixels are reduced.

Conventional array substrates, liquid crystal display panels and liquid crystal display devices are disclosed in, for example, U.S. 2009/0207365 A1 , U.S. 2012/0113343 A1 , U.S. 2004/0263748 A1 and U.S. 2003/0184693 A1 described.

object of the invention

It is an object of the present invention to provide an array substrate, a liquid crystal display panel and a liquid crystal display device, by which the pixel aperture ratio and the light transmission rate of the pixels can be increased.

The array substrate of the present invention includes: a plurality of scan lines and a plurality of data lines defining a plurality of first sub-pixel regions and a plurality of second sub-pixel regions; first pixel electrodes located in the respective first sub-pixel area; second pixel electrodes located in the respective second sub-pixel region; common electrodes each interposed between two adjacent first pixel electrodes and each between the first pixel electrode and the second pixel electrode which are adjacent; first vias located in the respective first sub-pixel region and in the respective second sub-pixel region, the first vias being used to establish electrical connections between the first pixel electrodes and the data lines and the second pixel electrodes and the data lines; second vias located in the respective second sub-pixel area, the common electrodes receiving the voltage through the second vias. Here, a pixel area of the array substrate includes two first sub-pixel areas and a second sub-pixel area, the second sub-pixel area being one of the sub-pixel areas R, G and B, wherein in each pixel area the common electrode receives the voltage through the second via located in the second sub-pixel area. Here, the respective first via and the respective second via lie on two sides of the respective scan line, the respective first via lies between the scan lines and the first pixel electrode and between the respective scan line and the corresponding second pixel electrode.

In this case, the area of a respective first pixel electrode is larger than that of the second pixel electrode.

Here, a pixel area of the array substrate includes three first sub-pixel areas and a second sub-pixel area, the second sub-pixel area being one of the sub-pixel areas R, G, B and W, wherein in each pixel area the common electrode receives the voltage through the second via located in the second sub-pixel area.

Here, the array substrate comprises a plurality of scan lines arranged in the row direction, with each first sub-pixel region being correspondingly connected to a scan line, with every second sub-pixel region being correspondingly connected to a scan line, the first sub-pixel regions and the second sub-pixel region being between the scan lines of the n-th row and the n+1th row are electrically connected to the scanning line of the nth row, where n is a positive integer.

Here, the common electrodes, the first pixel electrodes, and the second pixel electrodes are formed by the same photomask process.

Here, the common electrodes and the corresponding data lines overlap each other, with each common electrode comprising an opaque conductive metal layer.

The present invention provides a liquid crystal display panel comprising an array substrate, the array substrate comprising: a plurality of scanning lines and a plurality of data lines by which a plurality of first sub-pixel regions and a plurality of second sub-pixel regions are defined; first pixel electrodes located in the respective first sub-pixel area; second pixel electrodes located in the respective second sub-pixel region; common electrodes each interposed between two adjacent first pixel electrodes and each between the first pixel electrode and the second pixel electrode which are adjacent; first vias located in the respective first sub-pixel area and in the respective second sub-pixel area, the first vias being used to establish electrical connections between the first pixel electrodes and the data lines and the second pixel electrodes and the data lines; second vias located in the respective second sub-pixel area, the common electrodes receiving the voltage through the second vias. Here, a pixel area of the array substrate includes two first sub-pixel areas and a second sub-pixel area, the second sub-pixel area being one of the sub-pixel areas R, G and B, wherein in each pixel area the common electrode receives the voltage through the second via located in the second sub-pixel area. Here, the respective first via and the respective second via lie on two sides of the respective scanning line, the respective first via connecting between the scanning lines and the first pixel electrode and between the respective scanning line and the corresponding second pixel electrode.

In this case, the area of a respective first pixel electrode is larger than that of the second pixel electrode.

Here, a pixel area of the array substrate includes three first sub-pixel areas and a second sub-pixel area, the second sub-pixel area being one of the sub-pixel areas R, G, B and W, wherein in each pixel area the common electrode receives the voltage through the second via located in the second sub-pixel area.

Here, the array substrate comprises a plurality of scan lines arranged in the row direction, with each first sub-pixel region being correspondingly connected to a scan line, with every second sub-pixel region being correspondingly connected to a scan line, the first sub-pixel regions and the second sub-pixel region being between the scan lines of the n-th row and the n+1th row are electrically connected to the scanning line of the nth row, where n is a positive integer.

Here, the common electrodes, the first pixel electrodes, and the second pixel electrodes are formed by the same photomask process.

Here, the common electrodes and the corresponding data lines overlap each other, with each common electrode comprising an opaque conductive metal layer.

The present invention provides a liquid crystal display device comprising a liquid crystal display panel and a backlight module for providing a backlight for the liquid crystal display panel, the liquid crystal display panel comprising an array substrate, the array substrate comprising: a plurality of scanning lines and a plurality of data lines through which a plurality of first sub-pixel regions and a plurality of second sub-pixel areas are defined; first pixel electrodes located in the respective first sub-pixel area; second pixel electrodes located in the respective second sub-pixel region; common electrodes each interposed between two adjacent first pixel electrodes and each between the first pixel electrode and the second pixel electrode which are adjacent; first vias located in the respective first sub-pixel region and in the respective second sub-pixel region, the first vias being used to establish electrical connections between the first pixel electrodes and the data lines and the second pixel electrodes and the data lines; second vias located in the respective second sub-pixel area, the common electrodes receiving the voltage through the second vias.

The array substrate, the liquid crystal display panel and the liquid crystal display device of the embodiments of the present invention are designed such that a plurality of sub-pixels located in the same pixel area share a through hole, whereby the common electrode receives the voltage so as to increase the pixel aperture ratio and the light transmission rate of the pixels.

character list

• • 1 eine Schnittansicht eines Ausführungsbeispiels der erfindungsgemäßen Flüssigkristallanzeigetafel;
• • 2 eine schematische teilweise Darstellung der Pixelstruktur des Ausführungsbeispiels der Flüssigkristallanzeigetafel gemäß 1;
• • 3 eine schematische Darstellung einer Pixelstruktur gemäß 2;
• • 4 eine schematische Darstellung, in der die Bildung des ersten Pixelbereichs des Ausführungsbeispiels gemäß der vorliegenden Erfindung dargestellt ist;
• • 5 eine schematische Darstellung, in der die Bildung des zweiten Pixelbereichs des Ausführungsbeispiels gemäß der vorliegenden Erfindung dargestellt ist;
• • 6 eine Schnittansicht des Ausführungsbeispiels der erfindungsgemäßen Flüssigkristallanzeigevorrichtung.

The drawings used to explain the embodiment show in:

• • 1 Fig. 12 is a sectional view showing an embodiment of the liquid crystal display panel according to the present invention;
• • 2 FIG. 12 is a partial schematic representation of the pixel structure of the embodiment of the liquid crystal display panel of FIG 1 ;
• • 3 a schematic representation of a pixel structure according to FIG 2 ;
• • 4 Fig. 12 is a diagram showing the formation of the first pixel region of the embodiment according to the present invention;
• • 5 Fig. 12 is a diagram showing the formation of the second pixel region of the embodiment according to the present invention;
• • 6 Fig. 12 is a sectional view of the embodiment of the liquid crystal display device according to the present invention.

Detailed description of the embodiment

In order to enable a clear and complete understanding of the technical solution of the embodiment of the present invention, the preferred embodiment will be described in detail below with reference to the accompanying drawings.

1 Fig. 12 shows a sectional view of the embodiment of the liquid crystal display panel according to the present invention. 2 FIG. 12 shows a partial schematic representation of the pixel structure of the embodiment of the liquid crystal display panel according to FIG 1 . As in the 1 and 2 As shown, the liquid crystal display panel 10 of the present embodiment comprises a color filter substrate (CF substrate) 11 and an array substrate (thin film transistor substrate, TFT substrate; also known as thin film transistor substrate) 12 spaced from each other and one between the two substrates filled liquid crystal (liquid crystal molecules) 13, the liquid crystal 13 being in the liquid crystal cell formed by the superposition of the array substrate 11 and the color filter substrate 12.

The array substrate 12 includes multiple data lines D arranged in the column direction, multiple scan lines G arranged in the row direction, and multiple sub-pixel regions P defined by crossing the multiple scan lines G and the multiple data lines D. Each sub-pixel region P is connected to a corresponding data line D and a corresponding scan line G. All scan lines G are connected to a gate driver 21 to provide a scan voltage for each sub-pixel region P . All data lines D are connected to a source driver 22 to provide a gray scale voltage for each sub-pixel region P . Since the in-plane switching technology (IPS) is used for the liquid crystal display panel 10, a pixel structure with a domain structure is used for the array substrate 12 of the present exemplary embodiment, with all subpixel electrodes in the respective subpixel region P having "∧" or "<" are shaped. Accordingly, the data lines D do not run straight along the column direction.

In the present exemplary embodiment, a sub-pixel area P comprises a first sub-pixel area P1 and a second sub-pixel area P2. In the example of the liquid crystal display panel 10 with three sub-pixels RGB, the second sub-pixel area P2 corresponds to the sub-pixel area B (blue color) and the first sub-pixel areas P1 correspond to the sub-pixel area R (red color) and the sub-pixel area G (green color), with a second sub-pixel area P2 and two adjacent first sub-pixel areas P1 form a pixel area of the array substrate 12 . Since the structure of several pixel areas in the matrix arrangement is exactly the same, an in 3 shown pixel area of the n-th line is described as a representative, where n is a positive integer.

As in 3 As shown, the two first sub-pixel regions P1 and a second sub-pixel region P2 located between the n-th row and the n+1-th row are all connected to the scanning line of the n-th row Gn. The array substrate 12 includes common electrodes 31, first vias 32, second vias 33, first pixel electrodes 34 located in each first sub-pixel region P1, and second pixel electrodes 35 located in each second sub-pixel region P2. Here, the common electrodes 31 are each located between two adjacent first pixel electrodes 34 and each between the first pixel electrode 34 and the second pixel electrode 35, the first vias 32 being located in the respective first sub-pixel region P1 and in the respective second sub-pixel region P2. More specifically, each first via 32 is located in each first sub-pixel region P1 between the scan line Gn and each first pixel electrode 34 . The respective first via 32 is a via of the pixel electrode (pixel via) and serves to establish an electrical connection between a respective first pixel electrode 34 and the corresponding data line D. More specifically, the respective first via 32 is located in the respective second sub-pixel region P2 between the scanning line Gn and a respective second pixel electrode 32 and it serves to establish an electrical connection between a respective second pixel electrode 35 and the corresponding data line D. The respective second via 33 is located in the respective second sub-pixel region P2, wherein it and the respective first via 32 lie on two sides of the scan line Gn. The respective second via 33 is a via of the common electrode and is for the respective common electrode 31 to receive the voltage through the respective second via 33, wherein the voltage may be a sensing voltage. Since the respective second via 33 is provided only in the respective second sub-pixel region P2 and not in the first sub-pixel region P1 , the area of a respective first pixel electrode 34 is larger than that of the second pixel electrode 35 .

Here, the common electrode in the second sub-pixel region P2 receives the voltage through the second via hole 33, and the common electrode 31 in the first sub-pixel region P1 can be electrically connected to the common electrode 31 in the second sub-pixel region P2 through the external wiring. Preferably, the external wiring and the scan line Gn or the scan line Gn+1 overlap each other.

As can be seen from the above description, a plurality of sub-pixels (sub-pixel electrodes) located within the same pixel region share a via, so that the common electrode 31 receives the voltage through the via. In the present invention, compared to the prior art, the number of via holes is reduced, whereby the pixel aperture ratio and the light transmission rate of the pixels can be increased.

In the above pixel structure design, since the sub-pixel R and sub-pixel G have no via (second via 33) for common electrodes, the area of the first pixel electrode 34 increases, the pixel aperture ratio increases, and the light transmission rate increases compared to the prior art. The reason why the second via hole 33 is provided in the sub-pixel B in the present embodiment is that the sub-pixel B transmits blue light, and the blue light contributes less to the display brightness of the liquid crystal display panel 10 than the red and green lights. Even if the area of the second pixel electrode 35 becomes smaller, the influence on the total light transmittance rate of the pixels is still small.

Of course, in other exemplary embodiments, the second via 33 can also be arranged in the sub-pixel area R or sub-pixel area G, i. H. the second sub-pixel area P2 is the sub-pixel area R or sub-pixel area G.

In the four-subpixel RGBW liquid crystal display panel 10, a pixel area of the array substrate 12 includes three first sub-pixel areas P1 and one second sub-pixel area P2, the second sub-pixel area P2 being one of the sub-pixel areas R, G, B, W (White), for example, it may be a be sub-pixel region B. Within each pixel region, the common electrode 31 receives the voltage through the second via hole 33 located in the second sub-pixel region P2.

• • Bilden einer ein vorgegebenes Muster aufweisenden ersten Metallschicht 41 , wobei die erste Metallschicht 41 zur Bildung der Abtastleitung G, des Gates g für den Dünnfilmtransistor (TFT) des Arraysubstrats 12 , der der ersten Durchkontaktierung 32 entsprechenden Metallschicht und anderer Metallverdrahtungen dient;
• • Bilden einer aktiven Halbleiterschicht 42 des TFTs (Active Semiconductor Layer, AS) auf der ersten Metallschicht 41 , wobei die aktive Halbleiterschicht 42 oberhalb des Gates g liegt;
• • Bilden einer ein vorgegebenes Muster aufweisenden zweiten Metallschicht 43 auf der aktiven Halbleiterschicht 42 , wobei die zweite Metallschicht 43 zur Bildung der Datenleitung D, der Source s und des Drains d des TFTs dient;
• • Bilden einer mit der ersten Durchkontaktierung 32 versehenen ebenen Passivierungsschicht auf der zweiten Metallschicht 43 ;
• • Bilden einer ersten Pixelelektrode 34 und einer gemeinsamen Elektrode 31 auf der mit der ersten Durchkontaktierung 32 versehenen ebenen Passivierungsschicht, wobei vorzugsweise die gemeinsame Elektrode 31 und die erste Pixelelektrode 34 durch das gleiche Fotomaskenverfahren gebildet sind, d. h. die gemeinsame Elektrode 31 ist eine transparente leitfähige Schicht, deren Material Indiumzinnoxid (ITO) sein kann.

4 Fig. 12 is a diagram showing the formation of the first pixel region of the embodiment according to the present invention. As in 4 shown, the formation of the first sub-pixel area P1 in the present exemplary embodiment comprises the following steps:

• • forming a first metal layer 41 having a predetermined pattern, the first metal layer 41 for forming the scan line G, the gate g for the thin film transistor (TFT) of the array substrate 12, the metal layer corresponding to the first via hole 32, and other metal wirings;
• • forming an active semiconductor layer 42 of the TFT (Active Semiconductor Layer, AS) on the first metal layer 41, the active semiconductor layer 42 being above the gate g;
• • forming a second metal layer 43 having a predetermined pattern on the active semiconductor layer 42, the second metal layer 43 for forming the data line D, the source s and the drain d of the TFT;
• • forming a planar passivation layer provided with the first via 32 on the second metal layer 43;
• Forming a first pixel electrode 34 and a common electrode 31 on the planar passivation layer provided with the first via 32, preferably the common electrode 31 and the first pixel electrode 34 are formed by the same photomask process, ie the common electrode 31 is a transparent conductive layer , the material of which can be indium tin oxide (ITO).

• • Bilden einer ein vorgegebenes Muster aufweisenden ersten Metallschicht 51 , wobei die erste Metallschicht 51 zur Bildung der Abtastleitung G, des Gates g des TFTs, der der ersten Durchkontaktierung 32 entsprechenden Metallschicht, der der zweiten Durchkontaktierung 33 entsprechenden Metallschicht und anderer Metallverdrahtungen dient;
• • Bilden einer aktiven Halbleiterschicht 52 auf der ersten Metallschicht 51 , die oberhalb des Gates g liegt
• • Bilden einer ein vorgegebenes Muster aufweisenden zweiten Metallschicht 53 auf der aktiven Halbleiterschicht 52 , wobei die zweite Metallschicht 53 zur Bildung der Datenleitung D, der Source s und des Drains d des TFTs dient;
• • Bilden einer ebenen Passivierungsschicht auf der zweiten Metallschicht 53 , wobei die ebene Passivierungsschicht nicht nur mit einer ersten Durchkontaktierung 32 , sondern auch mit einer zweiten Durchkontaktierung 33 versehen ist;
• • Bilden einer zweiten Pixelelektrode 35 und einer gemeinsamen Elektrode 31 auf der mit der ersten Durchkontaktierung 32 und der zweiten Durchkontaktierung 33 versehenen ebenen Passivierungsschicht, wobei vorzugsweise die gemeinsame Elektrode 31 und die zweite Pixelelektrode 35 durch das gleiche Fotomaskenverfahren gebildet sind, d. h. die gemeinsame Elektrode 31 ist eine transparente leitfähige Schicht, deren Material aber nicht auf Indiumzinnoxid (ITO) beschränkt ist. Selbstverständlich kann in anderen Ausführungsbeispielen auch eine gemeinsame Elektrode 31 angeordnet sein, die allein durch das Fotomaskenverfahren oder durch andere Mittel gebildet ist. Da sich die gemeinsame Elektrode 31 und die entsprechende Datenleitung D gegenseitig überlappen, kann die Datenleitung D der gemeinsamen Elektrode 31 auch eine undurchsichtige leitfähige Metallschicht sein.

5 Fig. 12 is a diagram showing the formation of the second pixel region of the embodiment according to the present invention. As in 5 shown, the formation of the second sub-pixel region P2 in the present exemplary embodiment comprises the following steps:

• • Forming a first metal layer 51 having a predetermined pattern, the first metal layer 51 for forming the scanning line G, the gate g of the TFT, the metal layer corresponding to the first via hole 32, the metal layer corresponding to the second via hole 33, and other metal wirings;
• • forming an active semiconductor layer 52 on the first metal layer 51 overlying the gate g
• • forming a second metal layer 53 having a predetermined pattern on the active semiconductor layer 52, the second metal layer 53 for forming the data line D, the source s and the drain d of the TFT;
• • forming a planar passivation layer on the second metal layer 53, the planar passivation layer being provided not only with a first via 32 but also with a second via 33;
• • forming a second pixel electrode 35 and a common electrode 31 on the planar passivation layer provided with the first via 32 and the second via 33, preferably the common electrode 31 and the second pixel electrode 35 are formed by the same photomask process, ie the common electrode 31 is a transparent conductive layer, but its material is not limited to indium tin oxide (ITO). Of course, in other embodiments, a common electrode 31 formed solely by the photomask method or by other means may also be arranged. Since the common electrode 31 and the corresponding data line D overlap each other, the data line D of the common electrode 31 may be an opaque conductive metal layer.

In actual use, the first sub-pixel regions P1 and the second sub-pixel region P2 are not individually formed. Referring at the same time to the 4 and 5 the first metal layers 41, 51 can be formed by a same photomask process, the active semiconductor layers 42, 52 can be formed by a same process, the second metal layers 43, 53 can be formed by a same photomask process, the planar passivation layers can be formed by a the same method can be formed, the second via hole 33 and all the first via holes 32 can be formed by a same method, the common electrode 31, the first pixel electrodes 34 and the second pixel electrode 35 can also be formed by a same photomask method.

The embodiment of the present invention further provides a liquid crystal display device 60 as shown in FIG 6 1, wherein the liquid crystal display device 60 comprises the above liquid crystal display panel 10 and a backlight module 61 that supplies light to the liquid crystal display panel 10. Since the liquid crystal display device 60 also has the above configuration of the array substrate 12, it also achieves the same advantageous effect.

The above description represents only a preferred embodiment of the invention and is not intended to limit the protection claims. All equivalent changes and modifications, which can be made by one skilled in the art in accordance with the description and drawings of the invention, fall within the scope of the present invention.

Claims (11)

Array substrate (12), the array substrate (12) comprising: a plurality of scan lines (G) and a plurality of data lines (D), a plurality of first sub-pixel regions (P1) and a plurality of second sub-pixel regions (P2) through the plurality of scan lines (G) and the plurality data lines (D) are defined; first pixel electrodes (34) located in the respective first sub-pixel region (P1); second pixel electrodes (35) located in the respective second sub-pixel region (P2); common electrodes each lying between two adjacent first pixel electrodes (34) and each between the first pixel electrode (34) and the second pixel electrode (35) which are adjacent; first vias (32), which are located in the respective first sub-pixel area (P1) and in the respective second sub-pixel area (P2), the first vias (32) for producing electrical connections between the first pixel electrodes (34) and the data lines (D) and the second pixel electrodes (35) and the data lines (D); second vias (33), which are located in the respective second sub-pixel area (P2), the common electrodes receiving the voltage through the second vias (33), characterized in that a pixel area of the array substrate (12) has two first sub-pixel areas (P1) and one second sub-pixel area (P2), wherein the second sub-pixel area (P2) is one of the sub-pixel areas (P) R, G and B, wherein in each pixel area the common electrode through the second via (33) located in the second sub-pixel area (P2) carries the voltage receives; wherein the respective first via (32) and the respective second vias (33) lie on two sides of the respective scanning lines, the respective first vias (32) being between the scanning lines (G) and the first pixel electrode (34) and between the respective scanning line and the corresponding second pixel electrode. Array substrate (12) after claim 1 , wherein the area of a respective first pixel electrode (34) is larger than that of the second pixel electrode (35). Array substrate (12) after claim 1 , wherein the array substrate (12) comprises a plurality of scanning lines (G) arranged in the row direction, each first sub-pixel region (P1) being correspondingly connected to a scanning line, each second sub-pixel region (P2) being correspondingly connected to a scanning line, the first sub-pixel regions (P1) and the second sub-pixel region (P2) lying between the (G) nth row and n+1th row scan lines are electrically connected to the nth row scan line, where n is a positive integer number is. Array substrate (12) after claim 3 wherein the common electrodes, the first pixel electrodes (34) and the second pixel electrodes (35) are formed by the same photomask method. Array substrate (12) after claim 3 wherein the common electrodes and the corresponding data lines (D) overlap each other, each common electrode comprising an opaque conductive metal layer. A liquid crystal display panel (10), the liquid crystal display panel (10) comprising an array substrate (12), the array substrate (12) comprising: a plurality of scan lines (G) and a plurality of data lines (D), a plurality of first sub-pixel regions (P1) and a plurality of second sub-pixel regions (P2) are defined by the plurality of scanning lines (G) and the plurality of data lines (D); first pixel electrodes (34) located in the respective first sub-pixel area (P1); second pixel electrodes (35) located in the respective second sub-pixel region (P2); common electrodes each lying between two adjacent first pixel electrodes (34) and each between the first pixel electrode (34) and the second pixel electrode (35) which are adjacent; first vias (32), which are located in the respective first sub-pixel area (P1) and in the respective second sub-pixel area (P2), the first vias (32) for producing electrical connections between the first pixel electrodes (34) and the data lines (D) and the second pixel electrodes (35) and the data lines (D); second vias (33), which are located in the respective second sub-pixel area (P2), the common electrodes receiving the voltage through the second vias (33), characterized in that a pixel area of the array substrate (12) has two first sub-pixel areas (P1) and one second sub-pixel area (P2), wherein the second sub-pixel area (P2) is one of the sub-pixel areas (P1) R, G and B, wherein in each pixel area the common electrode through the second via (33) located in the second sub-pixel area (P2) carries the voltage receives, the respective first via (32) and the respective second via (33) lying on two sides of the respective scan line, the respective first via (32) between the scan lines (G) and the first pixel electrode (34) and between the respective scanning line and the corresponding second pixel electrode (35). Liquid crystal display panel (10). claim 6 , in which the area of a respective first pixel electrode (34) is larger than that of the second pixel electrode (35). Liquid crystal display panel (10). claim 6 , in which the array substrate (12) comprises a plurality of scanning lines (G) arranged in the row direction, each first sub-pixel region (P1) being correspondingly connected to a scanning line, each second sub-pixel region (P2) being correspondingly connected to a scanning line, the first sub-pixel regions (P1) and the second sub-pixel region (P2) lying between the scan lines (G) of the nth row and the n+1th row are electrically connected to the scan line of the nth row, where n is a positive integer number is. liquid crystal display panel claim 8 wherein the common electrodes, the first pixel electrodes (34) and the second pixel electrodes (35) are formed by the same photomask method. Liquid crystal display panel (10). claim 8 , in which the common electrodes and the corresponding data lines (D) overlap each other, the respective common electrode comprising an opaque conductive metal layer. A liquid crystal display device (60) comprising a liquid crystal display panel (10) and a backlight module (61) for providing a backlight for the liquid crystal display panel (10), the liquid crystal display panel (10) comprising an array substrate (12), the array substrate (12) comprising : a plurality of scanning lines (G) and a plurality of data lines (D), a plurality of first sub-pixel regions (P1) and a plurality of second sub-pixel regions (P2) being defined by the plurality of scanning lines (G) and the plurality of data lines (D); first pixel electrodes (34) located in the respective first sub-pixel area (P1); second pixel electrodes (35) located in the respective second sub-pixel area (P2); common electrodes each lying between two adjacent first pixel electrodes (34) and each between the first pixel electrode (34) and the second pixel electrode (35) which are adjacent; first vias (32), which are located in the respective first sub-pixel area (P1) and in the respective second sub-pixel area (P2), the first vias (32) for producing electrical connections between the first pixel electrodes (34) and the data lines (D) and the second pixel electrodes and the data lines (D); second vias (33) located in the respective second sub-pixel area (P2), the common electrodes receiving the voltage through the second vias (33); characterized in that a pixel area of the array substrate (12) comprises two first sub-pixel areas (P1) and a second sub-pixel area (P2), the second sub-pixel area (P2) being one of the sub-pixel areas (P) R, G and B, wherein in each pixel area the common electrode receives the voltage through the second via (33) located in the second sub-pixel region (P2), the respective first via (32) and the respective second via (33) being on two sides of the respective scan line, the respective first via (32) between the scanning lines (G) and the first pixel electrode (34) and between each scanning line and the corresponding second pixel electrode (35).

Images