DE112016003568B4 - Intelligent checking or verification for programming non-volatile memory - Google Patents

Abstract

A non-volatile memory device comprising:a plurality of non-volatile memory elements (MC1, MC2, ...);a control circuit (110, 122, 124, 128, 132) communicating with the non-volatile memory elements, the control circuit thereto is configured to:obtain a command to program a group of the plurality of non-volatile memory elements;characterize a programming speed of the group by applying a programming signal to the group while a subset of the group is enabled for programming and the remaining members of the group thereon be prevented from being programmed, wherein in characterizing the programming speed, a threshold voltage verification is performed at an intelligent verification reference level; determining a magnitude for a dummy programming pulse based on the programming speed; applying the dummy programming pulse to the group, while selected of the remaining members of the group are cleared for programming and while the subset is prevented from being programmed; andprogram the group of non-volatile memory elements after the dummy programming pulse is applied to the group.

Description

background

The present disclosure relates to non-volatile storage technology.

Semiconductor memories are used in various electronic devices. For example, non-volatile semiconductor memories are used in cell phones, digital cameras, personal digital assistants, portable computing devices, non-portable computing devices, and other devices. Electrical Eraseable Programmable Read Only Memory (EEPROM) and flash memory are among the most popular non-volatile semiconductor memories.

Some non-volatile memories store information in a charge storage region that is isolated from a channel region in a semiconductor memory substrate. For example, a floating gate is positioned over a channel region of a semiconductor substrate and is isolated from the channel region in the semiconductor substrate. The floating gate is positioned between the source region and the drain region. A control gate is provided across the floating gate and is isolated from the floating gate. The threshold voltage of the transistor is controlled by the amount of charge retained in the floating gate. That is, the minimum amount of voltage that must be applied to the control gate before the transistor is turned on to allow conduction between its source and drain is controlled by the charge level on the floating gate.

Some non-volatile memories use a charge trapping layer to store information. One such example has an oxide-nitride-oxide (ONO) region in which the nitride (e.g. SiN) serves as a charge trapping layer to store information. When such a memory cell is to be programmed, electrons are stored in the charge trapping layer.

Non-volatile memory could have a 2D architecture or a 3D architecture. Recently, ultra-high density memory devices that have a 3D stacked memory structure comprising strings of memory cells have been proposed. Such a storage device is sometimes referred to as a “Bit Cost Scalable” (BiCS) architecture. For example, a 3D NAND stacked memory device may be formed from an array of alternating conductor and insulator layers. A storage hole is drilled into the layers to define or delimit many storage layers simultaneously. A NAND chain is then formed by filling the memory hole with appropriate materials. A straight NAND chain extends in a memory hole, while a tube or U-shaped NAND chain (P-BiCS) is a pair of vertical columns of memory cells that extend in two memory holes and that are connected via a pipe connection. Control gates of the memory cells are provided by the conductor layers.

Prior to programming certain non-volatile memory devices, such as a NAND flash memory device, the memory cells are erased. The erase operation removes electrons from the floating gate in some devices. In some devices, the erase operation removes electrons from the charge trapping layer. Consequently, erasing can reduce the threshold voltage of the memory cell.

Programming the memory cells can be accomplished by applying a programming voltage to the control gate to increase the threshold voltage of the memory cell. Typically, a sampling operation, called program monitoring or program verification, is performed after the program voltage is applied to determine whether the memory cell has reached its intended threshold voltage. This process can be repeated in a number of program loops. Memory cells can be excluded from further programming after they have reached their target threshold voltage to prevent overprogramming.

US 2009 / 0 323 429 A1 discloses a method for programming non-volatile memory that reduces programming errors.

Brief description of the drawings

• 1 ist eine perspektivische Ansicht einer 3D-gestapelten nicht-flüchtigen Speichervorrichtung.
• 2 ist ein funktionelles Blockdiagramm einer Speichervorrichtung, wie beispielsweise die 3D-gestapelte nicht-flüchtige Speichervorrichtung gemäß 1.
• 3 ist ein Blockdiagramm einer Speicherstruktur, die zwei Ebenen aufweist
• 4A zeigt in einer Draufsicht einen Anteil eines Blocks von Speicherzellen.
• 4B zeigt in einer Querschnittsansicht einen Anteil eines Blocks Speicherzellen.
• 4C stellt die Ansicht der ausgewählten Gate-Schichten und Wortleitungsschichten dar.
• 4D zeigt in Querschnittsansicht eine vertikale Spalte aus Speicherzellen.
• 5A zeigt ein Flussdiagramm einer Ausführungsform eines Programmierprozesses.
• 5B illustriert beispielhaft V_T-Verteilungen, die mit Datenzuständen des Speicherzellarrays korrespondieren, wenn jede Speicherzelle drei Bits Daten speichert
• 5C illustriert, dass V_T-Verteilungen partiell überlappen können.
• 5D ist ein Flussdiagramm einer Ausführungsform eines Prozesses 500 zur Programmierung nicht-flüchtiger Speicherelemente.
• 6 ist ein Flussdiagramm einer Ausführungsform eines Prozesses 600 zur Durchführung einer intelligenten Überprüfung bzw. Verifizierung.
• 7A - /D zeigen Schwellenspannungsverteilungen während einer Ausführungsform einer intelligenten Überprüfung bzw. Verifizierung.
• 8 ist ein Flussdiagramm einer Ausführungsform eines Prozesses 800 zur Programmierung von Speicherzellen unter Verwendung einer LM-Sequenz.
• 9 ist ein Flussdiagramm einer Ausführungsform eines Prozesses 900 zur Programmierung von Speicherzellen unter Verwendung einer vollständigen Sequenz.
• 10A ist ein Flussdiagramm einer Ausführungsform eines Prozesses 1000 zur Anwendung eines Dummy-Programmierungsimpulses während einer IM-Programmierungssequenz.
• 10B zeigt V_T-Verteilungen vor einer Ausführungsform eines Prozesses 1000 aus 10A.
• 10C - 10F zeigen V_T-Verteilungen während einer Ausführungsform eines Prozesses 1000 gemäß 10A.
• 11A ist ein Flussdiagramm einer anderen Ausführungsform eines Prozesses 1100 zur Anwendung eines Dummy-Programmierungsimpulses während einer IM-Programmierungssequenz.
• 11B - 11E zeigen V_T-Verteilungen während einer Ausführungsform eines Prozesses 1100 aus 11A.
• 12A ist ein Flussdiagramm einer Ausführungsform eines Prozesses 1200 zur Programmierung von Speicherzellen in einen LM-Zustand.
• 12B zeigt Ergebnisse nach einer Ausführungsform des Prozesses 1200.
• 13A ist ein Flussdiagramm einer Ausführungsform eines Prozesses 1300 zur Programmierung unter Verwendung einer vollständigen Sequenz.
• 13B - 13H zeigen V_T-Verteilungen während einer Ausführungsform des Prozesses 1300 aus 13A.
• 14A ist ein Flussdiagramm einer Ausführungsform eines Prozesses 1400 zur Programmierung unter Verwendung einer vollständigen Sequenz.
• 14B - 14H zeigen V_T-Verteilungen während einer Ausführungsform des Prozesses 1400 aus 14A.
• 15 ist ein Flussdiagramm einer Ausführungsform eines Prozesses 1500 zur Beendigung einer vollständigen Sequenzprogrammierung.
• 16 ist ein Diagramm zur Illustration einer Ausführungsform zur Auswahl von Speicherzellen zur intelligenten Überprüfung bzw. Verifizierung.

Elements that have the same reference numbers refer to the same components or components in different drawings.

• 1 is a perspective view of a 3D stacked non-volatile memory device.
• 2 is a functional block diagram of a memory device, such as the 3D stacked non-volatile memory device according to 1 .
• 3 is a block diagram of a storage structure that has two levels
• 4A shows a portion of a block of memory cells in a top view.
• 4B shows a portion of a block of memory cells in a cross-sectional view.
• 4C represents the view of the selected gate layers and wordline layers.
• 4D shows a vertical column of memory cells in a cross-sectional view.
• 5A shows a flowchart of an embodiment of a programming process.
• 5B illustrates, by way of example, V _T distributions that correspond to data states of the memory cell array when each memory cell stores three bits of data
• 5C illustrates that V _T distributions can partially overlap.
• 5D is a flowchart of one embodiment of a process 500 for programming non-volatile memory elements.
• 6 is a flowchart of one embodiment of a process 600 for performing intelligent verification.
• 7A - /D show threshold voltage distributions during an embodiment of intelligent verification.
• 8th is a flowchart of one embodiment of a process 800 for programming memory cells using an LM sequence.
• 9 is a flowchart of one embodiment of a process 900 for programming memory cells using a complete sequence.
• 10A is a flowchart of one embodiment of a process 1000 for applying a dummy programming pulse during an IM programming sequence.
• 10B shows V _T distributions before an embodiment of a process 1000 10A .
• 10C - 10F show V _T distributions during an embodiment of a process 1000 according to 10A .
• 11A is a flowchart of another embodiment of a process 1100 for applying a dummy programming pulse during an IM programming sequence.
• 11B - 11E show V _T distributions during one embodiment of a process 1100 11A .
• 12A is a flowchart of one embodiment of a process 1200 for programming memory cells into an LM state.
• 12B shows results according to one embodiment of process 1200.
• 13A is a flowchart of one embodiment of a process 1300 for programming using a complete sequence.
• 13B - 13H show V _T distributions during one embodiment of process 1300 13A .
• 14A is a flowchart of one embodiment of a process 1400 for programming using a complete sequence.
• 14B - 14H show V _T distributions during one embodiment of process 1400 14A .
• 15 is a flowchart of one embodiment of a process 1500 for completing complete sequence programming.
• 16 is a diagram illustrating an embodiment for selecting memory cells for intelligent verification.

Detailed description

Techniques and methods for programming non-volatile memory are presented. In general, programming can consume significant amounts of power. A significant portion of the power may be consumed during the programming verification operation. One reason for this power consumption is that memory cells that have not gone through the programming check are turning on and conducting current because their threshold voltage is not yet high enough to go through the programming check. Techniques disclosed herein reduce the amount of power used during the program verification operation. A significant amount of power can also be used when setting up programming. Techniques disclosed herein reduce the amount of power used during programming conditions adjustment.

In one embodiment, intelligent verification is performed using a subset of memory cells to be programmed. By applying intelligent verification to only a subset of the memory cells electricity is saved. Intelligent verification applies a programming pulse to memory cells and then detects the subset, in one embodiment. In one embodiment, the memory cells in the group that are being programmed but for which the intelligent verification is not to be performed are excluded during the intelligent verification so that their threshold voltages are not affected by the programming pulse. They can also be excluded during capture to save electricity. One factor in reducing power consumption is that bitlines do not need to be precharged. Another factor to reduce power consumption is that these memory cells do not conduct power during the acquisition operation because they have been excluded.

The intelligent checking or verification can be used to characterize the programming of the memory cells. For example, intelligent verification may provide information to determine how quickly the memory cells are programmed. In one embodiment, intelligent verification is used to determine a magnitude of a dummy programming pulse that is applied later in the memory cell programming process. The dummy programming pulse is not followed by a programming check, reducing power consumption. The dummy programming pulse can be used to raise the threshold voltage of selected memory cells to a higher voltage before applying another programming pulse, followed by a programming check. This can reduce power consumption due to the following reasons. If the dummy programming pulse shifts the threshold voltages high enough, then these memory cells will not conduct current when checked. This reduces power consumption during program verification. A variety of techniques or methods of using dummy programming impulses are discussed.

In some embodiments, techniques disclosed herein are applied in a 3D stacked non-volatile memory device. The following example is an example of a 3D stacked storage device. Embodiments disclosed herein are not limited to this 3D example. Embodiments disclosed herein are not limited to 3D memory. For example, techniques or methods disclosed herein can also be used in 3D memory, but also in 2D NAND, but are not limited thereto. Embodiments are not limited to NAND.

The following discussion provides details of an example of a suitable structure for a memory device that can implement the proposed technology. 1 is a perspective view of a three-dimensional (3D) stacked non-volatile memory device. The memory device 100 includes a substrate 101. On and above the substrate are example blocks BLK0 and BLK1 of memory cells (non-volatile memory elements). Also on the substrate 101 is a peripheral area 104 with support circuits used by the blocks. Substrate 101 may also support circuitry beneath the blocks, along with one or more lower metal layers patterned into traces to carry signals from the circuitry. The blocks are formed in an intermediate region 102 of the storage device. In an upper region 103 of the memory device, one or more upper metal layers are patterned into conductive traces to carry circuit travel signals. Each block has a stacked area of memory cells where alternating levels of the stacks represent word lines. Although two blocks are shown as an example, additional blocks extending in the x and/or y directions can be used.

In an example implementation, the length of the plane in the x direction represents a direction in which signal traces for word lines extend (word line or SGD line direction), and the width of the plane in the y direction represents a direction in which signal traces extend for bit lines extend (bit line direction). The z-direction represents a height of the storage device.

2 is a functional block diagram of an example of a memory device such as the 3D stacked non-volatile memory device 100 1 . Memory device 100 includes one or more memories 108. Each memory 108 includes a three-dimensional memory structure 126 of memory cells (such as a 3D array of memory cells), a control circuit 110, and read/write circuits 128. The memory structure 126 is addressable by word lines via a row decoder 124 and through bit lines via a column decoder 132. The read/write circuits 128 include multiple sense blocks SB1, SB2, ..., SBp (sense circuits) and enable a page of memory cells to be read or programmed in parallel. In some systems, a controller 122 is in the same memory device device 100 (e.g. a removable memory card) such as the one or more memory dies 108 included. However, in other systems, control may be separate from memory 108. In some embodiments, a controller 122 communicates with multiple memories 108. In other embodiments, each memory 108 has its own controller. Commands and data are transferred between the host 140 and the controller 122 over a data bus 120, and between the controller 122 and the one or more memory dies 108 over lines 118. In one embodiment, memory 108 includes a set of input and/or output (I/O) pins connected to lines 118.

The memory structure 126 may include one or more arrays of memory cells, including a 3D array. The memory structure may include a monolithic three-dimensional memory structure in which multiple memory levels are formed over (rather than in) a single substrate, such as a wafer, with no intervening substrates. The memory structure may include any type of non-volatile memory that is monolithically formed in one or more physical levels of arrays of memory cells having an active region disposed over a silicon substrate. The memory structure may be in a non-volatile memory device that includes circuitry associated with the operation of the memory cells, regardless of whether the associated circuitry is above or in the substrate.

The control circuit 110 cooperates with the read/write circuits 128 to perform memory operations (e.g., erase, program, read, and others) on the memory structures 126 and includes a state machine 112, an on-chip address decoder 114, and a power control module 116. The state machine 112 provides chip-level control of memory operations. Code and parameter memory 113 may be provided to store operational parameters and software. In one embodiment, the state machine 112 is programmable by software stored in the code and parameter memory 113. In other embodiments, the state machine 112 does not use software and is entirely hardware implemented (e.g., electronic circuits).

The on-chip address decoder 114 provides an address interface between the addresses used by the host 140 or memory controller 122 and the hardware address used by the decoders 124 and 132. The power or control module 116 controls the power and voltages delivered to the word lines and bit lines during memory operations. It may include drivers for the word line layers (discussed below) in a 3D configuration, selected transistors (e.g. SGS and SGD transistors, described below) and source lines. The power control module 116 may include charge pumps to generate voltages. The capture blocks include bitline drivers. An SGS transistor is a select gate transistor at a source end of a NAND chain and an SGD transistor is a select gate transistor at a drain end of a NAND chain.

Any or any combination of control circuit 110, state machine 112, decoder 114/124/132, memory 113, power control module 116, acquisition blocks SB1, SB2, ..., SBp, read/write circuits 128, and controller 122 can be used as management or . Line circuit that performs the functions described here can be considered.

The (on-chip or off-chip) controller 122 may include a processor 122c and storage devices (memory) such as ROM 122a and RAM 122b. The storage devices include code, such as a set of instructions, and the processor 122c is capable of executing the set of instructions to provide the functionality described herein. Alternatively or additionally, processor 122c may access code from a memory device in the memory structure, such as a reserved area of memory cells connected to one or more word lines.

Multiple memory elements in memory structure 126 may be configured to be connected in series or connected such that each element is individually accessible. As a non-limiting example, flash memory devices in a NAND (NAND flash memory) configuration typically include memory elements connected in series. A NAND chain or NAND string is an example of a set of memory cells and select gate transistors connected in series.

A NAND flash memory array can be configured so that the array consists of multiple memory cells that share a single bitline and are accessed as a group. Alternatively, storage elements can be configured like this It must be ensured that each element is individually accessible or can be accessed individually, e.g. a NOR memory array. NAND and NOR configurations are exemplary, and memory cells may be configured otherwise.

The memory cells may be arranged in the individual memory device level in an ordered array, such as a plurality of rows and/or columns. However, the memory elements may be arranged in an irregular or non-orthogonal configuration or in structures that are not considered arrays.

A three-dimensional memory array is arranged so that memory cells occupy multiple levels or multiple memory device levels, thereby forming structures in three dimensions (i.e., in the x, y, and z directions, with the z direction being essentially perpendicular and the x and y directions are substantially parallel to the main surface of the substrate.

As a non-limiting example, a three-dimensional memory structure may be arranged vertically as a stack of multiple two-dimensional memory device levels. As a further non-limiting example, a three-dimensional memory array may be arranged as multiple vertical columns (e.g., columns that extend substantially perpendicular to the main surface of the substrate, for example in the y-direction), with each column having multiple memory cells. The vertical columns can be arranged in a two-dimensional configuration, for example in an xy plane, resulting in a three-dimensional arrangement of memory cells, with memory cells in multiple or several vertically stacked spoke levels. Further configurations of memory elements in three dimensions can also produce a three-dimensional memory array or form.

As a non-limiting example of a three-dimensional NAND memory array, the memory elements may be coupled together to form a vertical NAND chain that extends across multiple horizontal memory device levels. Other three-dimensional configurations are conceivable, with some NAND chains or NAND strings having storage elements in a single storage level, while other chains or strings have storage elements that extend through multiple storage levels. Three-dimensional memory arrays can also be designed in a NOR configuration and in a ReRAM configuration.

One skilled in the art will recognize that this technology is not limited to a single specific memory structure, but covers many relevant memory structures within the spirit and scope of the technology as described herein and will be understood by one skilled in the art as such.

3 is a block diagram illustrating an example of the organization of the memory structure 126, which is divided into two levels 302 and 304. Each level is also divided into M blocks. In one example, each level has approximately 2000 blocks. However, different numbers of blocks and levels can be used.

4A is a block diagram showing a top view of a portion of a block of memory structure 126. The part of the block that is in 4A shown corresponds to a part 306 in block 2 4A agree. How out 4A can be seen, extends the block that is in 4A is shown, in arrow direction 330 and in arrow direction 332. In one embodiment, the memory array has 48 layers. Other embodiments have fewer or more than 48 layers. However, shows 4A only the top layer.

4A shows a variety of circles representing vertical columns. Each of the vertical columns includes multiple select transistors and multiple memory cells. In one embodiment, each vertical column implements a NAND string. More details of the vertical columns are provided below Since the in 4A The block shown extends in the direction of arrow 330 and in the direction of arrow 332, the block contains more vertical columns than in 4A shown.

4A also shows a set of bit lines 412. 4A shows twenty-four bit lines because only a portion of the block is shown. It is contemplated that more than twenty-four bit lines are connected to the vertical columns of the block. Each of the circles representing vertical columns has an “x” to indicate its connection to a bitline.

The block that is in 4A 402, 404, 406, 408 and 410 connecting the various layers to a source line under the vertical column. Local interconnects 402, 404, 406, 408, and 410 also serve to divide each layer of the block into four regions; for example, the top layer, which is in 4A is shown divided into regions 420, 430, 440 and 450. In the layers of the block that implement memory cells, the four regions are referred to as wordline fins ger, which are separated by the local interconnects. In one embodiment, the wordline fingers connect at a common level of a block at the end of the block to form a single wordline. In another embodiment, the wordline fingers are not connected to each other at the same level. In an exemplary implementation, a bitline connects to only one vertical column from each of regions 420, 430, 440, and 450. In such an implementation, each block has sixteen rows of active columns and each bitline connects to four rows every block. In one embodiment, all four rows connected to a common bitline are connected to the same wordline (via different wordline fingers at the same level connected to each other); therefore, the management circuit uses the source-side select lines and the drain-side select lines to select one (or another subset) of the four to subject it to a memory operation (program, verify, read, and/or erase).

Although 4A shows that each region has four rows of vertical columns, four regions and sixteen rows of vertical columns in a block, these exact numbers are only an exemplary embodiment. Other embodiments may include more or fewer regions per block, more or fewer rows of vertical columns per region, and more or fewer vertical columns per block.

4A also shows the vertical columns in a staggered or staggered design. In other embodiments, different stagger patterns may be used. In some embodiments, the vertical columns are not staggered.

4B illustrates a portion of an embodiment of a three-dimensional memory structure 126, which is a cross-sectional view taken along line AA 4A shows. This cross-sectional view cuts through vertical columns 432 and 434 and through region 430 (see 4A) . The structure 4B includes two drain-side selection layers SGD1 and SGD1; two source-side selection layers SGS1 and SGS2; four dummy word line layers DWLL1a, DWLL1b, DWLL2a and DWLL2b; and thirty-two word line layers WLL0 - WLL31 for connection to data memory cells. Other embodiments may include more or less than two drain-side selection layers, more or less than two source-side selection layers, more or less than four dummy wordline layers, and more or less than thirty-two wordline layers. Vertical columns 432 and 434 are shown extending through the drain-side select layers, through the source-side select layers, through the dummy wordline layers, and through the wordline layers. In one embodiment, each vertical column includes a NAND chain. Among the vertical columns and layers listed below is substrate 101, an insulating film 454 on the substrate, and a source line SL. The NAND chain of the vertical columns 432 has a source end at the bottom of the stack and a drain end at the top of the stack. In accordance with 4A , shows 4B a vertical column 432 connected to a bit line 414 through a connector 415. Local interconnects 404 and 406 are also shown.

For easier orientation, drain-side selection layers are SGD1 and SGD1; Source-side selection layers SGS1 and SGS2; dummy word line layers DWLL1a, DWLL1b, DWLL2a and DWLL2b; and word line layers WLL0-WLL31 are collectively referred to as the line layers. In one embodiment, the conduction layers are formed from a combination of TiN and tungsten. In other embodiments, other materials may be used to form the conduction layers, such as doped polysilicon, metals such as tungsten, or metal silicates. In some embodiments, different conductive layers may be formed from different materials. Between the conduction layers are dielectric layers DL0-DL19. For example, the dielectric layer DL10 is above the word line layer WLL26 and below the word line layer WLL27. In one embodiment, the dielectric layers are made from SiO2. In other embodiments, other dielectric materials may be used to form the dielectric layers.

The memory cells are formed along vertical columns that extend through alternating conductive and dielectric layers in the stack. In one embodiment, the memory cells are arranged in NAND chains or NAND strings. The word line layers WLL0-WLL31 are connected to the memory cells (also called data memory cells). Dummy word line layers DWLL1a, DWll1b, DWll2a and DWll2b are connected to the dummy memory cells. A dummy memory cell, also called a non-data memory cell, does not store user data while a data memory cell is suitable or capable of storing user data. Consequently, data storage cells can be programmed. Drain-side selection layers SGD1 and SGD1 are used to electrically connect and disconnect NAND chains and NAND strings from the bit lines. The source-side selection layers SGD1 and SGD2 are used to connect and disconnect NAND chains and NAND strings to the source line SL, respectively.

4C represents a perspective view of the line layers (SGD1, SGD1, SGS1, SGS2, DWLL1a, DWLL1b, DWLL2a, DWLL2b and WLL0-WLL31) of the block, which is partially in 4C is shown. As above regarding 4A As mentioned, the local interconnects 401, 404, 406, 408 and 410 divide each line layer into four regions. For example, the drain-side select gate layer SGD1 (the top layer) is divided into four regions 420, 430, 440 and 450. Likewise, the word line layer WLL31 is divided into regions 460, 462, 464 and 466. For word line layers (Wll0-Wll31), the regions or areas are referred to as word line fingers; for example, the word line layer WLL31 is divided into word line fingers 460, 462, 464 and 466.

4D represents a cross-sectional view of a region or area 442 of the 4B which includes part of a vertical column 432. In one embodiment, the vertical columns are round and have four layers; however, in other embodiments, more or less than four layers may be included and other shapes may be used. In one embodiment, a vertical column 432 includes an inner core layer 470 composed of a dielectric such as SiO ₂ . Other materials can also be used. A polysilicon channel 471 surrounds the inner core 470. Materials other than polysilicon can also be used. Note that it is channel 471 that is connected to the bit line. A tunnel-capable dielectric 472 surrounds the channel 471. In one embodiment, the tunnel-capable dielectric 472 has an ONO structure. The tunnelable dielectric 472 surrounds a charge trapping layer 473, such as a specially formulated silicon nitride, that increases trap density.

4D shows the dielectric layers DLL11, DLL12, DLL13, DLL14 and DLL15, as well as the word line layers WLL27, WLL28, WLL29, WLL30 and WLL31. Each of the wordline layers includes a wordline region 476 surrounded by an aluminum oxide layer 477 surrounded by a blocking oxide (SiO ₂ ) layer 478. The physical interaction of the wordline layers with the vertical columns forms the memory cells. Thus, a memory cell has a channel 471, a tunnel-capable dielectric 472, a charge trapping layer 473, a blocking oxide layer 478, an aluminum oxide layer 477 and a word line region 476. For example, the word line layer WLL31 and a part of the vertical column 432 include a memory cell MC1. The word line layer WLL30 and a part of the vertical column 432 have a memory cell MC2. The word line layer WLL29 and a part of the vertical column 432 have a memory cell MC3. The word line layer WLL28 and a part of the vertical column 432 have a memory cell MC4. The word line layer WLL27 and a part of the vertical column 432 have a memory cell MC5.

When a memory cell is programmed, electrons are stored in a portion of the charge trapping layer 473 associated with the memory cell. These electrons are drawn into the charge trapping layer 473 of the channel 471, through the tunnelable layer 473 , in response to an appropriate voltage being applied to the wordline region 471. The threshold voltage (V _T ) of a memory cell increases proportionally with the amount of stored charge. During an erase operation, the electrons return to the channel.

5A is a flowchart describing an execution of a programming process 550 that includes one or more verification steps. Any of the programming sequences described here can be used, as well as other programming sequences. For example, process 550 may be used in an LM sequence, a full programming sequence, an intelligent verification, etc.

In step 552, the programming voltage (Vpgm) is set to an initial value. In addition, in step 552 a program counter (PC) is initialized or set to zero. In step 554, a program pulse is applied to the control gate of the memory cell. Step 554 may also include setting programming conditions on the bit lines. Bit lines associated with memory cells to be programmed may be provided with a program enable voltage; Bit lines associated with memory cells that prevent them from being programmed can be provided with a programming prevention voltage.

In step 556, a verification process is performed. In step 558 it is determined whether memory cells whose threshold voltage is at the target voltage of this memory cell have been verified or checked. It should be noted that it is not necessary for each memory cell to be verified or checked for the associated threshold voltage for a specific state. Error correction can correct for some memory cells to be below their target threshold voltage. Error correction is able to correct some memory cells that have been over-programmed. Step 558 refers to all states that have been fully programmed.

If the verification was passed, the programming process is successfully completed in step 560 (status = passed). If not all memory cells have been verified, a determination is made as to whether the program counter (PC) is less than a maximum value, such as 20. If the program counter is not less than a maximum value (step 562), then the programming process has failed (step 564). . If the program counter (PC) is less than a maximum value (e.g., 20), then the program counter (PC) is incremented by 1 and the programming voltage is increased to the next pulse increment in step 556. After step 556, the process returns to step 554 and the next programming pulse is applied to the memory cells.

At the end of a successful programming process (with verification), the threshold voltage of the memory cell should lie within one or more threshold value distributions for programmed memory cells or, accordingly, within a distribution of threshold voltages for erased memory cells. 5B shows, by way of example, V _T distributions that correspond to data states of the memory cell array when three bits of data are stored in each memory cell. However, other embodiments may use more or less than three bits of data per memory cell. This can be a logarithmic scale. The other axis represents the threshold voltage (V _T ) of the memory cells.

5B shows eight V _T distributions corresponding to a cleared state and the programmed states AG. In one embodiment, the threshold voltage in the erased state is negative and the threshold voltage in the programmed states AG is positive. However, the threshold voltage may be negative in one or more programmed states AG. Some or all of the threshold voltages in the erased state could be positive.

At or near the bottom of the threshold distribution for each programmed state is a verification reference voltage. For example shows 5B VvA for state A, VvB for state B, VvC for state C, VvD for state D, VvE for state E, VvF for state F and VvG for state G. When memory cells are programmed to a specific state , the management circuit checks whether these memory cells have a threshold voltage that is greater than or equal to the verification reference voltage.

Between each adjacent pair of V _T distributions are read reference voltages that are used to read data from the memory cell. For example shows 5B a read reference voltage VrA between the erased state and the state A, a read reference voltage VrB between the state A and the state B, a read reference voltage VrC between the state B and the state C, a read reference voltage VrD between the state C and the state D, a read reference voltage VrE between state D and state E, a read reference voltage VrF between state E and state F, and a read reference voltage VrG between state F and state G. By checking whether the threshold voltage of a particular memory cell is above or below the corresponding read reference voltage , the management circuit can determine what state the memory cell is in. For example, a memory cell whose threshold voltage is greater than VrD but less than VrE can be assumed to be in state D.

5C shows that V _T distributions can partially overlap. For example, with reference to the read level VrB, some memory cells that are in state A may have a threshold voltage greater than VrB. Also, some memory cells that are in state B may have a threshold voltage that is less than VrB. Some amount of overlap is acceptable because an error correction algorithm can handle a certain percentage of cells whose V _T is outside their intended V _T range lies.

It is noted that in some embodiments, immediately after programming, the threshold voltage distribution of those out of 5C can resemble. However, over time, the threshold voltage of the memory cells can shift, for example in such a way that an overlap can arise between the V _T distributions. A possible cause of the shift may be a charge leak in the charge storage region of the memory cell. Another possible cause of the shift may be an unintentional addition of charge to the charge storage region of the memory cells.

On the other hand, in some cases, overlap between the V _T distributions may occur immediately after programming. For example, some memory cells may be overprogrammed. An example of this is if a memory cell is programmed to state A, its threshold voltage may inadvertently go above VrB. It is also possible that underprogramming occurs. An example of this is if a memory cell is programmed into state B, its threshold voltage does not quite reach the VrB level. In either case, this does not mean that the programming has failed. As mentioned above, an error correction algorithm may handle a certain percentage of cells whose threshold voltage is not within their intended V _T distribution.

It is also noted that, as opposed to the same spacing/width of the threshold voltage distributions shown, different distributions may have different widths/spacing to account for different susceptibilities to data retention loss as well as other factors.

5D is a flowchart of one embodiment of a process 500 for programming non-volatile memory elements (eg, memory cells). Step 502 involves receiving a command to program a group of memory cells. In one embodiment, each memory cell to be programmed is associated with the same word line. In one embodiment, each memory cell to be programmed is associated with a different bit line. In one embodiment, controller 122 sends a command to memory 108 to program a group of memory cells. The command can be sent to a memory packet that contains multiple memories. Note that the memory cells are usually erased before programming. It is also noted that the group of memory cells may be in an erased state prior to process 500.

Process 500 can be used in a number of programming sequences. One example is called full sequence programming. In full sequence programming, memory cells can be programmed from the erased state to their corresponding target threshold during a single phase. One example is called LM sequence programming. In LM sequence programming, memory cells whose target threshold is the highest are first programmed from the erased state to an intermediate level in one phase. Memory cells are then programmed from either the erased state or the intermediate level to their corresponding target threshold during a second phase. There are many other programming sequences that can be used in process 500.

In a step 504, intelligent verification is performed using a subset of the memory cells that are being programmed. One embodiment of intelligent verification is discussed below. In short, during intelligent verification, the control circuitry selects a subset of memory cells to receive some amount of programming during intelligent verification. Unselected memory cells do not receive programming during intelligent verification. A variety of techniques can be used to select memory cells. The intelligent verification is used in one embodiment to determine how quickly the memory cells are programmed. For example, intelligent verification may examine the number of programming pulses and the magnitude of the program pulses needed to increase the threshold voltage of the memory cells to a target level. It should be noted that some memory cells are programmed faster than others, making this verification based on determining when a certain percentage of memory cells have reached the target level or on some other method.

In step 506, a magnitude of a dummy programming pulse is determined based on the results of the intelligent verification. Here, the term “dummy programming pulse” refers to a programming pulse that is not followed by programming verification or checking to examine the effectiveness of the dummy programming pulse. Of course a pro can Programming verification or checking can be carried out after a programming pulse that is not a dummy programming pulse is later applied. Step 506 may determine magnitudes for several different dummy programming pulses.

Step 508 includes enabling programming of selected memory cells for which intelligent verification has not been performed. In one embodiment, step 508 includes applying a voltage to the bit lines that allows memory cells associated with those bit lines to be programmed. In this step, the selected memory cells do not necessarily include all of the memory cells that will ultimately be programmed in this process. In one example, memory cells that are to be programmed to a data state near an intelligent verification level (and for which intelligent verification has not been performed) are selected. In one example, memory cells that are to be programmed to an intermediate state (and for which intelligent verification has not been performed) are selected. In one example, memory cells that are to be programmed to a particular state (and for which intelligent verification has not been performed) are selected. In one example, memory cells that are to be programmed to some state (and for which intelligent verification has not been performed) are selected. Some memory cells for which intelligent verification has been carried out can also be released for programming. For example, memory cells that are to be programmed to a state that is significantly above an intelligent verification level can be released for programming. Many examples are described here.

Step 510 includes preventing programming of selected memory cells for which the intelligent check was performed. In one embodiment, it may include, but is not limited to, that memory cells be programmed to a state near an intelligent verification level. One reason for this selection is to prevent over-programming of these memory cells, which are part of intelligent verification and should be programmed to a state close to the intelligent verification reference level. It is noted that not all memory cells for which intelligent verification was performed are excluded in some embodiments. Other memory cells for which intelligent verification has not been performed may also be prevented from being programmed. For example, memory cells that remain in the erased state may be prevented from being programmed. Also, any memory cell that was not selected in step 508 could be prevented from being programmed in step 510. In one embodiment, step 510 includes applying a voltage to the bitlines that prevents memory cells associated with those bitlines from being programmed.

Step 512 involves applying a dummy programming pulse (e.g., a voltage pulse) to the memory cells in the group. In one embodiment, the dummy programming voltage pulse is applied to the word line associated with the group of memory cells. In one embodiment, the dummy programming pulse is applied to the control gate of each of the memory cells in the group. Step 512 may include applying more than one dummy programming pulse to the memory cells. It is noted that in a case where more than one dummy pulse is applied, the memory cells that have been enabled and those that have been prevented from being programmed may be changed.

Step 514 involves continuing to program the memory cells. Step 514 may include applying a programming pulse followed by performing a programming verification. This pattern can be repeated until the programming of the group of memory cells is complete. Accordingly, a process that could 5A same, can be used.

6 is a flowchart of an execution of a process 600 of executing intelligent verification. This information can be used to determine a magnitude of a dummy programming pulse. Process 600 is an embodiment of step 504 of process 500. In one embodiment, intelligent verification is used when programming the memory cells to an intermediate state. This can also be called programming a lower page of data. In this example, the intelligent verification reference level may be a verification level associated with the intermediate state. In this case, the memory cells used in the intelligent verification ation or verification are those that are to be programmed to the states D, E, F and G. In one embodiment, intelligent verification is used during full sequence programming. In this example, the intelligent verification reference level may be a verification level associated with the lowest data state (e.g., state A). It should be noted that the intelligent verification level may not be exactly at these levels for reasons discussed below. In the full sequence example, the memory cells involved in intelligent verification may include those to be programmed to states A, B, C, D, E, F, and G. It should be noted that these are just two examples. Intelligent verification can also be used if the V _T distribution has more or fewer than eight states at the end of programming.

In step 602, conditions are set on a first set of bitlines to enable programming. This first set of bit lines is associated with the memory cells that are programmed during intelligent verification. In one embodiment, a programming enable voltage is applied to the first set of bit lines. This is a voltage that connects the NAND chains of selected memory cells to the bit line in one embodiment. This allows this voltage to turn on or activate a drain-side select gate.

In one embodiment, the memory cells in step 602 include a subset of memory cells to be programmed to states D, E, F, and G. In one embodiment, the memory cells include a subset of memory cells to be programmed to states A, B, C, D, E, F and G. A different data set can be used. It is noted that only selecting a subset of memory cells can significantly reduce power consumption.

In step 604, conditions are set on a second set of bitlines to prevent programming. This second set of bit lines is associated with the memory cells that are not to be programmed during intelligent verification. In one embodiment, a program prohibition voltage is applied to the second set of bit lines. This is a voltage that isolates the NAND strings of non-selected memory cells from the bit line in one embodiment. Thus, this voltage can turn off or deactivate a drain-side selection gate.

In step 606, a programming pulse is applied to control gates of the memory cells. In one embodiment, the programming pulse is applied to a wordline associated with the memory cells. Note that in some architectures, the wordline is connected to the control gate of all of the memory cells in the group The programming pulse may be applied to the control gate of all of the memory cells in the group because bitline conditions may prevent programming where it is not desired. However, it is not necessary that the programming pulse be applied to the control gate of memory cells that are not part of the intelligent verification.

In step 608, a V _T verification is performed at an intelligent verification reference level. This may include applying a reference voltage to the control gate of the memory cells and sampling the bit lines in response. Note that it is not necessary that bitlines associated with all memory cells in the group be sampled. Therefore, it is not necessary to build up sampling voltages on all the bit lines that can store current and/or energy. Thus, in one embodiment, the control circuitry excludes from scanning all memory cells in the group that are different from those of the subset selected for intelligent verification. Excluding sampling may include not precharging the bitlines to a level that allows sampling. Memory cells that are to be scanned may have their bitlines precharged to a level that allows scanning.

In step 610, it is determined whether the intelligent verification is completed. Referring to 7A Initially, all of the memory cells are in the erased state 702. After the first programming pulse is applied, the threshold voltage of the memory cells whose bit lines have been activated moves up. This is done by the intelligent verification distribution 704 in 7B represented. The erase distribution 702 now contains fewer memory cells.

In one embodiment, the control circuit determines whether a sufficient number of memory cells have passed or gone through the intelligent verification or checking. Step 610 may check whether the fastest programmed memory cells have reached the intelligent verification level. Therefore, step 610 can occur even if many of the slower programmed memory cells have not yet reached the intelligent verification level. Note that some of the memory cells whose bit lines have been activated may be excluded from checking in step 610. For example, some memory cells are not representative of typical programming speed, but are included to provide better results for those memory cells that are representative of typical programming speed. In one example, in a 2D NAND, the control circuitry could activate memory cells in groups of four adjacent NAND strings (in step 602). There may be multiple (or many) NAND chains or NAND strings between each of the four groups that are not enabled. In this case, the memory cells on the two inner NAND chains or NAND strings in each group of the four may be representative of the typical programming conditions. This allows the bit lines of the two inner NAND chains or NAND strings to be sampled in step 610. However, the memory cells on the two outer NAND strings in each group of four may not be representative of typical programming conditions. One reason for this is that they have a neighbor that is not the subject of the programming. This means that the bit lines of the two outer NAND chains or NAND strings can be excluded or excluded from the scanning in step 610.

The process 600 then proceeds to step 606 to apply another programming pulse to the control gates of the memory cells, assuming that the intelligent verification has not yet been completed. This programming pulse may have the same properties as the previous one, or the properties can change. For example, the programming pulse may have the same magnitude as the previous one, or the magnitude may be increased. Another option is to change the duration of the programming pulse. For example, the programming pulse could be longer than the process duration. A combination of changing the magnitude or size and changing the duration or running time can be used.

The 7B - 7D show the results after each additional programming pulse has been applied. After the intelligent verification level (Vsm) is reached (step 610 = yes), information regarding the intelligent verification is recorded in step 614. It is noted that in 7D the intelligent verification or checking is completed when the fastest programmed memory cells have reached the intelligent verification level (Vsm). In one embodiment, the number of programming pulses applied to achieve the intelligent verification level is recorded. In one embodiment, information about the magnitude of the programming pulse is recorded. For example, the magnitude of the last programming pulse could be recorded in an embodiment in which the magnitude changes during the process. In one embodiment, the control circuit determines an appropriate magnitude for a start programming pulse based on the results of the intelligent verification. Thus, the recorded information could be a voltage magnitude of a dummy programming pulse. The information may be a number such as one, two, three..., identifying the number of programming loops used to program the fastest memory cells to a starting value, the magnitude of a programming voltage used to do so was used to program the fastest memory cells to a starting value, etc. It should be noted that process 600 is one embodiment that can be used to determine how quickly the memory cells are programmed, but other techniques can also be used become.

The recorded information may be stored externally to the memory array 126, for example in code/parameters 113. Or the information may be stored externally to the memory 108. An advantage of storing the information in the non-volatile memory cells of the memory array is that the information is not lost if a power failure occurs in the storage device or if the information is overwritten when another block is programmed. In contrast, a data register typically uses volatile memory, such as RAM, in which data is lost in the event of a power failure. Another advantage of storing information in non-volatile memory cells is that they are cheaper than RAM.

8th is a flowchart of one embodiment of a process 800 for programming memory cells using an LM sequence. Process 800 is in an LM sequence used, which includes an intermediate state (IM) in one embodiment. Process 800 is an embodiment of steps 506-512 of process 500. It is noted that intelligent verification of a subset of the memory cells may thus be performed prior to process 800.

In step 802, a magnitude for one or more dummy programming pulses is determined based on the results of the intelligent verification. In one embodiment, a magnitude is suitable for raising a threshold voltage from the erased state to near state D without overprogramming beyond state D. This can be conservative to prevent or avoid over-programming. Likewise, magnitudes can be determined that are suitable for raising threshold voltages from the erased state to the vicinity of states E, F or G, whereby the respective states can again be determined without overprogramming. Instead of going directly from the erased state to state E, the programming could go from the erased state to near state D, and then to state E. Many more examples are possible. Further details are discussed below.

In step 804, of the memory cells to be programmed to a level near the intelligent verification level, those that did not participate in the intelligent verification are enabled for programming. In one embodiment, state D is near the intelligent verification level. Therefore, of the memory cells to be programmed into state D, those that did not participate in intelligent verification may be released in step 804. However, instead, the threshold level of another state may be considered to be close to the intelligent verification level. A data state can be defined as being near the intelligent verification level based on the verification levels. For example, if the intelligent verification level within a state is below the specified state, it is considered to be close. For example, if the intelligent verification level is between VvC and VvD, then it is considered to be close to state D. However, the intelligent verification level can be slightly above the state and still be considered close. It is noted that additional memory cells can also be released in step 804. For example, memory cells that are to be programmed to a data state above state D can be released for programming. In general, memory cells that are to be programmed into a data state above the above-mentioned state near the intelligent verification level can be released.

In step 806, of the memory cells to be programmed to a level near the intelligent verification level, those that participated in the intelligent verification are excluded from programming. It is noted that other memory cells may also be excluded from programming in step 806.

In step 808, one or more dummy programming pulses are applied to the control gates of the memory cells. It should be noted that there is no programming verification to verify the results of the dummy programming pulses. It should also be noted that if more than one dummy programming pulse is applied, the memory cells enabled for programming and those excluded from programming may change. It is also noted that if more than one dummy programming pulse is applied, the magnitude of the dummy programming pulse may differ from the others depending on how much movement of V _T is desired. This is done with reference to the 10 and 11 explained further.

9 is a flowchart of one embodiment of a process 900 for programming memory cells using a complete sequence. Process 900 is an embodiment of steps 506-512 of process 500. It is noted that this allows intelligent verification of a subset of the memory cells to be performed prior to process 900.

In step 902, a magnitude of one or more dummy programming pulses is determined based on the results of the intelligent verification. In one embodiment, an appropriate dummy programming pulse is determined for different states. For example, if the memory cells are to be programmed to a state A via a state G, a suitable dummy programming pulse can be used to program the erased state to the State A, or the deleted state, can be determined directly to state B, etc. Another possibility is to provide a dummy pulse whose goal is to program the erased state to state A, and then provide a dummy from the previous resulting distribution for programming to state B, etc. Further details are discussed below.

In step 904, memory cells that did not participate in intelligent verification and that are to be programmed to a selected set of states are enabled for programming. For example, memory cells that are to be programmed into state A through state G can be released. A smaller set of the data states could be selected. It may be desirable to select those to be programmed to the higher threshold voltage states, as greater power savings may be gained in the overall programming process to dummy program the higher threshold voltage states. The term “dummy programming” refers to the application of one or more dummy programming pulses to a memory cell that has been enabled for programming.

In step 906, memory cells that were not selected in step 904 are excluded from programming. These memory cells may include both those that participated in the intelligent verification and those that did not participate in the intelligent verification but were not selected in step 904.

In step 908, one or more dummy programming pulses are applied to the control gates of the memory cells. Again, note that no programming verification is performed to verify the results of the dummy programming pulses. It should also be noted that if more than one dummy programming pulse is applied, the memory cells enabled for programming and those excluded from programming may change between the dummy pulses. This will be further discussed with reference to the 13 and 14 explained.

10A is a flowchart of one embodiment of a process 1000 of applying dummy pulses during an IM programming sequence. Process 1000 is an embodiment of steps 804 - 808 from process 800. Thus, intelligent verification may be performed prior to process 1000. 10B shows V _T distributions before an embodiment of the process 1000. The verification reference levels VvA, VvB, VvC, VvD, VvE, VvF and VvG are also shown as examples. A delete distribution 702 and an intelligent verification distribution 1050 are shown there. In this embodiment, the intelligent verification distribution 1050 has been programmed so that the fastest programmable memory cells are at or below the state D (VvD) verification level. The intelligent verification distribution 1050 could be programmed for a higher or lower V _T. One reason why the intelligent verification level is kept lower is that the V _T of the memory cells can shift upward when an adjacent memory cell is programmed. By setting the intelligent verification level below VvD, overprogramming of the memory cells in state D can be prevented. However, it is noted that these effects are architecture dependent and it may not always be necessary to have the intelligent verification level below VvD. In another embodiment, the intelligent verification distribution 1050 is programmed to a verification level associated with an intermediate data state (e.g., VLM). In another embodiment, the intelligent verification distribution 1050 is programmed to a level slightly below the VLM, for the reasons just discussed. lies. Other verification levels may be used for intelligent verification distribution 1050. For clarity, the process 1000 is based on the example intelligent verification distribution 1050 shown in 10B is shown, explained.

It should also be noted that the magnitudes of the dummy programming pulses may have already been determined in step 802 from process 800. Process 1000 is for an embodiment that has eight data states. Process 1000 can be modified to accommodate fewer or more data states. In process 1000, it is assumed that all of the memory cells are associated with the same word line.

In step 1002, memory cells remain in the erased state and those to be programmed into states A, B and C are excluded. In step 1004, of the memory cells to be programmed into state D, those that participated in the intelligent verification are excluded. Also the memory cells in state D that did not take part in the intelligent verification or checking are released for programming. It is noted that these memory cells are protected by intelligent verification distribution 1050 in 10B be represented. Steps 1002-1004 are expressed this way for clarity. Another way to describe this is that all memory cells that have participated in intelligent verification are excluded and all of those that are to be programmed to a state A, B or C are also excluded.

In step 1006, the memory cells to be programmed to states E, F and G are enabled for programming. Enabling programming can be done by specifying conditions on the associated or connected bit lines that enable programming.

In step 1008, a first dummy programming pulse is applied to the word line associated with the group of memory cells. 10C shows an example of a V _T distribution after step 1008. The distribution 1052 affects the memory cells that are to be programmed to the D, E, F or G state and that were not involved in the intelligent verification. The magnitude of the dummy pulse was chosen to attempt to obtain the threshold voltages near the verification level VvD for state D in this example. The distribution 1052 can be very wide due to the different programming speeds of the individual memory cells. This means that some memory cells can shift their V _T significantly or significantly more than the others. The magnitude of the dummy pulse was determined based on how quickly the memory cells were programmed during intelligent verification in one embodiment. In this example, some of the memory cells could have a V _T above VvD, but this is not required. So the distribution could be 1052 lower. On the other hand, the distribution could be higher. If the V _T of memory cells rises above VvE, then they may be overprogrammed (for the cells in state D). Thus, it could be advantageous to prevent a significant portion of the distribution 1052 from rising above VvE. This can be achieved by being fairly conservative with the dummy programming pulse. As also mentioned above, in some memory architectures, the V _T of a memory cell can be determined by the capacitive coupling with a neighbor that is programmed later appears to increase. This effect can be taken into account when determining a suitable magnitude of the dummy programming pulse. The distribution 1050 now only represents the cells in state D that took part in the intelligent verification. Distribution 1051 represents the cells in states E, F and G that participated in intelligent verification.

In step 1010, memory cells in state D are excluded from further programming. In step 1012, a second dummy programming pulse is applied to the word line associated with the group of memory cells. 10D shows an example of V _T distributions after step 1012. Distribution 1054 concerns the memory cells to be programmed to the E, F or G state. This includes those previously in the 1051 and 1052 distribution. Consequently, some of the cells in state E, F or G are programmed from distribution 1051 to distribution 1054. Others are programmed from the 1052 to 1054 distribution. The magnitude of the dummy pulse can be selected in such a way that an attempt is made to get close to the verification level VvE of state E with the threshold voltages. The magnitude is determined based on how quickly the memory cells are programmed during intelligent verification in one embodiment. In this example, some of the memory cells have a V _T above VvE, but this is not necessary. So the distribution 1054 could be lower or higher.

Distribution 1053 represents cells in state D from distributions 1050 and 1052. That is, distribution 1053 represents all cells in state D. Note that distribution 1053 from 10C compared to the distribution 1052 in 10D has shrunk.

In step 1014, memory cells in state E are excluded from further programming. In step 1016, a third dummy programming pulse is applied to the word line associated with the group of memory cells. 10E shows an example of a V _T distribution after step 1016. Distribution 1056 concerns the memory cells to be programmed to states F or G. The magnitude of the dummy pulse was chosen to come close to the verification level VvF of state F with the threshold voltages. The magnitude was determined based on how fast the memory cells protruded during intelligent verification in one embodiment were grammed. In this example, some of the memory cells have a V _T above VvF, but this is not necessary. Consequently, the 1056 distribution could be lower or higher. It is noted that the distribution is 1054 10D compared to the distribution 1054 10E has shrunk because the distribution 1054 now only contains memory cells in state E.

In step 1018, memory cells in state F are excluded from further programming. In step 1020, a fourth dummy programming pulse is applied to the word line associated with the group of memory cells. 10F shows an example of V _T distributions after step 1020. Distribution 1058 has the memory cells to be programmed to state G. The magnitude of the dummy pulse was selected to come close to the verification level VvG of state G with the threshold voltages. The magnitude of the dummy pulse was determined based on how quickly the memory cells were programmed during intelligent verification in one embodiment. In this example, some of the memory cells have a V _T above VvG, but this is not necessary. So the distribution could be 1058 lower or higher. It is noted that the distribution is 1056 10E compared to the distribution 1056 10F has shrunk.

The result 10F is that most of the V _T of the memory cells programmed to the E, F and G states have increased above VvD. This can save power when programming to an intermediate state, as explained below. However, prior to this explanation, another embodiment will be discussed that may result in V _T distributions similar to those of 10F is.

11A is a flowchart of another embodiment of a process 1100 of applying dummy pulses during an IM programming sequence. Process 1100 is an embodiment of steps 804 - 808 from process 800. Thus, the intelligent verification can be performed before process 1100. Thus the V _T distributions are off 10B also applicable to the conditions prior to an embodiment of the process 1100. The magnitudes of the dummy programming pulse for process 1100 were also already determined in step 802 from process 800. Process 1100 is for an embodiment that has eight data states. The process 1100 can be modified to accommodate fewer or more data states. In process 1100, it is assumed that all memory cells are associated with the same word line.

In step 1102, memory cells that are to remain in the erased state and those that are to be programmed to the A, B, C, E, F and G states are excluded. In step 1104, programming the memory cells to state D, those who participated in the intelligent verification are excluded. Steps 1002 - 1004 are expressed this way for ease of explanation. Another way of saying this is that all memory cells that have participated in the intelligent verification are excluded, and those that are to be programmed to the states A, B, C, E, F and G, just like those that should remain in the deleted state should also be excluded.

In step 1106, programming the memory cells to state D, those that did not participate in intelligent verification are enabled for programming. Enabling programming can be achieved by setting conditions for the associated bit lines that enable programming.

In step 1108, a first dummy programming pulse is applied to the word line associated with the group of memory cells. 11B shows an example of V _T distributions after step 1108. Distribution 1152 concerns the memory cells that are to be programmed to state D and that were not involved in the intelligent verification. The magnitude of the dummy pulse was selected to come close to the verification level VvD of state D with the threshold voltages. The magnitude of the dummy pulse is determined in one embodiment based on how quickly the memory cells were programmed during intelligent verification. Consequently, the distribution 1152 could be lower or higher. The distribution 1150 refers to the memory cells in states D, E, F and G that were included in the intelligent verification.

In step 1110, all memory cells in state D are excluded. In addition, the memory cells in state E are released for programming. Those remaining in the erased state and those to be programmed to states A, B, C, F, and G remain in the excluded state.

In step 1112, a second dummy programming pulse is applied to the word line associated with the group of memory cells. 11C shows an example of V _T distributions after step 1112. Distribution 1154 concerns the memory cells that are to be programmed to the E state. Some of these memory cells come from the intelligent verification distribution 1150 (from 11B) , others from erase distribution 702. Distribution 1151 contains memory cells in states D, F and G that were in intelligent verification. The magnitude of the dummy pulse was chosen to get the threshold voltages close to the verification level VvE of state E. The magnitude was determined based on how quickly the memory cells were programmed during intelligent verification in one embodiment. In this example, some of the memory cells have a V _T above VvE, but this is not necessary. The distribution 1154 could therefore be lower or higher.

In step 1114, all memory cells in state E are excluded. In addition, the memory cells in state F are released for programming. Those intended to remain in the erased state and those to be programmed to states A, B, C, D, and G remain in the excluded state.

In step 1116, a third dummy programming pulse is applied to the word line associated with the group of memory cells. 11D shows an example of V _T distributions after step 1112. Distribution 1156 concerns the memory cells to be programmed to the F state. Some of these memory cells come from erase distribution 702, others come from distribution 1151. Distribution 1155 contains the cells in state(s) D and G that participated in intelligent verification (previously in distribution 1151). The magnitude of the dummy pulse was chosen to get the threshold voltages close to the verification level VvF of state F. The magnitude was determined based on how quickly the memory cells were programmed during intelligent verification in one embodiment. In this example, some of the memory cells have a V _T above VvF, but this is not necessary. The distribution 1156 could therefore be lower or higher.

In step 1118, all memory cells in state F are excluded. In addition, memory cells in state G are released for programming. Those remaining in the erased state and those to be programmed to states A, B, C, D, and E remain in the excluded state.

In step 1120, a fourth dummy programming pulse is applied to the word line associated with the group of memory cells. 11E shows an example of V _T distributions after step 1120. Distribution 1158 concerns the memory cells to be programmed into the G state. Some of the cells are from deletion distribution 702, others are from distribution 1155. Figure 1155 is in 11E Not shown. Distribution 1159 represents all cells in state D (including those previously in distributions 1155 and 1152). The magnitude of the dummy pulse was chosen to get the threshold voltage close to the verification level VvG of state G. The magnitude was determined based on how quickly the memory cells were programmed during intelligent verification in one embodiment. In this example, some of the memory cells have a V _T above VvG, but this is not necessary. The distribution 1158 could therefore be lower or higher.

It is noted that results from 11E after process 1100 the results 10F according to process 1000 can be the same or similar. Other variations are possible. For example, according to the results 10C , in which the cells in states D, E, F and G are in a distribution 1052, a dummy pulse is used to bring the cells in state E close to VvE, the cells in state F close to VvF (using a dummy pulse) and to get or push the cells in state G close to the VvG (using a dummy pulse).

12A is a flowchart of one embodiment of a process 1200 of programming memory cells to an LM state. Process 1200 can be used after process 1000 or 1100 has been performed. In step 1202, conditions are set on the bit lines to enable programming of the memory cells to be programmed into the D, E, F and G states. In step 1204, conditions are set on the bit lines to prevent programming of the memory cells that are to remain in the erased state as well as those that are to be programmed to the A, B and C states.

In step 1206, a programming voltage is applied to the word line. In step 1208, a programming verification operation is performed. In step 1210, it is determined whether LM programming is complete. This step may check whether a sufficient number of the memory cells have a V _T greater than the LM state. If not, then the process continues at step 1212. In step 1212, memory cells that have passed LM verification are excluded. Process 1200 then continues at step 1206. After step 1210 indicates that programming of the LM state is complete, the process is terminated.

12B shows results after process 1200. The LM distribution 1226 is shown immediately above the LM verification level (VLM). The distribution 1254 refers to the memory cells that are in the distribution 1054 10F were. It is noted that some of the memory cells in the distribution are 1054 10F were, perhaps programmed a little, and are now shown as part of the LM distribution 1226. Similar reasons can apply to distributions 1056 and 1058 10F apply. However, it is possible for a distribution to be made 10F is or was so high that no memory cell was programmed during process 1200. The distribution is 1052 10F has no corresponding distribution 12B . For purposes of discussion, assume that all memory cells in distribution 1052 are now in LM distribution 1226.

It is also noted that some of the memory cells that were in the intelligent verification distribution 1050 are now in the LM distribution 1226. This means that memory cells that are to be programmed into states D, E, F and G and which participated in the intelligent verification have been programmed from the distribution 1050 into the LM distribution 1226.

The discussion above compares the V _T distributions 10F with those of 12B . Similar justifications concern the V _T distributions 1152, 1154, 1156 and 1158 11E .

It is noted that a significant amount of power is saved in process 1200 due to the following reasons. Many of the memory cells in distributions 1054, 1056 and 1058 10F can be excluded from the process at an early stage. This reduces the total BL capacity or capacitance that must be precharged during the programming process. This can save a significant amount of power when programming conditions are specified. Also during program verification in process 1200, they will not conduct current because their V _T is above the LM verification level. This saves additional power during program verification or verification.

After process 1200, the LM programming sequence may be completed by programming all memory cells to their final states. This can involve programming the memory cells from the LM distribution 1226 to one of the states D, E, F or G; programming the memory cells from distribution 1254 to state E; programming the memory cells from distribution 1256 to state F; and programming the memory cells from distribution 1258 to state G. Additionally, some of the memory cells in the erased state 702 are programmed to states A, B, or C. The above programming can be done in a single phase or in multiple phases.

13A is a flowchart of one embodiment of a process 1300 of programming using a complete sequence. Process 1300 is an embodiment of steps 904 - 908 from process 900. Thus, intelligent verification may be performed prior to process 1300. It should be noted that the intelligent verification level may differ from those used in processes 1000 and 1100. A possible verification level of the process 1300 is at the verification level (VvA) of state A. However, as described above, the intelligent verification level may be slightly below the verification level (VvA) of state A in order to accommodate any V _T shift of the memory cells that may occur to take into account subsequent programming of an adjacent memory cell. As mentioned, this effect or impact may depend on the memory architecture.

The magnitudes for the dummy programming pulse of process 1300 may also have already been determined in step 902 of process 900. Process 1300 is for an embodiment with eight data states. The process 1300 can be modified to accommodate fewer or more data states. In process 1300, it is assumed that all of the memory cells are associated with the same word line.

In step 1302, the memory cells that are to remain in the erased state are excluded. Memory cells in state A that have undergone intelligent verification can also be excluded. In step 1304, memory cells to be programmed to states B through G are enabled for programming. Memory cells in state A that did not take part in the intelligent verification or checking are also released for programming. In step 1306, a dummy programming pulse is applied to the word line. The magnitude or size of this dummy pulse can be determined based on the intelligent verification or checking. 13B shows the results according to one embodiment of step 1306. 13B shows an erase distribution 702 and a distribution 1352. The distribution 1352 includes those memory cells that are programmed from the erase state 702. For the sake of clarity, an intelligent verification distribution is included in 13B Not shown.

In step 1308, memory cells that are to be programmed to state A are excluded. The memory cells that are to remain in the erased state remain in the excluded state. The memory cells that are to be programmed into states B to G remain in the state enabled for programming. In step 1310, a dummy programming pulse is applied to the word line. The magnitude of this dummy pulse can be determined based on the intelligent verification. 13C shows results according to one embodiment of step 1310. 13C shows distribution 1354, which represents the memory cells in states B through G that were programmed from distribution 1352. The distribution 1352 now only contains the memory cells in state A.

In step 1312, memory cells to be programmed to state B are excluded. Other memory cells remain in their previous state. In step 1314, a dummy programming pulse is applied to the word line. The magnitude of this dummy pulse can be determined based on the intelligent verification. 13D shows results according to one embodiment of step 1314. 13D shows distribution 1356, which represents the memory cells in states C through G that were programmed from distribution 1354. The distribution 1354 now only contains the memory cells in state B.

In step 1316, memory cells that are to be programmed to state C are excluded. Other memory cells remain in their previous states. In step 1318, a dummy programming pulse is applied to the word line. The magnitude of this dummy pulse can be determined based on the intelligent verification. 13E shows results according to one embodiment of step 1318. 13E shows distribution 1358, which represents the memory cells in states D through G that were programmed from distribution 1356. The distribution 1356 now only contains the memory cells in state C.

In step 1320, memory cells that are to be programmed to state D are excluded. Other memory cells remain in their previous states. In step 1322, a dummy programming pulse is applied to the word line. The magnitude of this dummy pulse can be determined based on the intelligent verification. 13F shows results according to one embodiment of step 1322. 13F shows distribution 1360, which represents the memory cells in states E through G programmed from distribution 1358. The distribution 1358 now only contains the memory cells in state D.

In step 1324, memory cells that are to be programmed to state E are excluded. Other memory cells remain in their previous states. In step 1326, a dummy programming pulse is applied to the word line. The magnitude of this dummy pulse can be determined based on the intelligent verification. 13G shows results according to one embodiment of step 1318. 13G shows distribution 1362, which represents the memory cells in states F through G that were programmed from distribution 1360. The distribution 1360 now only contains the memory cells in state E.

In step 1328, memory cells that are to be programmed to state F are excluded. Other memory cells remain in their previous states. In step 1330, a dummy programming pulse is applied to the word line. The magnitude of this dummy pulse can be determined based on the intelligent verification. 13H shows results according to one embodiment of step 1330. 13H shows distribution 1364, which represents the memory cells in states G programmed from distribution 1362. The distribution 1360 now only contains the memory cells in state F.

14A is a flowchart of one embodiment of a process 1400 of programming using a complete sequence. In process 1400, the dummy programming pulse advances the V _T directly from the erased state to near its intended programming state. Process 1400 is an embodiment of steps 904 - 908 from process 900. Thus, intelligent verification may be performed prior to process 1400. In one embodiment, the intelligent verification level is at the AvV level, or slightly below the AvV level. The magnitudes of the dummy programming pulse of process 1400 may have already been determined in step 902 of process 900. Process 1400 is for an eight data state embodiment. The process 1400 can be modified to accommodate fewer or more data states. In process 1400, it is assumed that all of the memory cells are associated with the same word line.

In step 1402, the memory cells that are to remain in the erased state and in states B through G are excluded. In addition, the memory cells in state A that took part in the intelligent verification can be excluded. In step 1404, the memory cells to be programmed into state A that did not participate in the intelligent verification are enabled for programming. In step 1406, a dummy programming pulse is applied to the word line. The magnitude of this dummy pulse can be determined based on the intelligent verification. 14B shows the results according to one embodiment of step 1406. 14B shows an erase distribution 702 and a distribution 1452. The distribution 1452 contains the memory cells in state A that were programmed from the erase state 702. The distribution 1452 may also include the memory cells in states A through G that were programmed during intelligent verification.

In step 1408, the memory cells to be programmed to state A are excluded. The memory cells that are to be programmed to state B are released for programming. Other memory cells remain in the excluded state. In step 1410, a dummy programming pulse is applied to the word line. The magnitude of this dummy pulse can be determined based on the intelligent verification. 14C shows the results according to one embodiment of step 1410. 14C shows a distribution 1454 representing the state B memory cells programmed from the erase state 702.

In step 1412, the memory cells to be programmed to state B are excluded. The memory cells that are to be programmed to state C are released for programming. Other memory cells remain in the excluded state. In step 1414, a dummy programming pulse is applied to the word line. The magnitude of this dummy pulse can be determined based on the intelligent verification. 14D shows the results according to one embodiment of step 1414. 14D shows a distribution 1456 representing the state C memory cells programmed from the erase state 702.

In step 1416, the memory cells to be programmed to state C are excluded. The memory cells that are to be programmed to state D are released for programming. Other memory cells remain in the excluded state. In step 1418, a dummy programming pulse is applied to the word line. The magnitude of this dummy pulse can be determined based on the intelligent verification. 14E shows the results according to one embodiment of step 1418. 14E shows a distribution 1458 representing the memory cells of state D that were programmed from the erase state 702.

In step 1420, the memory cells to be programmed to state D are excluded. The memory cells that are to be programmed to state E are released for programming. Other memory cells remain in the excluded state. In step 1422, a dummy programming pulse is applied to the word line. The magnitude of this dummy pulse can be determined based on the intelligent verification. 14F shows the results according to one embodiment of step 1422. 14F shows a distribution 1460 representing the memory cells of state E that were programmed from the erase state 702.

In step 1424, the memory cells to be programmed to state E are excluded. The memory cells that are to be programmed to state F are released for programming. Other memory cells remain in the excluded state. In step 1426, a dummy programming pulse is applied to the word line. The magnitude of this dummy pulse can be determined based on the intelligent verification. 14G shows the results according to one embodiment of step 1426. 14G shows a distribution 1462 representing the memory cells of state F that were programmed from the erase state 702.

In step 1428, the memory cells to be programmed to state F are excluded. The memory cells that are to be programmed to state G are released for programming. Other memory cells remain in the excluded state. In step 1430, a dummy programming pulse is applied to the word line. The magnitude of this dummy pulse can be determined based on the intelligent verification. 14H shows the results according to one embodiment of step 1430. 14H shows a distribution 1464 representing the memory cells of state G that were programmed from the erase state 702.

15 is a flowchart of a process 1500 of completing complete sequence programming. This process can be done after process 1300 or 1400. The process 1500 can begin with the V _T distributions like the examples from 13H or 14H look, but is not limited or limited to these examples. A goal of one embodiment of process 1500 is to tighten V _T distributions. In step 1502, memory cells to be programmed to states A through G are enabled for programming. Memory cells in the erase state can be excluded. In one embodiment, information about the V _T of the memory cells is maintained during intelligent verification so that some of the memory cells in states A to G can be excluded to prevent possible overprogramming.

In step 1504, a programming voltage is applied to the word line associated with the memory cells. In step 1506, programming verification is performed at the various levels (e.g., VvA, VvB, VvC, VvD, VvE, VvF, Vvg). In step 1508, memory cells that have passed verification for their respective states are excluded from further programming. Step 1510 determines whether programming is complete. This check can only be based on a certain number of memory cells that fail program verification. The programming voltage (Vpgm) is increased in step 1512 if programming is not complete. The process returns to step 1504 if programming is not complete.

It is noted that power consumption during the process 1500 can be significantly reduced. Because many of the memory cells have such a high V _T at the beginning of process 1500, they will not conduct current when verifying at many of the verification reference levels. This is in contrast to a conventional or traditional process. Recall that processes 1300 and 1400 apply dummy pulses. Consequently, no power was used or consumed during programming verification in these processes 1300 and 1400.

16 is a diagram of a part of 4A . The region between local interconnects 404 and 406 is shown. 16 shows a technique for selecting the memory cells that participate in intelligent verification. The memory cells are numbered 1 - 8. This numbering may refer to how they are addressed. The memory cells labeled 1, 2, 7, or 8 are closer to the local interconnects 404, and 406. These are referred to as “outer memory cells.” The memory cells labeled 3, 4, 5, and 6 are further away from the local interconnects. These are called “internal memory cells”. The programming characteristics (e.g. speed) of the inner memory cells may differ from those of the outer memory cells.

In one embodiment, memory cells are selected for intelligent verification based on whether they are inner or outer memory cells. For example, inner memory cells could be selected for intelligent verification while the outer memory cells are not selected. Alternatively, outer memory cells can be selected for intelligent verification while the inner memory cells are not selected. One possible reason for this is that memory cells that can be programmed more quickly are selected for intelligent verification. Selecting fast cells to program can be useful to ensure that the dummy pulse(s) derived from the intelligent verification is not too high in magnitude. Other reasons can be used to choose between inner and outer memory cells. Additionally, the selection of inner or outer memory cells is an example of selecting memory cells for intelligent verification based on their physical location. In this example, it is based on the distance of the memory cells from the local interconnects 404 and 406. There may be other configurations in which the physical location of the memory cells affects the programming speed. The concept of selecting memory cells that are programmed more quickly for intelligent verification den, can be extended to other physical or physical conditions.

An embodiment as disclosed herein includes a non-volatile memory device having a plurality of non-volatile memory elements and control circuitry in communication with the non-volatile memory elements. The control circuit is configured to receive a command to program a group of the plurality of non-volatile memory elements and to enable a subset of the group of non-volatile memory elements for programming and to disable the remaining memory elements in the group for programming. The control circuit is configured to perform an intelligent verification on the subset of non-volatile memory elements and to determine a magnitude of the dummy programming pulse based on the intelligent verification. The control circuit is configured to release for programming the selected non-volatile memory elements in the group for which intelligent verification has not been performed. The control circuit is configured to prevent programming of the selected non-volatile memory elements in the group for which the intelligent verification was performed. The control circuit is configured to apply the dummy programming pulse to the group of non-volatile memory elements while enabling the selected non-volatile memory elements in the group for which the intelligent verification has not been performed to be programmed, and while the selected non-volatile memory elements in the group for which the intelligent verification was carried out are excluded from programming. The control circuit is configured to program the group of non-volatile memory elements after the dummy programming pulse is applied to the group.

An embodiment as disclosed herein includes a method of operating non-volatile memory. The method includes receiving a command to program a group of non-volatile memory elements, enabling programming of a subset of the group of non-volatile memory elements and preventing programming of the remaining memory elements in the group, performing an intelligent verification on the subset of non-volatile memory elements. Based on the intelligent verification or checking, a magnitude of a dummy programming pulse is determined. The method also includes enabling the programming of selected non-volatile memory elements in the group for which the intelligent verification has not been carried out, excluding the selected non-volatile memory elements in the group from programming for which the intelligent verification has been carried out and applying the dummy programming pulse to the group of non-volatile memory elements during the release to program selected non-volatile memory elements in the group for which the intelligent verification was not performed and while the selected non-volatile memory elements Volatile memory elements in the group for which intelligent verification has been carried out are excluded from programming. The method further includes programming the group of non-volatile memory elements after the dummy programming pulse is applied.

One embodiment includes a 3D stacked non-volatile memory device that includes a substrate, a three-dimensional memory array overlying the substrate, and control circuitry in communication with the non-volatile memory element. The three-dimensional memory array includes a plurality of non-volatile memory elements, each having a control gate. The control circuit receives a command to program a group of the plurality of non-volatile memory elements, applies signals to the control gates of the group of non-volatile memory elements while enabling a first set of non-volatile memory elements in the group for programming and a second Set of non-volatile memory elements in the group are excluded from programming. The control circuit samples the first set of non-volatile memory elements in response to the applied signals, determines the programming characteristics based on the applied signals and the sampling of the first set of non-volatile memory elements, and determines a magnitude or size of a dummy programming pulse based on the programming characteristics. The control circuit enables the selected non-volatile memory elements in the second set for programming, prohibits programming of the selected non-volatile memory elements in the first set, and applies the dummy programming pulse to the control gates of the group of non-volatile memory elements while the selected non-volatile memory elements in the second set are released for programming, whichever Rend the selected non-volatile memory elements in the first set from programming. The control circuit programs the group of non-volatile memory elements after the dummy programming pulse is applied.

Claims (15)

A non-volatile memory device comprising: a plurality of non-volatile memory elements (MC1, MC2, ...); a control circuit (110, 122, 124, 128, 132) communicating with the non-volatile memory elements, the control circuit configured to: receive an instruction for programming a group of the plurality of non-volatile memory elements; to characterize a programming speed of the group by applying a programming signal to the group while a subset of the group is enabled for programming and the remaining members of the group are prevented from being programmed, wherein in characterizing the programming speed a threshold voltage verification on an intelligent verification reference level is carried out; determine a magnitude for a dummy programming pulse based on the programming speed; applying the dummy programming pulse to the group while selected ones of the remaining members of the group are enabled for programming and while the subset is prevented from being programmed; and program the group of non-volatile memory elements after the dummy programming pulse is applied to the group. Non-volatile storage device Claim 1 , wherein the control circuit configured to characterize the programming speed of the group is further configured to: sense the non-volatile memory elements in the subset after the programming signal is applied while the remaining members of the group be excluded from recording. Non-volatile storage device Claim 1 , wherein the selected ones of the remaining members of the group that are enabled for programming while the control circuit applies the dummy programming pulse to the group are to be programmed to a threshold voltage that exceeds a target threshold voltage of one or more members of the group Non-volatile storage device Claim 1 , wherein the control circuit is configured to not validate the non-volatile memory elements in response to the dummy programming pulse being applied. Non-volatile storage device Claim 1 , wherein the selected ones of the remaining members of the group that are enabled for programming are to be programmed from a clear state to an intermediate state while the control circuit applies the dummy programming pulse to the group. Non-volatile storage device Claim 1 , wherein the selected ones of the remaining members of the group that are enabled for programming while the control circuit applies the dummy programming pulse to the group are to be programmed from a clear state to any one of a plurality of data states. Non-volatile storage device Claim 1 , which further comprises a three-dimensional memory array or a memory matrix having a plurality of word line layers, the group of non-volatile memory elements lying in the same word line layer. Non-volatile storage device Claim 7 , wherein non-volatile memory elements in the group have different distances from a local connection or a local interconnect, the subset being selected to characterize the programming speed of the group based on the distance from the local connection. A method of operating a non-volatile memory, comprising: receiving an instruction to program a group of non-volatile memory elements (502); enabling programming of a subset of the group of non-volatile memory elements and preventing programming of remaining memory elements in the group (504); performing intelligent verification of the subset of non-volatile memory elements (504); determining a magnitude of a dummy programming pulse (506) based on the intelligent verification; Release for programming selected non- volatile memory elements in the group for which intelligent checking was not performed (508); excluding from programming selected non-volatile memory elements in the group for which the intelligent check was performed (510); Applying the dummy programming pulse to the group of non-volatile memory elements during enabling to program selected non-volatile memory elements in the group for which the intelligent check has not been performed and during excluding from programming (512) the selected non-volatile memory elements Storage items in the group for which smart scanning was performed; and continuing to program the entire group of non-volatile memory elements after the dummy programming pulse is applied (514). Procedure according to Claim 9 , wherein performing an intelligent check on the subset of non-volatile memory elements includes: excluding from programming all non-volatile memory elements in the group that are not in the subset; enabling programming of non-volatile memory elements in the subset to be programmed from an erase state to a data state; applying a programming signal to control gates of the group of non-volatile memory elements; and sensing the non-volatile memory elements in the subset. Procedure according to Claim 10 , wherein scanning the non-volatile memory elements in the subset includes: excluding from the sampling all non-volatile memory elements in the group that are not in the subset; and enabling scanning of the non-volatile memory elements in the subset to be programmed from an erase state to a data state. Procedure according to one of the Claims 9 until 11 , further comprising selecting the subset based on the physical address or physical location of the non-volatile memory elements in the group Procedure according to Claim 9 , wherein the release to program selected non-volatile memory elements in the group for which the intelligent check was not performed includes: Release to program non-volatile memory elements that were not affected by the intelligent check and which are close to a first data state should be programmed to a reference state for intelligent checking. Procedure according to Claim 13 , which further includes enabling the programming of non-volatile memory elements that were affected by the intelligent check and which are to be programmed into a second data state above the first data state. Procedure according to Claim 14 , wherein determining a magnitude of a dummy programming pulse includes: determining a magnitude of a dummy programming pulse for changing a threshold voltage immediately from an erase state to a state close to but not above the second data state

Images