DE112014005546T5 - Landing-based compensation and parameter extraction in Amoled displays - Google Patents

Abstract

A system reads a desired circuit parameter from a pixel circuit that includes a light-emitting device, a drive device for providing a programmable drive current to the light-emitting device, a program input, and a memory device for storing a programming signal. One embodiment of the extraction system turns off the drive device and provides the light emitting device with a predetermined voltage from an external source, discharges the light emitting device until the light emitting device turns off, and then reads the voltage on the light emitting device off while this device is off. The voltages on the light-emitting devices in a plurality of pixel circuits can be read out at different times over the same external line. In-pixel, charge-based compensation schemes are also discussed that can be used with the external parameter extraction implementations.

Description

FIELD OF THE INVENTION

The present invention relates generally to organic active matrix light emitting diode device (AMOLED) displays, and more particularly to extraction parameters of the pixel circuits and light emitting devices in such displays.

BACKGROUND

The advantages of Organic Active Matrix Light Emitting Device (AMOLED) displays include lower power consumption, manufacturing flexibility, and a faster refresh rate over conventional liquid crystal displays. Unlike traditional liquid crystal displays, there is no backlight for an AMOLED display, so each pixel consists of different colored OLEDs that emit light independently of each other. The OLEDs emit light based on current provided by driver transistors controlled by programming voltages. The power consumed in each pixel is related to the intensity of the light generated in that pixel.

The output quality in an OLED-based pixel is affected by the characteristics of the driver transistor, which is typically made of materials including, but not limited to, amorphous silicon, polysilicon, or metal oxide, as well as the OLED itself. In particular, the threshold voltage and mobility of the driver transistor tend to change as the pixel ages. In order to maintain image quality, changes in these parameters must be compensated by adjusting the programming voltage. For this purpose, such parameters must be extracted from the driver circuit. Adding components to extract such parameters in a simple driver circuit requires more space on a display substrate for the driver circuitry, thereby reducing the amount of aperture or range of light emission from the OLED.

When biased in saturation, the I-U characteristic of a thin film driver transistor depends on the mobility and threshold voltage, which is a function of the materials used to make the transistor. Therefore, various thin film transistor devices implemented on the display panel may not exhibit uniform performance due to aging and process variations in mobility and threshold voltage. Accordingly, each constant voltage device may have a different drain current. An extreme example may be when a device may have a low threshold voltage and low mobility as compared to a second high threshold voltage, high mobility device.

Therefore, with very few electronic components available to maintain a desired aperture, extraction of nonuniform parameters (ie, threshold voltage V _th and mobility μ) of the driver TFT and the OLED becomes difficult. It would be desirable to extract such parameters in a drive circuit for an OLED pixel with as few components as possible to maximize the pixel aperture. It would also be desirable to combine parameter extraction with in-pixel compensation for optimum lifetime performance. In-pixel compensation refers to compensating for aging or time-dependent parameters within the pixel circuit without extracting any information from the pixel circuit to the outside.

SUMMARY

One disclosed embodiment reads or extracts a desired circuit parameter from a pixel circuit including a light-emitting device, a drive device for providing a programmable drive current to the light-emitting device, a program input, and a memory device for storing a programming signal. The extraction method includes turning off the driving device and providing a predetermined voltage from an external source to the light-emitting device, discharging the light-emitting device until the light-emitting device turns off, and then reading the voltage on the light-emitting device, while this device is off. In one implementation, the voltages on the light-emitting devices in a plurality of pixel circuits are read via the same external line at different times. Reading the desired parameter may be accomplished by coupling the pixel circuit to a charge pump amplifier, isolating the charge pump amplifier from the pixel circuit to provide a voltage output that is either proportional to the charge level or integrating the current from the pixel circuit, reading the voltage output of the charge pump amplifier; and determining at least one pixel circuit parameter from the voltage output of the charge pump amplifier.

Another embodiment extracts a circuit parameter from a pixel circuit by turning on the driving device, so that the voltage of the light-emitting device rises to a level higher than its turn-on voltage, turning off the driving device, so that the voltage on the light-emitting device through the light Emissive device is discharged until the light-emitting device turns off, and then reading the voltage on the light-emitting device while this device is turned off.

Another embodiment extracts a circuit parameter from a pixel circuit by programming the pixel circuit, turning on the driving device, and adjusting a parameter of the driving device by either (i) reading the current flowing through the driving device while applying a predetermined voltage to the driving device, or ( ii) reading the voltage on the driving device while a predetermined current is being passed through the driving device is extracted.

Another embodiment extracts a circuit parameter from a pixel circuit by turning on the driver and measuring the current and voltage of the driver transistor while changing the voltage between the gate and the source or drain of the driver transistor to drive the driver transistor in a linear mode during a time interval during a second time interval in the saturated operating state, and extracting a parameter of the light emitting device from the relationship of currents and voltages measured in the driver transistor operating in the two operating states.

Many other embodiments are shown and described herein.

The above and additional aspects and embodiments of the present invention will become apparent to those of ordinary skill in the art upon reading the detailed description of various embodiments and / or aspects made with reference to the drawings, a brief description of which is provided below.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other advantages of the invention will become apparent upon reading the following detailed description and upon reference to the drawings.

1 is a block diagram of an AMOLED display with compensation control;

2 is a circuit diagram of a data extraction circuit for a two-transistor pixel in the AMOLED display in 1 ;

3A FIG. 11 is a signal timing diagram of the signals to the data extraction circuit to determine the threshold voltage and mobility of an n-type driver transistor in FIG 2 to extract;

3B FIG. 11 is a signal timing diagram of the signals to the data extraction circuit to determine the characteristic voltage of the OLED in FIG 2 extract with an n-type driver transistor;

3C FIG. 12 is a signal timing diagram of the signals to the data extraction circuit for direct reading to determine the threshold voltage of an n-type driver transistor in FIG 2 to extract;

4A FIG. 12 is a signal timing diagram of the signals to the data extraction circuit to determine the threshold voltage and mobility of a p-type driver transistor in FIG 2 to extract;

4B FIG. 11 is a signal timing diagram of the signals to the data extraction circuit to determine the characteristic voltage of the OLED in FIG 2 extract with a p-type driver transistor;

4C FIG. 12 is a signal timing diagram of the signals to the data extraction circuit for direct reading to determine the threshold voltage of a p-type driver transistor in FIG 2 to extract;

4D FIG. 13 is a signal timing diagram of the signals to the data extraction circuit for directly reading the OLED turn-on voltage using either an n-type or a p-type driver transistor in FIG 2 ,

5 FIG. 12 is a circuit diagram of a data extraction circuit for a three-transistor drive circuit for one pixel in the AMOLED display in FIG 1 for the extraction of parameters;

6A FIG. 11 is a signal timing diagram of the signals to the data extraction circuit to determine the threshold voltage and mobility of the driver transistor in FIG 5 to extract;

6B FIG. 11 is a signal timing diagram of the signals to the data extraction circuit to determine the characteristic voltage of the OLED in FIG 5 to extract;

6C FIG. 12 is a signal timing diagram of the signals to the data extraction circuit for direct reading to the threshold voltage of the driver transistor in 5 to extract;

6D FIG. 13 is a signal timing diagram of the signals to the data extraction circuit for direct reading to determine the characteristic voltage of the OLED in FIG 5 to extract;

7 Fig. 10 is a flow chart of the extraction cycle to read the characteristics of the driver transistor and the OLED of a pixel circuit in an AMOLED display;

8th is a flow chart of various parameter extraction cycles and final applications; and

9 Figure 12 is a block diagram and diagram of the components of a data extraction system.

10 FIG. 11 is a signal timing diagram of the signals to the data extraction circuit to compare the threshold voltage and mobility of the driver transistor in a modified version of the circuit in FIG 5 to extract;

11 FIG. 12 is a signal timing diagram of the signals to the data extraction circuit to compare the characteristic voltage of the OLED in a modified version of the circuit in FIG 5 to extract;

12 is a circuit diagram of a data extraction circuit for reading the pixel charge from a drive circuit for a pixel in the AMOLED display in 1 ,

13 FIG. 11 is a signal timing diagram of the signals to the data extraction circuit of FIG 12 for reading the pixel status by externally initializing the nodes.

14 FIG. 13 is a flowchart for reading the pixel status in the circuit of FIG 12 by externally initializing the nodes;

15 FIG. 11 is a signal timing diagram of the signals to the data extraction circuit of FIG 12 for reading the pixel status by internally initializing the nodes;

16 FIG. 13 is a flowchart for reading the pixel status in the circuit of FIG 12 by internally initializing the nodes;

17 is a circuit diagram of a pair of circuits such as the circuit of 12 used in a common monitor line to read the pixel charge from two different pixels in the AMOLED display in 1 be used;

18 FIG. 11 is a signal timing diagram of the signals to the data extraction circuit of FIG 17 for reading the pixel charge when the monitor line is shared; and

19 FIG. 10 is a flowchart for reading the pixel status of a pair of circuits such as the circuit of FIG 17 with a common monitor line.

20A Fig. 10 is a schematic circuit diagram of a modified pixel circuit.

20B is a timing diagram illustrating the operation of the pixel circuit of 20A illustrated with charge-based compensation.

21 is a timing diagram illustrating the operation of the pixel circuit of 20A illustrated to obtain a readout of a parameter of the driver transistor.

22 is a timing diagram illustrating the operation of the pixel circuit of 20A illustrated in order to obtain a readout of a parameter of the OLED.

23 FIG. 11 is a timing diagram illustrating a modified operation of the pixel circuit of FIG 20A illustrated in order to obtain a readout of a parameter of the OLED.

24 is a circuit for extracting the parasitic capacitance from a pixel circuit using external compensation.

25 illustrates a pixel circuit that can be used for current measurement.

26 FIG. 10 is an exemplary pixel circuit using a charge-based in-pixel compensation implementation and its associated timing diagram.

27 shows the same pixel circuit used in 26 but using a different timeline.

28 FIG. 12 is an example of another pixel circuit in which the EM signal is divided into two signals to reset an internal node of the pixel circuit for compensation.

29 is another example of a pixel circuit and a timing diagram in which the OLED current or the OLED voltage can be read out via a monitor line.

30 is another exemplary charge-based compensation pixel circuit and a Timing diagram that compensates for a fluctuation or aging of the driver transistor.

31 Yet another example of a pixel circuit and an associated timing diagram having a discharge period to at least partially discharge the storage capacitor.

32 is 31 Similarly, except that the driver transistor T1 is programmed to operate as a switch.

33 is a pixel circuit in which the OLED voltage or the OLED current is read out via a monitor line, which can also function as a comparison line and / or a data line for programming information, and its associated timing diagram.

34 is another pixel circuit that shows another way to implement the EM function, along with an associated timing diagram.

35 is an ordinary pixel circuit.

36 is a pixel circuit in which one or more switches can be shared between rows and / or columns of the pixel array.

37 shows one 36 similar pixel circuit, but uses a different programming mode.

38 Figure 11 illustrates another pixel circuit sharing one or more switches.

39A and 39B illustrate a pixel circuit and an associated timing diagram having a discharge cycle.

40A and 40B illustrate another pixel circuit and an associated timing diagram having a reset cycle.

41A and 41B illustrate yet another pixel circuit and associated timing diagram having a reset and read cycle.

42A and 42B illustrate yet another pixel circuit and associated timing diagram having a reset and read cycle.

43A and 43B illustrate another pixel circuit and associated timing diagram having a read cycle as a result of a program cycle in which the pixel circuit is programmed off-current.

44A and 44B illustrate another pixel circuit and associated timing diagram having a read cycle as a result of a program cycle in which the pixel circuit is programmed off-current.

45A and 45B illustrate yet another pixel circuit and associated timing diagram having a discharge cycle.

46A and 46B illustrate yet another pixel circuit and an associated timing diagram having a reset cycle.

47A and 47B illustrate yet another pixel circuit and associated timing diagram having a reset and read cycle.

48A and 48B illustrate yet another pixel circuit and associated timing diagram having a reset and read cycle.

49A and 49B illustrate yet another pixel circuit and associated timing diagram having a read cycle as a result of a program cycle.

Although the present disclosure is open to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and will be described in detail herein. It should be understood, however, that the present disclosure is not intended to be limited to the particular forms disclosed. Rather, this disclosure is intended to cover all modifications, equivalents and alternatives falling within the spirit and scope of the invention as defined in the appended claims.

DETAILED DESCRIPTION

1 is an electronic advertising system 100 that has an active matrix area or a pixel array 102 in which an n × m array of pixels 104 arranged in a row and column configuration. For better illustration, only two rows and two columns are shown. Outside the active matrix area of the pixel array 102 is a border area 106 where peripheral circuitry for driving and controlling the pixel array 102 are attached. The peripheral circuitry includes an address or gate driver circuit 108 , a data or source driver circuit 110 , one control 112 and an optional supply voltage (eg, Vdd) driver 114 , The control 112 controls the gate, source and supply voltage drivers 108 . 110 . 114 , The gate driver 108 that by the controller 112 is controlled, operates on address or select lines SEL [i], SEL [i + 1] and so on, one for each row of pixels or pixel circuits 104 in the pixel arrangement 102 , In the pixel sharing configurations described below, the gate or address driver circuitry may be used 108 if applicable, also work on global selector lines GSEL [j] and optionally / GSEL [j] on multiple lines of pixels 104 in the pixel arrangement 102 work, such as every two lines of pixels 104 , The source driver circuit 110 that from the controller 112 is controlled, works on the voltage data connections Vdata [k], Vdata [k + 1] and so on, one for each column of pixels 104 in the pixel arrangement 102 , The voltage data lines transmit voltage programming information to each pixel 104 representing the brightness of each light-emitting device in the pixel 104 specify. A storage element, such as a capacitor, in each pixel 104 stores the voltage programming information until an emission or drive cycle turns on the light-emitting device. The optional power supply driver 114 that by the controller 112 controls a supply voltage (EL_Vdd) line, one for each row or column of pixels 104 in the pixel arrangement 102 ,

The ad system 100 further includes a power supply and readout circuit 120 which reads output data from data output lines VD [k], VD [k + 1] and so on, one for each column of pixels 104 in the pixel arrangement 102 ,

As is known, every pixel or every pixel circuit has to 104 in the ad system 100 with information (in the form of a current or voltage or charge) which is indicative of the brightness of the light-emitting device in the pixel 104 specify. A frame defines the amount of time that includes: (i) a programming cycle or programming phase during which each individual pixel in the display system 100 programmed with a programming voltage indicating a brightness; and (ii) a drive or emission cycle during which each light-emitting device in each pixel is turned on to emit light of a brightness corresponding to the programming voltage stored in a memory element. A single frame is therefore one of many still images that make a complete moving picture on the display system 100 is shown. There are at least schemes for programming and driving the pixels: line by line or frame by frame. In line-by-line programming, one line of pixels is programmed and then driven before the next line is programmed and driven. In frame by frame programming, all lines of pixels in the display system are first 100 programmed, and all lines of pixels are driven at once. Both schemes can use a short vertical blanking time at the beginning or end of each frame during which the pixels are neither programmed nor driven.

The outside of the pixel layout 102 arranged components can be in a border area 106 around the pixel layout 102 be arranged on the same physical substrate on which the pixel array 102 is arranged. These components include the gate driver 108 , the source driver 110 , the optional power supply driver 114 and a power supply and readout circuit 120 , Alternatively, some of the components may be in the border area 106 on the same substrate as the pixel array 102 may be disposed while other components are disposed on a different substrate, or all components in the edge region may be disposed on a substrate other than the substrate on which the pixel array is disposed 102 is arranged. Together, the gate driver 108 , the source driver 110 and the supply voltage driver 114 a display driver circuit. The display driver circuit may, in some configurations, be the gate driver 108 and the source driver 110 but not the supply voltage control 114 include.

When biased in saturation, the IU characteristic of a metal oxide semiconductor (MOS) transistor (a thin film transistor in this case of interest) is modeled as: I _D = 1/2 μC _ox W / L (V _GS - V _th ) ² where I _{D is} the drain current and V _{GS is} the voltage difference applied between gate and source terminals of the transistor. The one on the ad system 100 The implemented thin-film transistor devices exhibit non-uniform behavior due to aging and process variations in mobility (μ) and threshold voltage (V _th ). Accordingly, for a constant voltage difference V _GS applied between gate and source, each transistor on the pixel array 102 have a different drain current based on non-deterministic mobility and threshold voltage: I _{D (i, j)} = f (μ _{i, j} , V _{thi, j} ) where i and j are the coordinates (row and column) of a pixel in an nxm array of pixels, such as the array of pixels 102 in 1 , are.

2 shows a data extraction system 200 which is a two-transistor (2T) driver circuit 202 and a readout circuit 204 includes. The supply voltage control 114 is in a 2T pixel display system 104 optional. The readout circuit 204 is part of the power supply and readout circuit 120 and collects data from a column of pixels 104 , as in 1 shown. The readout circuit 204 includes a charge pump circuit 206 and a switch box circuit 208 , A voltage source 210 represents the driver circuit 202 through the control box circuit 208 the supply voltage ready. The charge pump and control box circuits 206 and 208 are on the top and bottom of the arrangement 102 implemented, such as in the voltage driver 114 and the power supply and readout circuit 120 in 1 , This is done either by direct fabrication on the same substrate as the pixel array 102 or by bonding a microchip to the substrate or connecting cord as a hybrid solution.

The driver circuit 202 includes a driver transistor 220 , an organic light-emitting device 222 , a drain storage capacitor 224 , a source storage capacitor 226 and a selection transistor 228 , A supply line 212 provides the supply voltage and also a monitor path (for the readout circuit 204 ) to a column of driver circuits such as the driver circuit 202 ready. A selection line input 230 is connected to the gate of the selection transistor 228 coupled. A programming data input 232 is connected to the gate of the driver transistor 220 through the selection transistor 228 coupled. The drain of the driver transistor 220 is with the supply voltage line 212 coupled and the source of the driver transistor 220 is with the OLED 222 coupled. The selection transistor 228 controls the coupling of the programming input 230 to the gate of the driver transistor 220 , The source storage capacitor 226 is between the gate and the source of the driver transistor 220 coupled. The drain storage capacitor 224 is between the gate and the drain of the driver transistor 220 coupled. The OLED 222 has a parasitic capacitance acting as a capacitor 240 is modeled. The supply voltage line 212 also has a parasitic capacitance acting as a capacitor 242 is modeled. The driver transistor 220 in this example, is a thin film transistor made of amorphous silicon. Of course, other materials such as polysilicon or metal oxide may also be used. A knot 244 is the circuit node where the source of the driver transistor 220 and the anode of the OLED 222 coupled together. In this example, the driver transistor is 220 an n-type transistor. The system 200 can with a p-type transistor instead of the n-type driver transistor 220 can be used as explained below.

The readout circuit 204 includes the charge pump circuit 206 and the switchbox circuit 208 , The charge pump circuit 206 includes an amplifier 250 which has a positive and a negative input. The negative input of the amplifier 250 is with a capacitor 252 (C _int ) in parallel with a switch 254 in a negative feedback loop with one output 256 of the amplifier 250 connected. The desk 254 (S4) is used to connect the capacitor 252 C _int to discharge during the precharge phase. The positive input of the amplifier 250 is with a common mode voltage input 258 (VCM) coupled. The exit 256 of the amplifier 250 are different extracted parameters of the driver transistor 220 and the OLED 222 as explained below.

The control box circuit 208 includes several switches 260 . 262 and 264 (S1, S2 and S3) to supply power to and from the pixel driver circuit 202 to lead. The desk 260 (S1) is used during the reset phase to provide a discharge path to ground. The desk 262 (S2) sets the supply connection during the normal operation of the pixel 104 and also during the integration phase of the readout. The desk 264 (S3) is used to charge the pump circuit 206 from the supply line voltage 212 To isolate (VD).

The general readout concept for the two transistor pixel driver circuit 202 for each of the pixels 104 , as in 2 shown results from the fact that the charge, which is due to the capacitor 240 represented parasitic capacitance at the OLED 222 is stored, useful information of the threshold voltage and mobility of the driver transistor 220 and the turn-on voltage of the OLED 222 having. The extraction of such parameters can be used for various applications. For example, such parameters may be used to represent the programming data for the pixels 104 to compensate for pixel variations and maintain image quality. Such parameters can also be used to control the pixel arrangement 102 to age. The parameters can also be used to estimate the process yield for the pixel array fabrication 102 to rate. These and other parameters may be determined by any of the pixel circuits described herein, including a line such as a monitor line the pixel circuit is connected to extract or read such parameters.

Assuming that the capacitor 240 (C _OLED ) is initially discharged, the capacitor needs 240 (C _OLED ) some time to recharge to a voltage level that drives the driver 220 off. This voltage level is a function of the threshold voltage of the driver transistor 220 , The voltage at the programming data input 232 (V _Data ) is applied, must be low enough that the steady state voltage of the OLED 222 (V _OLED ) is lower than the turn-on threshold voltage of the OLED 222 itself. In this state, V _{Data -V OLED is} a linear function of the threshold voltage (V _th ) of the driver transistor 220 , For the mobility of a thin film transistor device, such as a driver transistor 220 The transient oscillation of such devices, which is a function of both the threshold voltage and the mobility, is taken into account. Assuming that the threshold voltage deviation is below the TFT devices such as the driver transistor 220 is compensated, is the tension of the node 244 which is sampled at a constant interval after the start of the integration, a function of the mobility of only the TFT device such as the driver transistor 220 of interest.

3A - 3C are signal timing diagrams of the components in 2 applied control signals to parameters such as voltage threshold and mobility from the driver transistor 220 and the turn-on voltage of the OLED 222 in the driver circuit 200 to extract, on the assumption that the driver transistor 220 is an n-type transistor. Such control signals may be provided by the controller 112 at the source driver 110 , Gate driver 108 and the power supply and readout circuit 120 in 1 be created. 3A Figure 9 is a timing diagram showing the signals appearing at the extraction circuit 200 are applied to the threshold voltage and mobility from the driver transistor 220 to extract. 3A includes a signal 302 for the selection input 230 in 2 , a signal 304 (φ ₁ ) at the switch 260 , a signal 306 (φ ₂ ) for the switch 262 , a signal 308 (φ ₃ ) for the switch 264 , a signal 310 (φ ₄ ) for the switch 254 , a programming voltage signal 312 for the programming data input 232 in 2 , a tension 314 of the node 244 in 2 and an output voltage signal 316 for the exit 256 of the amplifier 250 in 2 ,

3A shows the four phases of the read-out process, a reset phase 320 , an integration phase 322 , a preloading phase 324 and a selection phase 326 , The process starts by activating a high selection signal 302 at the selection entrance 230 , The selection signal 302 is held high by the entire reading process, as in 3A shown.

During the reset phase 320 becomes the input signal 304 (φ ₁ ) at the switch 260 set high to provide a discharge path to ground. The signals 306 . 308 and 310 (φ ₂ , φ ₃ , φ ₄ ) at the switches 262 . 264 and 250 will be kept low during this phase. A sufficiently high voltage level (V _{RST_TFT} ) will be at the programming _{data input} 232 (V _Data ) applied to the current flow through the driver transistor 220 to maximize. Consequently, the voltage at the node becomes 244 in 2 discharged to ground to be ready for the next cycle.

During the integration phase 322 the signal stays 304 (φ ₂ ) at the switch 262 high, giving a charge path from the voltage source 210 to the switch 262 provides. The signals 304 . 308 and 310 (φ ₁ , φ ₃ , φ ₄ ) at the switches 260 . 264 and 250 will be kept low during this phase. The programming voltage input 232 (V _Data ) is set to a voltage level (V _{INT_TFT} ), so once the capacitor 240 (C _oled ) is fully charged, the voltage at the node 244 lower than the turn-on voltage of the OLED 222 is. This condition minimizes any interference from the OLED 222 during the readout of the driver transistor 220 , Shortly before the end of the integration time, the signal becomes 312 at the programming voltage input 232 (V _Data ) to V _OFF decreases to the charge on the capacitor 240 (C _oled ) to isolate from the rest of the circuit.

If the integration time is long enough, that is on the capacitor 240 (C _oled ) stored charge a function of the threshold voltage of the driver transistor 220 , For a shorter integration time, the voltage experiences at the node 244 an incomplete transient and the stored charge on the capacitor 240 (C _oled ) is a function of both the threshold voltage and the mobility of the driver transistor 220 , Accordingly, it is feasible to extract both parameters by making two separate readings with short and long integration phases.

During the preloading phase 324 are the signals 304 and 306 (φ ₁ , φ ₂ ) at the switches 260 and 262 set low. As soon as the input signal 310 (φ ₄ ) at the switch 254 is set high, is the amplifier 250 set in a unit feedback configuration. To the output stage of the amplifier 250 short-circuit current from the supply voltage 210 to protect, the signal becomes 308 (φ ₃ ) at the switch 264 high when the signal 306 (φ ₂ ) at the switch 262 is set low. If the desk 264 is closed, the parasitic capacitance 242 the supply line to the common mode voltage VCM precharged. The common mode voltage VCM is a voltage level lower than the ON voltage of the OLED 222 have to be. Shortly before the end of the precharge phase, the signal is 310 (φ ₄ ) at the switch 254 set low to the charge pump amplifier 250 to prepare for the selection cycle.

During the selection phase 336 are the signals 304 . 306 and 310 (φ ₁ , φ ₂ , φ ₄ ) at the switches 260 . 262 and 254 set low. The signal 308 (φ ₃ ) at the switch 264 is held high to a load transfer path from the driver circuit 202 to the charge pump amplifier 250 provide. A sufficiently high voltage 312 (V _{RD_TFT} ) is at the programming _{voltage input} 232 (V _Data ) applied to the channel resistance of the driver transistor 220 to minimize. If the integration cycle is long enough, the accumulated charge is at the capacitor 252 (C _int ) is not a function of the integration time. Accordingly, the output voltage of the charge pump amplifier 250 in this case the same:

For a shortened integration time, the accumulated charge is at the capacitor 252 (C _int ) given by:

Consequently, the output voltage 256 of the charge pump amplifier 250 at the end of the read cycle:

Therefore, the threshold voltage and the mobility of the driver transistor 220 by reading the output voltage 256 of the amplifier 250 in the middle of and at the end of the selection phase 326 be extracted.

3B FIG. 12 is a timing chart for the readout operation of the threshold turn-on voltage parameter of the OLED 222 in 2 , The read-out process of the OLED 222 also includes four phases, one reset phase 340 , an integration phase 342 , a preloading phase 344 and a selection phase 346 , Like the readout process for the driver transistor 220 in 3A The read-out process for OLED starts by activating the selection input 230 with a high selection signal 302 , The time course of the signals 304 . 306 . 308 and 310 (φ ₁ , φ ₂ , φ ₃ , φ ₄ ) at the switches 260 . 262 . 264 and 254 is the same as the drive transistor readout 220 in 3A , A programming signal 332 for the programming input 232 , a signal 334 for the node 244 and an output signal 336 for the output of the amplifier 250 are different from the signals in 3A ,

During the reset phase 340 becomes a sufficiently high voltage level 332 (V _{RST_OLED} ) on the programming _{data input} 232 (V _Data ) applied to the current flow through the driver transistor 220 to maximize. Consequently, the voltage at the node becomes 244 in 2 to earth at the switch 260 unloaded to be ready for the next cycle.

During the integration phase 342 the signal stays 306 (φ ₂ ) at the switch 262 high, giving a charge path from the voltage source 210 to the switch 262 provides. The programming voltage input 232 (V _Data ) is at a voltage level 332 (V _{INT_OLED} ), so once the capacitor 240 (C _oled ) is fully charged, the voltage at the node 244 higher than the turn-on voltage of the OLED 222 is. In this case, the driver transistor drives 220 at the end of the integration phase 342 a constant current through the OLED 222 ,

During the preloading phase 344 becomes the driver transistor 220 through the signal 332 at the programming input 232 switched off. The capacitor 240 (C _oled ) will allow it to discharge until it reaches the turn-on voltage of OLED 222 at the end of the preloading phase 344 reached.

During the selection phase 346 becomes a sufficiently high voltage 332 (V _{RD_OLED} ) at the programming _{voltage input} 232 (V _Data ) applied to the channel resistance of the driver transistor 220 to minimize. When the precharge phase is long enough, the steady state voltage is at the capacitor 252 (C _int ) not a function of pre-charge time. Consequently, the output voltage 256 of the charge pump amplifier 250 at the end of the selection phase given by:

The signal 308 (φ ₃ ) at the switch 264 is held high to a load transfer path from the driver circuit 202 to the charge pump amplifier 250 provide. Therefore, the output voltage signal 336 used to control the turn-on voltage of the OLED 220 to determine.

3C is a timing diagram for the direct readout of the driver transistor 220 under Use of the extraction circuit 200 in 2 , The direct read-out process has a reset phase 350 , a preloading phase 352 and an integration / readout phase 354 on. The read-out process is activated by activating the selection input 230 in 2 initialized. The selection signal 302 at the selection entrance 230 is held high by the reading process, as in 3C shown. The signals 364 and 366 (φ ₁ , φ ₂ ) for the switches 260 and 262 are inactive in this read process.

During the reset phase 350 are the signals 368 and 370 (φ ₃ , φ ₄ ) for the switches 264 and 254 set high to provide a virtual ground discharge path. A sufficiently high voltage 372 (V _{RST_TFT} ) is at the programming _input 232 (V _Data ) applied to the current flow through the driver transistor 220 to maximize. Consequently, the node becomes 244 at the common mode voltage 374 (VCM _RST ) to be ready for the next cycle.

During the preloading phase 354 becomes the driver transistor 220 by applying an off voltage 372 (V _OFF ) at the programming input 232 in 2 switched off. The common mode voltage input 258 at the positive input of the amplifier 250 is increased to VCM _RD to precharge the line resistance. At the end of the preloading phase 354 becomes the signal 370 (φ ₄ ) at the switch 254 switched off to the charge pump amplifier 250 to prepare for the next cycle.

At the beginning of the readout / integration phase 356 becomes the programming voltage input 232 (V _Data ) to V _{INT_TFT} 372 increased to the driver transistor 220 turn. The capacitor 240 (C _OLED ) begins to accumulate the charge until V _Data minus the voltage at the node 244 equal to the threshold voltage of the driver transistor 220 is. In the meantime, a proportional charge will be in the capacitor 252 (C _INT ) accumulates. Accordingly, at the end of the readout cycle 356 the output voltage 376 at the exit 256 of the amplifier 250 a function of the threshold voltage given by:

As indicated by the above equation, in the case of direct readout, the output voltage has a positive polarity. Therefore, the threshold voltage of the driver transistor 220 by the output voltage of the amplifier 250 be determined.

As stated above, the driver transistor 220 in 2 be a p-type transistor. 4A - 4C are signal timing diagrams of the signals appearing at the components in 2 are applied to the threshold voltage and mobility from the driver transistor 220 and the OLED 222 to extract if the driver transistor 220 is a p-type transistor. In the example in which the driver transistor 220 a p-type transistor is the source of the driver transistor 220 with the supply line 212 (VD) and the drain of the driver transistor 220 is with the OLED 222 coupled. 4A Figure 9 is a timing diagram showing the signals appearing at the extraction circuit 220 are applied to the threshold voltage and mobility from the driver transistor 220 to extract if the driver transistor 220 is a p-type transistor. 4A shows voltage signals 402 - 416 for the selection input 232 , the circuits 260 . 262 . 264 and 254 , the programming data input 230 , the voltage at the node 244 and the output voltage 256 in 2 , The data extraction is carried out in three phases, a reset phase 420 , an integration / preloading phase 422 and a selection phase 424 ,

As in 4A shown is the selection signal 402 active low and is about the readout phases 420 . 422 and 424 kept low. The signals are read out via the read-out process 404 and 406 (φ ₁ , φ ₂ ) at the switches 260 and 262 kept low (inactive). During the reset phase, the signals become 408 and 410 (φ ₃ , φ ₄ ) at the switches 264 and 254 set high to the knot 244 to a reset common-mode voltage level VCM _rst . The common mode voltage input 258 at the charge pump input 258 (VCM _rst ) should be low enough to the OLED 222 keep off. The programming data input 232 V _Data is at a low enough value 412 (V _{RST_TFT} ) set to maximum charging current through the driver transistor 220 provide.

During the integration / pre-charge phase 422 is the common mode voltage at the common mode voltage input 258 reduced to VCM _int and the programming input 232 (V _Data ) is at a level 412 (V _{INT_TFT} ) increases so that the driver transistor 220 in the opposite direction. If the time allotted for this phase is long enough, the voltage goes to the node 244 back until the gate-source voltage of the driver transistor 220 the threshold voltage of the driver transistor 220 reached. Before the end of this cycle the signal decreases 410 (φ ₄ ) at the switch 254 to the charge pump amplifier 250 on the selection phase 424 prepare.

The selection phase 424 is by reducing the signal 412 at the programming input 232 (V _Data ) initialized to V _{RD_TFT} to the driver _transistor 220 turn. The on the capacitor 240 (C _OLED ) stored charge is now the capacitor 254 (C _INT ). At the end of the selection phase 424 becomes the signal 408 (φ ₃ ) at the switch 264 set low to the charge pump amplifier 250 from the driver circuit 202 to isolate. The output voltage signal 416 V _out from the amplifier output 256 is now a function of the threshold voltage of the driver transistor 220 which is given by:

4B is a timing diagram for the in-pixel extraction of the threshold voltage of the OLED 222 in 2 , assuming that the driver transistor 220 is a p-type transistor. The extraction process is the time course of signals at the extraction circuit 200 for an n-type transistor in 3A very similar. 4B shows voltage signals 432 - 446 for the selection input 230 , the switches 260 . 262 . 264 and 254 , the programming data input 232 , the voltage at the node 244 and the amplifier output 256 in 2 , The extraction process includes a reset phase 450 , an integration phase 452 , a preloading phase 454 and a selection phase 456 , The main difference of this readout cycle compared to the readout cycle in 4A exists in the voltage levels of the signal 442 at the programming data input 232 (V _Data ) connected to the driver circuit 210 are created in each selection phase. For a p-type thin-film transistor used for the driver transistor 220 can be used is the selection signal 430 at the selection entrance 232 active low. The selection input 232 is kept low on the reading process, as in 4B shown.

The read-out process is started by first the capacitor 240 (C _OLED ) in the reset phase 450 is reset. The signal 434 (φ ₁ ) at the switch 260 is set high to provide a discharge path to ground. The signal 442 at the programming input 232 (V _Data ) is reduced to V _{RST_OLED} to the driver _transistor 220 turn.

In the integration phase 452 become the signals 434 and 436 (φ ₁ , φ ₂ ) at the switches 260 and 262 in off or on states offset to the OLED 222 to provide a charging path. The capacitor 240 (C _OLED ) will allow to charge until the voltage 444 at the node 244 about the threshold voltage of the OLED 222 goes out to turn it on. Before the end of the integration phase 452 becomes the voltage signal 442 at the programming input 232 (V _Data ) increased to V _OFF to the driver transistor 220 off.

Also be in the preloading phase 454 the signals 434 and 436 (φ ₁ , φ ₂ ) at the switches 260 and 262 switched off while the signals 438 and 440 (φ ₃ , φ ₄ ) at the switches 264 and 254 be turned on. This represents the state for the amplifier 250 ready, the supply line 212 (VD) at the common mode voltage input 258 (VCM) at the positive input of the amplifier 250 is provided. At the end of the precharge phase the signal will be 430 (φ ₄ ) at the switch 254 switched off to the charge pump amplifier 250 on the selection phase 456 prepare.

The selection phase 456 is done by turning on the driver transistor 220 initializes when the voltage 442 at the programming input 232 (V _Data ) is reduced to V _{RD_OLED} . The on the capacitor 240 (C _OLED ) stored charge is now the capacitor 254 (C _INT ) which transmits the output voltage 446 at the exit 256 of the amplifier 250 as a function of the threshold voltage of the OLED 220 builds.

4C is a signal timing diagram for the direct extraction of the threshold voltage of the driver transistor 220 in the extraction system in 2 if the driver transistor 220 is a p-type transistor. 4C shows voltage signals 462 - 476 for the selection input 230 , the switches 260 . 262 . 264 and 254 , the programming data input 232 , the voltage at the node 244 and the output voltage 256 in 2 , The extraction process includes a pre-charge phase 480 and an integration phase 482 , However, in the timing diagram in 4C a dedicated final selection phase 484 which can be eliminated when the output of the charge pump amplifier 250 at the end of the integration phase 482 is scanned.

The extraction process is accomplished by simultaneously precharging the drain storage capacitor 224 , the source storage capacitor 226 , the capacitor 240 (C _OLED ) and the capacitor 242 in 2 initialized. For this purpose, the signals 462 . 468 and 470 at the selection line input 230 and the switches 264 and 254 activated, as in 4C shown. The signals are read out via the read-out process 404 and 406 (φ ₁ , φ ₂ ) at the switches 260 and 262 kept low. The voltage level of the common-mode voltage input 258 (VCM) determines the voltage on the supply line 212 and therefore the tension at the knot 244 , The common mode voltage (VCM) should be low enough so that the OLED 222 is not turned on. The voltage 472 at the programming input 232 (V _Data ) is set to a level (V _{RST_TFT} ) low enough to the transistor 220 turn.

wobei I_TFT der Drain-Strom des Treibertransistors 220 ist, der eine Funktion der Beweglichkeit und (V_CM – V_Data – |V_th|) ist. T_int ist die Länge der Integrationszeit. In der optionalen Auslesephase 484 wird das Signal 468 (ϕ₃) am Schalter 264 niedrig gehalten, um den Ladungspumpenverstärker 250 von der Treiberschaltung 202 zu isolieren. Die Ausgangsspannung 256, die eine Funktion der Beweglichkeit und der Schwellenspannung des Treibertransistors 220 ist, kann zu jeder Zeit während der Auslesephase 484 abgetastet werden.At the beginning of the integration phase 482 is the signal 470 (φ ₄ ) at the switch 254 turned off to the charge pump amplifier 250 to allow the current through the driver transistor 220 to integrate. The output voltage 256 of the charge pump amplifier 250 rises at a constant rate, which is a function of the threshold voltage of the driver transistor 220 and its gate-source voltage is. Before the end of the integration phase 482 is the signal 468 (φ ₃ ) at the switch 264 switched off to the charge pump amplifier 250 from the driver circuit 220 to isolate. Accordingly, the output voltage 256 of the amplifier 250 given by:

where I _{TFT is} the drain current of the driver transistor 220 , which is a function of mobility and (V _CM - V _Data - | V _th |). T _int is the length of the integration time. In the optional readout phase 484 becomes the signal 468 (φ ₃ ) at the switch 264 kept low to the charge pump amplifier 250 from the driver circuit 202 to isolate. The output voltage 256 , which is a function of the mobility and threshold voltage of the driver transistor 220 is, at any time during the selection phase 484 be scanned.

4D is a timing diagram for direct reading of the OLED 222 in 2 , If the driver transistor 220 With a sufficiently high gate-source voltage turned on, it came as an analog switch used to connect to the anode terminal of the OLED 222 access. In this case, the voltage is at the node 244 essentially equal to the voltage on the supply line 212 (VD). Accordingly, the drive current through the driver transistor 220 only a function of the turn-on voltage of the OLED 222 and the voltage on the supply line 212 is set. The drive current may be through the charge pump amplifier 250 be provided. When integrated over a certain period of time, the output voltage is 256 the integrator circuit 206 a measure of how far the OLED 222 aged.

4D Figure 3 is a timing diagram indicating the signals appearing at the extraction circuit 200 are applied to the turn-on voltage from the OLED 222 to extract via a direct reading. 4D shows the three phases of the read-out process, a pre-charge phase 486 , an integration phase 487 and a selection phase 488 , 4D includes a signal 489n or 489p for the selection input 230 in 2 , a signal 490 (φ ₁ ) at the switch 260 , a signal 491 (φ ₂ ) for the switch 262 , a signal 492 (φ ₃ ) for the switch 264 , a signal 493 (φ ₄ ) for the switch 254 , a programming voltage signal 494n or 494p for the programming data input 232 in 2 , a tension 495 of the node 244 in 2 and an output voltage signal 496 for the exit 256 of the amplifier 250 in 2 ,

The process begins by activating the selection signal corresponding to the desired row of pixels in the array 102 , As in 4D illustrates is the selection signal 489n active high for an n-type select transistor and active low for a p-type select transistor. A high selection signal 489n will be at the selection entrance 230 applied in the case of an n-type driver transistor. A low signal 489p will be at the selection entrance 230 in the case of a p-type driver transistor for the driver transistor 220 created.

was ein Maß dafür darstellt, wie stark die OLED gealtert ist. T_int ist in dieser Gleichung das Zeitintervall zwischen der abfallenden Flanke des Schaltersignals 493 (ϕ₄) und der abfallenden Flanke des Schaltersignals 492 (ϕ₃).The selection signal 489n or 489p is during the precharge and integration cycles 486 and 487 kept active. The φ ₁ and φ ₂ input 490 and 491 are inactive in this selection process. During the precharge cycle, the switching signals become 492 φ ₃ and 493 φ _{4 is} set high to provide a signal path so that the parasitic capacitance 242 the supply line (C _p ) and the voltage at the node 244 can be precharged to the common mode voltage (VCM _OLED ), which is the non-inverting terminal of the amplifier 250 provided. A drive voltage signal 494n or 494p (V _{ON_nTFT} or V _{ON_pTFT} ), which is high enough, is sent to the data input 232 (V _Data ) applied to the driver transistor 220 to operate as an analog switch. Consequently, the supply voltage 212 VD and the node 244 precharged to the common mode voltage (VCM _OLED ) to prepare for the next cycle. At the beginning of the integration phase 487 becomes the switch input 493 φ ₄ turned off to the charge pump module 206 to allow the current of the OLED 222 to integrate. The output voltage 496 of the charge pump module 206 drops at a constant rate, which is a function of the turn-on voltage of the OLED 222 and the tension 495 at the node 244 is set, ie VCM _OLED represents. Before the end of the integration phase 487 becomes the switch signal 492 φ ₃ switched off to the charge pump module 206 from the pixel circuit 202 to isolate. From this point on, the output voltage is constant until the charge pump module 206 is reset for another reading. When integrated over a certain period of time, the output voltage is given as follows:

which is a measure of how much the OLED has aged. T _int in this equation is the time interval between the falling edge of the switch signal 493 (φ ₄ ) and the falling edge of the switch signal 492 (φ ₃ ).

Similar extraction processes of a driver circuit of the two-transistor type, such as. In 2 , can be used to prevent nonuniformity and aging conditions, such as Threshold voltages, and the mobility of a tri-transistor type driver circuit as part of the data extraction system 500 to extract, as in 5 is shown. The data extraction system 500 includes a drive circuit 502 and a readout circuit 504 , The readout circuit 504 is part of the power supply and the readout circuit 120 and collects data from a column of pixels 104 as in 1 and includes a charge pump circuit 506 and a switch box circuit 508 , A voltage source 510 represents the supply voltage (VDD) for the drive circuit 502 ready. The charge pump and the switchbox circuits 506 and 508 are on the top or bottom of the plate 102 arranged, such. B. in the voltage driver 114 and in the power supply and readout circuit 120 in 1 , This is done either by direct preparation on the same substrate as in plate 102 or by bonding a microchip to the substrate or a flexible base as a hybrid solution.

The drive circuit 502 includes a driver transistor 520 , an organic light-emitting device 522 , a drain storage capacitor 524 , a source storage capacitor 526 and a selection transistor 528 , A selection line input 530 to the gate of the selection transistor 528 coupled. A programming input 532 is through the selection transistor 528 to the gate of the driver transistor 220 coupled. The selection line input 530 is also connected to the gate of an output transistor 534 coupled. The output transistor 534 is with the source of the driver transistor 520 and a monitor output voltage line 536 , The drain of the driver transistor 520 is with the supply voltage source 510 coupled, and the source of the driver transistor 520 is with the OLED 522 coupled. The source storage capacitor 526 is between the gate and the source of the driver transistor 520 coupled. The drain storage capacitor 524 is between the gate and the drain of the driver transistor 520 coupled. The OLED 522 has a parasitic capacitance that acts as a capacitor 540 is modeled. The monitor output voltage line 536 also has a parasitic capacitance that acts as a capacitor 542 is modeled. The driver transistor 520 In this example, a thin film transistor made of amorphous silicon is shown. A voltage node 544 is the point between the source terminal of the driver transistor 520 and the OLED 522 , In this example, the driver transistor is 520 an n-type transistor. The system 500 can with a p-type driver transistor instead of the driver transistor 520 be implemented.

The readout circuit 504 includes the charge pump circuit 506 and the switchbox circuit 508 , The charge pump circuit 506 includes an amplifier 550 who has a capacitor 552 (C _int ) in a negative feedback loop. A switch 554 (S4) is used to connect the capacitor 552 C _int to discharge during the precharge phase. The amplifier 550 has a negative input connected to the capacitor 552 and the switch 554 is coupled, and a positive input connected to a common mode voltage input 558 (VCM) is coupled. The amplifier 550 has an exit 556 on which the various extracted factors of the driver transistor 520 and the OLED 522 as explained below.

The control box circuit 508 includes several switches 560 . 562 and 564 to the power to the drive circuit 502 and to lead her away. The desk 560 is used during the reset phase to provide the discharge path to ground. The desk 562 provides the supply connection during normal operation of the pixel 104 and also during the integration phase of the readout. The desk 564 is used to charge the pump circuit 506 from the supply line voltage source 510 to isolate.

In the three-transistor drive circuit 502 The reading is normally done by the monitor line 536 , The readout can also be done by the power supply line from the supply voltage source 510 similar to the method for timing signals in 3A - 3C , Accurate timing of the input signals (φ ₁ -φ ₄ ) into the switches 560 . 562 . 564 and 554 , the selection input 530 and the programming voltage input 532 (V _Data ) is used to control the performance of the readout circuit 500 to control. Certain voltage values are applied to the programming data input 532 (V _Data ) and the common-mode voltage input 558 (VCM) during each phase of the readout process.

The three-transistor drive circuit 502 can be differentiated by the programming voltage input 532 and the monitor output 536 be programmed. Accordingly, the reset and precharge phases may be merged to obtain a reset / precharge phase followed by an integration phase and a readout phase.

6A Figure 3 is a timing diagram of the signals showing the extraction of the threshold voltage and the mobility of the driver transistor 520 in 5 include. The timing diagram includes voltage signals 602 - 618 for the selection input 530 , the switches 560 . 562 . 564 and 554 , the programming voltage input 532 , the voltage at the gate of the driver transistor 520 , the voltage at the node 544 and the output voltage 556 in 5 , The read-out process in 6A indicates a preloading phase 620 , an integration phase 622 and a selection phase 624 on. The readout process starts by simultaneous precharging of the drain capacitor 524 , the source capacitor 526 and the parasitic capacitors 540 and 542 , For this purpose, the selection line voltage 602 and the signals 608 and 610 (φ ₃ , φ ₄ ) to the switches 564 and 554 as in 6A shown activated. The signals 604 and 606 (φ ₁ , φ ₂ ) to the switches 560 and 562 stay low throughout the readout cycle.

The voltage level of the common mode input 558 (VCM) determines the voltage on the output monitor line 536 and thus the tension at the knot 544 , The voltage to the common mode input 558 (VCM _TFT ) should be low enough so that the OLED 522 does not turn on. In the preloading phase 620 is the voltage signal 612 to the programming voltage input 532 (V _Data ) high enough (V _{RST_TFT} ) to drive the driver 520 turn on, and low enough so that the OLED 522 always stays off.

At the beginning of the integration phase 622 is the tension 602 to the selection input 530 disabled, so that a charge on the capacitor 540 (C _OLED ) can be stored. The tension at the knot 544 begins to rise, and the gate voltage of the driver transistor 520 follows this with a ratio between the capacitor value of the source capacitor 526 and the capacitance of the source capacitor 526 and the drain capacitor 524 [C _S1 / (C _S1 + C _S2 )]. The charge is complete as soon as the difference between the gate voltage of the driver transistor 520 and the tension at the node 544 equal to the threshold voltage of the driver transistor 520 is. Before the end of the integration phase 622 becomes the signal 610 (φ ₄ ) to the switch 554 switched off to the charge pump amplifier 550 for the selection phase 624 prepare.

For the selection phase 624 becomes the signal 602 to the selection input 530 reactivated. The voltage signal 612 at the programming input 532 (V _{RD_TFT} ) is low enough to drive the driver 520 keep off. The charge on the capacitor 240 (C _OLED ) is now stored to the capacitor 254 (C _INT ) and creates an output voltage 618 proportional to the threshold voltage of the driver transistor 520 :

Before the end of the selection phase 624 becomes the signal 608 (φ ₃ ) to the switch 564 switched off to the charge pump circuit 506 from the drive circuit 502 to isolate.

6B is a timing diagram for the input signals for extracting the turn-on voltage of the OLED 522 in 5 , 6B includes voltage signals 632 - 650 for the selection input 530 , the switches 560 . 562 . 564 and 554 , the programming voltage input 532 , the voltage at the gate of the driver transistor 520 , the voltage at the node 544 , the common-mode voltage input 558 and the output voltage 556 in 5 , The read-out process in 6B indicates a preloading phase 652 , an integration phase 654 and a selection phase 656 on. Similar to the reading for the driver transistor 220 in 6A The read-out process starts with a simultaneous precharging of the drain capacitor 524 , the source capacitor 526 and the parasitic capacitors 540 and 542 in the preloading phase 652 , For this purpose, the signal 632 to the selection input 530 and the signals 638 and 640 (φ ₃ , φ ₄ ) to the switches 564 and 554 as in 6B shown activated. The signals 634 and 636 (φ ₁ , φ ₂ ) remain low during the read cycle. The input voltage 648 (VCM _Pre ) to the common mode voltage input 258 should be high enough for the OLED 522 is turned on. The voltage 642 (V _{Pre_OLED} ) to the programming _input 532 (V _Data ) is low enough to drive the driver 520 keep off.

At the beginning of the integration phase 654 becomes the signal 632 to the selection input 530 disabled, so that a charge in the capacitor 540 (C _OLED ) can be stored. The tension at the knot 544 begins to fall and the gate voltage of the driver transistor 520 follows this with a ratio between the capacitor value of the source capacitor 526 and the capacitance of the source capacitor 526 and the drain capacitor 524 [C _S1 / (C _S1 + C _S2 )]. The discharge is complete as soon as the voltage at the node 544 the ON voltage (V _OLED ) of the OLED 522 reached. Before the end of the integration phase 654 becomes the signal 640 (φ ₄ ) to the switch 554 switched off to the charge pump circuit 506 for the selection phase 656 prepare.

For the selection phase 656 becomes the signal 632 to the selection input 530 reactivated. The voltage 642 (V _{RD_OLED} ) at the programming _input 532 should be low enough to drive the driver 520 keep off. The in the capacitor 540 (C _OLED ) stored charge then becomes the capacitor 552 (C _INT ), which is an output voltage 650 at the amplifier output 556 proportional to the ON voltage of the OLED 522 generated.

The signal 638 (φ ₃ ) will be before the end of the readout phase 656 switched off to the charge pump circuit 508 from the drive circuit 502 to isolate.

As shown, the monitor output transistor 534 a direct way for a linear integration of the current for the driver transistor 520 or the OLED 522 ready. The reading can be done in a pre-charge and integration cycle. 6C however, shows timing diagrams for the input signals for another final readout phase that may be eliminated when the output of the charge pump circuit 508 is sampled in the integration phase. 6C includes voltage signals 660 - 674 for the selection input 530 , the switches 560 . 562 . 564 and 554 , the programming voltage input 532 , the voltage at the node 544 and the output voltage 556 in 5 , The read-out process in 6C therefore has a preload phase 676 , an integration phase 678 and an optional readout phase 680 on.

The direct integration read operation of the n-type driver transistor 520 in 5 will, as in 6C illustrated by simultaneously precharging the drain capacitor 524 , the source capacitor 526 and the parasitic capacitor 540 and 542 reached. For this purpose, the signal 660 to the selection input 530 and the signals 666 and 668 (φ ₃ , φ ₄ ) to the switches 564 and 554 as in 6C shown activated. The signals 662 and 664 (φ ₁ , φ ₂ ) to the switches 560 and 562 stay low during the readout cycle. The voltage level of the common-mode voltage input 558 (VCM) determines the voltage at the monitor output line 536 and therefore the tension at the knot 544 , The voltage signal (VCM _TFT ) of the common-mode voltage input 558 is low enough to keep the OLED 522 does not turn on. The signal 670 (V _{ON_TFT} ) to the programming _input 532 (V _Data ) is high enough to drive the driver 520 turn.

worin I_TFT der Drain-Strom des Treibertransistors 520, der eine Funktion der Beweglichkeit und von (V_Data – V_CM – V_th) ist. T_int ist die Länge der Integrationsdauer. Die Ausgangsspannung 674, die eine Funktion der Beweglichkeit und der Schwellenspannung des Treibertransistors 520 ist, kann zu jedem Zeitpunkt während der Auslesephase 680 abgetastet werden.At the beginning of the integration phase 678 becomes the signal 668 (φ ₄ ) to the switch 554 switched off so that the charge pump amplifier 550 the current from the driver transistor 520 can integrate. The output voltage 674 of the charge pump amplifier 550 decreases at a constant rate which is a function of the threshold voltage, mobility, and gate-to-source voltage of the driver transistor 520 is. Before the end of the integration phase, the signal becomes 666 (φ ₃ ) to the switch 564 switched off to the charge pump circuit 508 from the drive circuit 502 to isolate. Accordingly, the output voltage is as follows:

where I _{TFT is} the drain current of the driver transistor 520 , which is a function of mobility and of (V _Data - V _CM - V _th ). T _int is the length of the integration period. The output voltage 674 , which is a function of the mobility and threshold voltage of the driver transistor 520 is, at any time during the selection phase 680 be scanned.

6D shows a timing diagram of input signals for the direct reading of the (threshold) voltage of the OLED 522 in 5 , 6D includes voltage signals 682 - 696 for the selection input 530 , the switches 560 . 562 . 564 and 554 , the programming voltage input 532 , the voltage at the node 544 and the output voltage 556 in 5 , The read-out process in 6C indicates a preloading phase 697 , an integration phase 698 and an optional readout phase 699 on.

The read-out process in 6D is done by simultaneously precharging the drain capacitor 524 , the source capacitor 526 and the parasitic capacitor 540 and 542 initiated. For this purpose, the signal 682 to the selection input 530 and the signals 688 and 690 (φ ₃ , φ ₄ ) to the switches 564 and 554 as in 6D shown activated. The signals 684 and 686 (φ ₁ , φ ₂ ) remain low during the read cycle. The voltage level of the common-mode voltage input 558 (VCM) determines the voltage at the monitor output line 536 and therefore the tension at the knot 544 , The voltage signal (VCM _OLED ) of the common-mode voltage input 558 is high enough for the OLED 522 is turned on. The signal 692 (V _{OFF_TFT} ) of the programming _input 532 (V _Data ) is low enough to drive the driver 520 keep off.

At the beginning of the integration phase 698 becomes the signal 690 (φ ₄ ) to the switch 552 switched off so that the charge pump amplifier 550 the power from the OLED 522 can integrate. The output voltage 696 of the charge pump amplifier 550 decreases at a constant rate which is a function of the threshold voltage and voltage at the OLED 522 is.

worin I_OLED der OLED-Strom ist, der eine Funktion von (V_CM – V_th) ist, und T_int die Länge der Integrationsdauer ist. Die Ausgangsspannung, die eine Funktion der Schwellenspannung der OLED 522 ist, kann zu jedem Zeitpunkt während der Auslesephase 699 abgetastet werden.Before the end of the integration phase 698 becomes the signal 668 (φ ₃ ) to the switch 564 switched off to the charge pump circuit 508 from the drive circuit 502 to isolate. Accordingly, the output voltage is as follows:

where I _{OLED is} the OLED current that is a function of (V _{CM -V th} ), and T _{int is} the length of the integration period. The output voltage, which is a function of the threshold voltage of the OLED 522 is, at any time during the selection phase 699 be scanned.

The control 112 in 1 is best implemented using one or more general purpose computing systems, microprocessors, digital signal processors, microcontrollers, application specific integrated circuits (ASIC), programmable logic devices (PLD), field programmable logic devices (FPLD), field programmable gate arrays (FPGAs), and the like, which are taught in accordance with the teachings as described herein and as programmed herein as will be apparent to those skilled in the computer, software and networking arts.

In addition, two or more computing systems or devices may replace any of the controllers described herein. Accordingly, principles and advantages of distributed processing, such as e.g. Redundancy, replication and the like, if desired, may also be implemented to improve the robustness and performance of controls described herein. The controllers may also be implemented in one or more computing systems extending over any network environment, using any suitable interface mechanisms and communication technologies, including, for example, any form of telecommunications (eg, voice, modem, and the like), public switched telephone networks (PSTNs), packet data networks (PDNs), the Internet, intranet networks, a combination thereof, and the like.

The operation of the exemplary data extraction operation will be described below with reference to the flowchart in FIG 7 explained in more detail. The flowchart in 7 is representative of exemplary machine-readable instructions for determining the threshold voltages and the mobility of a simple driver circuit that has a maximum aperture of a pixel 104 in 1 allows. In this example, and in any other flowchart example herein, the machine-readable instructions include an algorithm for execution by: (a) a processor, (b) a controller, and / or (c) one or more other suitable processing device (s). The algorithm may be embedded in software stored on a physical medium, such as a flash memory, a CD-ROM, a floppy disk, a hard disk, a digital (universal) video disc (DVD), or other storage devices, but those skilled in the art will recognize Alternatively, the entire algorithm and / or portions thereof may be performed in a generally known manner by a device other than a processor and / or may be implemented in firmware or dedicated hardware (eg, may be implemented by an application specific integrated circuit). ASIC), programmable logic device (PLD), field programmable logic device (FPLD), field programmable gate array (FPGA), discrete logic, etc.). For example, any or all of the components of the extraction sequence may be implemented by software, hardware, and / or firmware. In addition, some or all of the machine readable instructions represented by the flowcharts herein may be included 7 , be implemented manually. Further, although the exemplary algorithm described with reference to the flowcharts presented herein are included 7 Those skilled in the art will recognize that many other methods of implementing the exemplary machine-readable instructions may alternatively be employed. For example, the execution order of the blocks may be changed, and / or some of the described blocks may be changed, eliminated or combined.

A pixel or a pixel circuit 104 which are being examined is selected by turning on the appropriate selection and programming lines ( 700 ). Once the pixel 104 is selected, the reading is carried out in four phases. The read-out process begins by first checking the parasitic capacitance at the OLED (C _oled ) in the reset phase ( 702 ) is unloaded. Next, the driver transistor is turned on for a certain time, allowing some charge in the capacitance at the OLED C _oled ( 704 ) is accumulated. In the integration _phase , the selection _{transistor is turned off} to isolate the charge of the capacitance at the OLED C _oled , and then the parasitic capacitance line (C _P ) is _precharged to a known voltage level ( 706 ). Finally, the driver transistor is turned on again so that the charge of the capacitance at the OLED C _{oled of} a readout _{phase is} transferred to the charge pump _{amplifier output} ( 708 ). The output of the amplifier represents an amount that is a function of the mobility and the threshold voltage. The read is completed by clearing the pixel selection to prevent interference when calibrating other pixels ( 710 ).

8th FIG. 10 is a flowchart of various extraction cycles and parameter applications for pixel circuits, such as pixel circuits. B. the two-transistor circuit in 2 and the three-transistor circuit in 5 , One method is an in-pixel integration involving a charge transfer ( 800 ). A charge relevant to the parameter of interest is accumulated in the pixel's internal capacitance ( 802 ). The charge is then transmitted to the external readout circuit, such as. B. the charge pump or the integrator to build a proportional voltage ( 804 ). Another method is an off-pixel integration or direct integration ( 810 ). The device current is from the external readout circuit, such. B. the charge pump or the integrator circuit ( 812 ) integrated directly.

In both methods, the generated voltage is post-processed to resolve the parameter of interest, such as. B. the threshold voltage or mobility of the driver transistor or the turn-on voltage of the OLED ( 820 ). The extracted parameters can then be used for various applications ( 822 ). Examples of the use of the parameters include modifying the programming data of the extracted parameters to compensate for pixel variations ( 824 ). Another example is pre-aging the pixel plate ( 826 ). Another example is evaluating the process output of the pixel plate after fabrication ( 828 ).

9 Figure 4 is a block diagram and illustration of the components of a data extraction system that includes a pixel circuit 900 , a control box 902 and a readout circuit 904 which may be a charge pump / integrator. The components ( 910 ) of the pixel circuit 900 include an emission device, such as. B. an OLED, a drive device such. B. a driver transistor, a memory device such. B. a capacitor, and access switches, such. B. a selector switch. The components 912 of the control box 902 comprise a set of electronic switches that can be controlled by external control signals. The components 914 the readout circuit 904 include an amplifier, a capacitor and a reset switch.

The parameters of interest can be as in block 920 be stored represented. The parameters of interest in this example may include the threshold voltage of the driver transistor, the mobility of the driver transistor, and the turn-on voltage of the OLED. The functions of the control box 902 are through the block 922 shown. These functions include directing a stream into and out of the pixel circuit 900 , Providing a discharge path between the pixel circuit 900 and the charge pump of the readout circuit 904 and isolating the charge pump of the readout circuit 904 from the pixel circuit 900 , These functions of the readout circuit 904 are through the block 924 shown. A function includes transmitting a charge from the internal capacitance of the pixel circuit 900 to the capacitor of the readout circuit 904 to generate a voltage proportional to this charge, if it is an in-pixel integration as in step 800 - 804 in 8th is. Another function includes integrating the current of the driver transistor or the OLED of the pixel circuit 900 over a period of time to produce a voltage proportional to this current, as in step 810 - 814 out 8th ,

10 is a timing diagram of the signals that the extraction of the threshold voltage and the mobility of the driver transistor 520 in a modified version of the circuit 5 wherein the gate of the output transistor 534 are connected to a separate control signal line RD, and not to the SEL line. The read-out process in 10 indicates a preloading phase 1001 , an integration phase 1002 and a selection phase 1003 on. During the preloading phase 1001 , the voltages V _A and V _B at the gate and at the source of the driver transistor 520 reset to initial voltages, with the SEL and RD signals both high.

During the integration phase 1002 the signal RD decreases, the gate voltage V _A remains at V _init and the voltage V _B at the source (node 544 ) is charged back to a voltage which is a function of TFT characteristics (including mobility and threshold voltage), e.g. B. (V _init - V _T ). When the integration phase 1002 is long enough, the voltage V _{B is} a function of the threshold voltage (V _T ) alone.

During the selection phase 1003 if the signal SEL is weak, V _A decreases (V _init + Vb - Vt) and V _B decreases to Vb. The charge is from the total capacity C _T at the node 544 to the integrated capacitor (C _int ) 552 in the readout circuit 504 transfer. The output voltage V _out can be determined using an analog-to-digital converter (ADW) at the output of the charge amplifier 550 be read out. Alternatively, a comparator may be used to compare the output voltage with a reference voltage while _adjusting V _init until the two voltages become equal. The reference voltage may be generated by testing the line without having one pixel connected to the line during one phase and by testing the pixel charge in another phase.

11 is a timing diagram for the input signals for the extraction of the on voltage OLED 522 in the modified version of the circuit in 5 ,

12 Figure 12 is a circuit diagram of a pixel circuit for reading the pixel status by externally initializing the nodes. The driver transistor T1 has a drain connected to a supply voltage Vdd, a source connected to an OLED D1, and a gate connected to a Vdata line via a switching transistor. The gate of the transistor T2 is connected to a write line WR. A storage capacitor Cs is connected between a node A (between the gate of the driver transistor T1 and the transistor T2) and a node B (between the source of the driver transistor T1 and the OLED). A readout transistor T3 couples node B to a monitor line and is controlled by the signal on a read line RD.

13 is a timing diagram that indicates an operation of the circuit 12 which initializes the nodes externally. During a first phase P1, the driver transistor T1 is programmed with an OFF voltage V0, and the OLED voltage is externally set to Vrst via the monitor line. During a second phase P2, the read-out signal RD turns off the transistor T3 and the OLED voltage is discharged through the OLED D1 until the OLED turns off (thereby generating the ON threshold voltage of the OLED). During a third phase P3, the OFF voltage of the OLED is transmitted via the monitor line to an external readout circuit (eg, using a charge amplifier).

14 Figure 11 is a flow chart illustrating the reading of the pixel status by externally initializing the nodes. In the first step, the internal nodes are reset so that at least one pixel component is ON. The second step provides time for the internal / external nodes to enter a desired state, e.g. B. the OFF state, settle. The third step reads the values of the OFF state of the internal nodes.

15 is a timing diagram showing the modified operation of the circuit 12 illustrates, wherein the nodes are still initialized internally. During a first phase P1, the driver transistor T1 is programmed with an ON voltage V1. Thus, the OLED voltage rises to a voltage higher than its ON threshold voltage. During a second phase P2, the driver transistor is programmed with an OFF voltage V0 and thus the OLED voltage is discharged through the OLED D1 until the OLED turns off (thereby producing the ON threshold voltage of the OLED). During a third phase P3, the ON threshold voltage of the OLED is transferred to an external readout circuit (eg, using a charge amplifier).

16 Figure 12 is a flow chart illustrating the reading of the pixel status by internally initializing the nodes. The first step turns on the pixels selected for the measurement so that the internal / external nodes settle into the ON state. The second step turns off the selected pixels so that the internal / external nodes settle into the OFF state. The third step reads the values of the OFF state of the internal nodes.

17 is a schematic diagram showing two of the 12 Illustrates pixel circuits, which are connected via the respective readout transistors T3 of the two circuits to a common monitor line, and 18 Figure 4 is a timing diagram illustrating the operation of the combined circuits for reading the pixel charges with the shared monitor line. During a first phase P1, the pixels are programmed with OFF voltages V01 and V03 and the OLED voltage is reset to VB0. During a second phase P2, the read-out signal RD is set to OFF and the pixel intended for the measurement is programmed with an ON-voltage V1, while the other pixel remains in an OFF-state. Therefore, the OLED voltage of the pixel selected for the measurement is higher than its ON threshold voltage while the other pixel connected to the monitor line remains in the reset state. During a third phase P3, the pixel programmed with an ON voltage is also turned off by being programmed with an OFF voltage V02. During this phase, the OLED voltage of the selected pixel discharges to its ON threshold voltage. During a fourth phase P4, the OLED voltage is read back.

19 Figure 10 is a flow chart illustrating the reading of pixel status with a shared monitor line. The first step turns off all pixels and resets the internal / external nodes. The second step turns on all the pixels selected for the measurement so that the internal / external nodes are set to an ON state. The third step turns off the selected pixels so that the internal / external nodes settle into an OFF state. The fourth step reads out the values of the OFF state of the internal nodes.

• 1. Während eines Programmierzyklus wird das Pixel mit einer Programmierspannung V_P programmiert, die dem Knoten A aus der Leitung Vdata über den Transistor T2 bereitgestellt wird, und Knoten B ist über den Transistor T3 mit einer Referenzspannung Vref aus der Leitung VMonitor/Vref verbunden.
• 2. Während eines Entladezyklus schaltet ein Auslesesignal RD den Transistor T3 aus und die Spannung am Knoten B wird somit eingestellt, um eine Schwankung (z. B. Alterung) des Treibertransistors T1 teilweise zu kompensieren.
• 3. Während einer Ansteuerphase schaltet ein Schreibsignal WR den Transistor T2 aus und nach einer Verzögerung (die gleich null sein kann), schaltet ein Signal EM den Transistor T4 ein, um die Versorgungsspannung Vdd mit dem Treibertransistor T1 zu verbinden. Somit wird der Strom des Treibertransistors T1 durch die in einem Kondensator C_S gespeicherte Spannung gesteuert und derselbe Strom geht an die OLED.

20A 1 illustrates a pixel circuit in which a line Vdata (programming voltage) is coupled to a node A via a switching transistor T2 and a line Monitor / Vref (Vref is a reference voltage) is coupled via a readout transistor T3 to a node B. The node A is connected to the gate of a driver transistor T1 and to one side of a storage capacitor Cs. 20B is a timing diagram for the operation of the circuit 20A using a charge-based compensation. The node B is connected to the source of the driver transistor T1 and to the other side of the capacitor Cs, and to the drain of a switching transistor T4 connected between the source of the driver transistor and a supply voltage source Vdd. The operation in this case is as follows:

• 1. During a programming cycle, the pixel is programmed with a programming voltage V _{P provided} to node A from line Vdata via transistor T2, and node B is connected via transistor T3 to a reference voltage Vref from line VMonitor / Vref.
• 2. During a discharge cycle, a read-out signal RD turns off transistor T3 and the voltage at node B is thus adjusted to partially compensate for a variation (eg, aging) in driver transistor T1.
• 3. During a drive phase, a write signal WR turns off transistor T2, and after a delay (which may be zero), a signal EM turns on transistor T4 to connect the supply voltage Vdd to the driver transistor T1. Thus, the current of the driver transistor T1 is controlled by the voltage stored in a capacitor C _S and the same current goes to the OLED.

• 1. Während des Programmierzyklus wird der Knoten A auf die aus der Leitung Vdata über den Transistor T2 bereitgestellte Referenzspannung Vref geladen und dem Knoten B wird eine Programmierspannung Vp aus der Leitung Monitor/Vref über den Transistor T3 bereitgestellt.
• 2. Während des Entladezyklus schaltet das Auslesesignal RD den Transistor T3 aus und die Spannung am Knoten B wird somit eingestellt, um eine Schwankung (z. B. Alterung) des Treibertransistors T1 teilweise zu kompensieren.
• 3. Während der Ansteuerphase schaltet das Schreibsignal WR den Transistor T2 aus und nach einer Verzögerung (die gleich null sein kann), schaltet das Signal EM den Transistor T4 ein, um die Versorgungsspannung Vdd mit dem Treibertransistor T1 zu verbinden. Somit wird der Strom des Treibertransistors T1 durch die im Speicherkondensator C_S gespeicherte Spannung gesteuert und derselbe Strom geht an die OLED.

In a further arrangement, a reference voltage Vref is provided to node A from line Vdata via switching transistor T2, and node B is provided with a programming voltage Vp from the monitor / Vdata line via read-out transistor T3. The operation in this case is as follows:

• 1. During the programming cycle, node A is charged to the reference voltage Vref provided from line Vdata via transistor T2, and node B is provided with a programming voltage Vp from the monitor / Vref line via transistor T3.
• 2. During the discharge cycle, the read-out signal RD turns off the transistor T3 and the voltage at the node B is thus adjusted to partially compensate for a variation (eg, aging) of the driver transistor T1.
• 3. During the drive phase, the write signal WR turns off the transistor T2, and after a delay (which may be zero), the signal EM turns on the transistor T4 to connect the supply voltage Vdd to the driver transistor T1. Thus, the current of the driver transistor T1 is controlled by the voltage stored in the storage capacitor C _S and the same current goes to the OLED.

21 is a timing diagram for the operation of the circuit 20A to generate a readout of the current and / or the voltage of the driver transistor T1. The pixel is programmed either with or without a discharge period. If there is a discharge period, it may be a short time to partially discharge the capacitor C _S , or it may be long enough to discharge the capacitor C _S until the driver transistor T1 is off. In the case of a short discharge time, the current of the driver transistor T1 can be read out by applying a fixed voltage during the readout time or the voltage generated by the driver transistor T1 acting as the amplifier can be detected by applying a fixed current from the monitor / Vref line through the readout transistor T3 be read out. In the case of a long discharge time, the voltage generated at node B due to a discharge can be read back.

22 is a timing diagram for the operation of the circuit 20A to generate a readout of the OLED voltage. In the in 22 In the illustrated case, the pixel circuit is programmed so that the driver transistor T1 acts as a switch (with a high ON voltage) and the current or voltage of the OLED is measured by the transistors T1 and T3. In another case, multiple current / voltage points are measured by changing the voltage at node A and node B, and the voltage of the OLED can be extracted from the equation between the currents and voltages. For example, the OLED voltage affects the current of the driver transistor T1 more when the transistor is operated in the linear operating state; Thus, the OLED voltage can be extracted from the voltage-current relationship of the transistor T1 when the linear and saturated operating states of the driver transistor T1 have current points.

When two or more pixels share the same monitor lines, the pixels not selected for the OLED measurement are turned OFF by applying an OFF voltage to their driver transistors T1.

• 1. Die OLED wird während einer Resetphase mit einer EIN-Spannung geladen.
• 2. Das Signal Vdata schaltet den Treibertransistor T1 während einer Entladephase aus und die OLED-Spannung wird somit durch die OLED auf eine AUS-Spannung entladen.
• 3. Die AUS-Spannung der OLED wird während einer Auslesephase durch den Treibertransistor T1 und den Auslese Transistor T3 zurückgelesen.

23 is a timing diagram for a modified operation of the circuit 20A to generate a reading of the OLED voltage as follows:

• 1. The OLED is charged during a reset phase with an ON voltage.
• 2. The signal Vdata turns off the driver transistor T1 during a discharge phase and the OLED voltage is thus discharged through the OLED to an OFF voltage.
• 3. The OFF voltage of the OLED is read back during a readout phase by the driver transistor T1 and the readout transistor T3.

24 Figure 12 illustrates a circuit for extracting the parasitic capacitance from a pixel circuit by means of external compensation. In most external OLED display compensation systems, the internal nodes of the pixels are different during the measurement and drive cycles.

• 1. Messen des Pixels im Zustand eins mit einem Satz aus Spannungen/Strömen (entweder externe Spannungen/Ströme oder interne Spannungen/Ströme).
• 2. Messen des Pixels in Zustand zwei mit einem anderen Satz aus Spannungen/Strömen (entweder externe Spannungen/Ströme oder interne Spannungen/Ströme).
• 3. Basierend auf einem Pixelmodell, das die parasitären Parameter umfasst, das Extrahieren der parasitären Parameter aus den zwei vorhergehenden Messungen (sind weitere Messungen für das Modell erforderlich, wird Schritt 2 für andere Sätze aus Spannungen/Strömen wiederholt).

Following is a method for compensating a parasitic parameter:

• 1. Measure the pixel in state one with a set of voltages / currents (either external voltages / currents or internal voltages / currents).
• 2. Measure the pixel in state two with another set of voltages / currents (either external voltages / currents or internal voltages / currents).
• 3. Based on a pixel model comprising the parasitic parameters, extracting the parasitic parameters from the two previous measurements (if further measurements are required for the model, step 2 is repeated for other sets of voltages / currents).

Another method is the experimental extraction of the parasitic effect. For example, the two sets of measurements can be subtracted and the difference added to other measurements by a gain. The gain can be extracted experimentally. For example, the scaled difference may be added to a measurement set performed on a panel for a specific gray scale. The scaling factor can be set experimentally until the figure on the panel meets the specifications. This scaling factor can be used as a fixed parameter for all other panels afterwards.

One method for the external measurement of parasitic parameters is the reading of a current. In this case, the external voltage set by a measurement circuit may be changed for two sets of measurements to extract parasitic parameters. 24 shows a pixel with a readout line for measuring the pixel current. The voltage of the readout line is controlled by a measuring unit bias voltage (V _B ).

25 illustrates a pixel circuit that can be used for current measurement. The pixel is programmed with a calibrated programming _voltage V _cal and a monitor line is set to a reference voltage V _ref . Then, the current of a driver transistor T1 is measured by turning on a transistor T3 with a control signal RD. During the drive _cycle , the voltage at node B is at V _oled and the voltage at node A changes from V _cal to V _cal + (V _oled - V _ref ) C _S / (C _P + C _S ) where V _{cal is} the one calibrated Programming voltage, C _{P is} the parasitic total capacitance at node A and V _{ref is} the monitor voltage during programming. The gate-source voltage V _GS of the driving transistor is different during the programming cycle (V _P - V _ref) and the drive cycle of [(V _P - V _ref) C _S / (C _P + C _S) - V _OLED C _P / ( C _P + C _S )]. Therefore, during programming and measurement, the current differs from the drive current due to the parasitic capacitance which will affect the compensation, especially when there is a significant variability in the drive transistor T1.

In order to extract the parasitic effect during the measurement, it is possible to have a different voltage V _B on the monitor line during the measurement than during the programming _cycle (V _ref ). Thus, during the measurement, the gate-source voltage V _GS becomes [(V _{P -V ref} ) C _S / (C _P + C _S ) -V _B C _P / (C _P + C _S )]. Two different V _B (V _B1 and V _B2 ) can be used to extract the value of the parasitic capacitance C _P. In one case, the voltage V _{P is} equal and the current for the two cases will differ. One can use pixel-current equations to extract the parasitic capacitance C _P from the difference in the two currents. In this condition, the difference (V _B1 -V _B2 ) will be C _P / (C _P + C _S ). Thus C _P can be extracted since all parameters are known.

A pixel with a charge read capability is in 26 illustrated. Here either an internal capacitor is charged and the charge is then transferred to a charge integrator or a current is integrated by a charge readout circuit. In the case where the current is integrated, the method described above can be used to extract the parasitic capacitance.

When reading the charge integrated into an internal capacitor is desired, two different integration times can be used to extract the parasitic capacitance in addition to the direct adjustment of the voltages. For example, in the in 25 The OLED capacitance may be used to integrate the pixel current internally and then a charge pump amplifier may be used to externally overhang it. In order to extract the parasitic parameters, the method described above can be used to change voltages. However, due to the nature of charge integration, one can do two Use different integration times if the current is integrated in the OLED capacitor.

As the voltage of node B increases, the effect of the parasitic parameters on the pixel current increases. Thus, the measurement with the longer integration time leads to a higher voltage at the node B and this is thus more affected by the parasitic parameters. The charge values and the pixel equations can be used to extract the parasitic parameters. Another method is to ensure that the normalized measured charge is equal to the integration time for both cases by adjusting the programming voltage. The difference between the two voltages may then be used to extract the parasitic capacitances as discussed above.

Charge-based in-pixel compensation for smart pixels

In 26 For example, the signals and bias lines from each pixel may be shared or replaced by other signals and achieve the same functionality. The pixel circuit off 26 is just an example. One can readily modify the position of the load (eg, a light-emitting diode). Pixel circuits, like those in 26 by using a charge-based in-pixel compensation by building a charge on an internal node of the pixel circuit (usually stored in a storage capacitor C _s ) and allowing at least a portion of that charge to be removed or as a function of T1 and / or the OLED is discharged so that a parameter, such as the threshold voltage of T1, can be developed within the pixel circuit.

In 26 For example, the compensation voltage is generated at node D during programming and the biases are applied to nodes B and C and a program voltage is applied to node C.

To generate the compensation circuit, you can, as in the timing diagram in 26 described, use a discharge method or create a bias current through the monitor line, as described in the previous applications against which this application claims priority.

The addition of switching transistor Tb2 eliminates the unwanted emission during the program / compensation cycle because it redirects the current up to Vb2.

This circuit also allows the reading of the pixel or OLED current / voltage as described elsewhere herein.

This pixel also allows the TFT or OLED current, voltage or charge to be read by Tm.

For reading TFT, the pixel can be programmed with a predefined (or calculated voltage) and then Tm turned ON. Here, the voltage of the monitor line may be lower than the OLED voltage, since Tem is ON. This will ensure that the OLED is off. At this point, the pixel stream can be read. In the other method, WR and RD are ON and EM is OFF and a current or voltage is applied to the monitor and the current or voltage is read back. Likewise, the current or voltage applied to the monitor line may be any value, including zero.

To read the OLED (current or voltage), the pixel can be programmed so that the driver TFT acts as a switch (for example, Vb1 can be set to make Td a switch). Then the OLED current or voltage can be read out by the monitor line.

For further readout of the OLED current or voltage, the EM signal can be switched off, as a result of which no current flows through Td and the OLED current or voltage can be read out.

For further readout of the OLED current or voltage, Vb1 may be selected such that node D goes to V _OLED during the programming cycle. And then the effect of the OLED voltage on the TFT can be read back after the TFT programming.

In 27 For example, the EM signal is divided into two signals. This allows using Tb to reset the node D for the generation of a compensation voltage based on the charge / discharge function as in FIG 27 described in waveform. As can be seen, EM 'can be the EM signal of the next line.

This pixel also allows the TFT or OLED current, voltage or charge to be read by Tm.

For reading TFT, the pixel can be programmed with a predefined (or calculated voltage) and then Tm turned ON. Here, the voltage of the monitor line may be lower than the OLED voltage, since Tem is ON. This will make sure the OLED is off. At this point then the pixel stream will be read. In the other method, WR and RD are ON and EM is OFF and a current or voltage is applied to the monitor and the current or voltage is read back. Likewise, the current or voltage applied to the monitor line may be any value, including zero.

To read out the OLED current or voltage, the pixel may be programmed so that the driver TFT acts as a switch (eg, Vb1 may be set to make Td a switch). Then the OLED current or voltage can be read out by the monitor line.

For further reading of the OLED current or voltage, the EM 'signal may be switched off, whereby no current flows through Td and the OLED current or voltage can be read out.

For further readout of the OLED current or voltage, Vb1 may be selected such that node D goes to V _OLED during the programming cycle. And then the effect of the OLED voltage on the TFT can be read back after the TFT programming.

In 28 For example, the EM signal is divided into two signals. This allows using Tb to reset the node D for the generation of a compensation voltage based on the charge / discharge function as in FIG 28 described in waveform. Likewise, Tm and Tb2 are shared

As can be seen, EM 'can be the EM signal of the next line.

This pixel circuit 104 also allows the reading or extraction of the TFT or OLED current, voltage or charge by Tm.

To read the current or voltage of the driver TFT, the pixel can be programmed with a predefined (or calculated voltage) and then Tm turned ON. In this example, the voltage on the monitor line may be less than the OLED voltage because Tem is ON. This will ensure that the OLED is off. At this point then the pixel stream will be read. Alternatively, WR and RD are ON and EM is OFF and a current or voltage is applied to the monitor and the current or voltage is read back. Likewise, the current or voltage applied to the monitor line may be any value, including zero.

For readout of the OLED (current / voltage / charge), the pixel can be programmed so that the TFT provides a zero current. Then, the OLED current or voltage can be read out by the monitor line.

For further reading of the OLED current or voltage, the EM 'signal may be switched off, whereby no current flows through Td and the OLED current or voltage can be read out.

For further readout of the OLED current or voltage, Vb1 may be selected such that node D goes to V _OLED during the programming cycle. And then the effect of the OLED voltage on the TFT can be read back after the TFT programming.

At the in 29 As shown, the node B is reset during programming by Tm and the monitor line, and node C is loaded onto Vdata while EM is turned off. During the compensation cycle (cycle 4), node B is charged to a compensation voltage with a driver TFT (Td), which is the function of Td characteristics. During the drive cycle (6) is an EM, and thus the gate of Td is defined by the information stored in _S C programming voltage and compensating voltage.

This pixel also allows the TFT or OLED current, voltage or charge to be read by Tm.

To read the current or voltage of the driver TFT, the pixel can be programmed with a predefined (or calculated voltage) and then Tm turned ON. Here, the voltage on the monitor line may be less than the OLED voltage, since Tem is ON. This will ensure that the OLED is off. At this point then the pixel stream will be read. Alternatively, WR and RD are ON and EM is OFF and a current or voltage is applied to the monitor and the current or voltage is read back. Likewise, the current or voltage applied to the monitor line may be any value, including zero.

For reading out the OLED current or voltage, the pixel can be programmed so that the TFT provides a zero current. Then the EM is ON and the OLED current or voltage can be read out through the monitor line.

Programming and driving

In an arrangement of an in 30 The charge-coupled compensation pixel circuit shown in FIG. 2 is the line connected to T2, the data voltage, and the line connected to T3 is the monitor / Vref voltage. The operation in this example can be as follows:
During the first cycle, the pixel is programmed with the programming voltage (VP) and node B is connected to a reference voltage.

During the second cycle, the RD signal turns off and thus the voltage at node B is partially adjusted to compensate for T1 variation (or aging).

During the third phase, the WR signal turns off and after a delay (which can be zero), EM turns on. Thus, the current of the driver transistor T1 is controlled by the voltage stored in CS and the same current goes to the OLED.

In another arrangement, the line connected to T2 is the reference voltage (Vref) and the line connected to T3 is the monitor / Vdata line.

During the first cycle, node A is charged to a reference voltage and node B is connected to a programming voltage (VP).

During the second cycle, the RD signal turns off and thus the voltage at node B is partially adjusted to compensate for T1 variation (or aging).

During the third phase, the WR signal turns off and after a delay (which can be zero), EM turns on. Thus, the current of the driver transistor T1 is controlled by the voltage stored in CS and the same current goes to the OLED.

Reading out the driver TFT

For reading out the driver T1 from its current or voltage, as in 31 shown, the pixel is programmed (either with discharge or without discharge period). If there is a discharge period, it may be a relatively short time to partially discharge the capacitor C _S , or it may be long to discharge the capacitor until the driver T1 is off. In the case of a short discharge time, the current of T1 can be read out by applying a fixed voltage during the readout time or the voltage generated by the driver T1 acting as the amplifier can be read out by applying a fixed current through T3. In the case of a long discharge time, the voltage generated at node B due to a discharge can be read back. This voltage will be representative of the threshold voltage of T1.

Likewise, the WR signal can remain on throughout the procedure.

OLED readout

In the in 32 T1 is programmed to act as a switch (with a high ON voltage). And the current or voltage of the OLED can be measured or extracted by T3 and T1.

In another example, some current / voltage points are measured by changing the voltage at node A and node B1, and from the equation between the currents and voltages, the voltage from OLED can be extracted. For example, the OLED voltage affects the current of T1 more when T1 is in the linear operating state, whereby the OLED voltage can be extracted from the voltage-current relationship of T1 when the linear and saturated operating states of T1 have current points.

When some pixels share the same monitor lines, the pixels that are not selected for the OLED measurement are turned OFF by applying an OFF voltage to T1.

In the in 33 presented pixel circuit is the OLED readout as follows:
The OLED is charged with an ON voltage during the reset phase.

The driver T1 turns off and so the OLED voltage is discharged through the OLED to an OFF voltage.

The OFF voltage is read back through T1.

In the aforementioned pixel circuit, the inverted one of RD or WR may be used as the EM signal (thus, the EM signal may correspond to / RD or / WR). In this case, the signal may be inverted and transmitted to the pixel, or a complementary TFT may be used to generate the inverse function. For example, the NMOS switch can be used for EM-TFT when the PMOS switch is used for RD-TFT.

Similarly, the inverted of the next RD or WR signal (or previous RD Signal) instead can be used as an EM signal of the current line. Likewise, the inverse function of RD and WR may be implemented outside and transmitted to the pixel circuit, or a complementary TFT combination may be used.

34 Figure 12 shows another way to achieve an emission EM function in a charge-based pixel circuit 104 to implement. Here, the inverted one of the control signals RD and WR may be used to generate the emission EM signal. Thereby, the pixel circuit is disconnected from the power source, VDD, if any one of them is ON. Likewise, the inverse function of RD and WR (/ RD and / WR) may be outside the pixel circuit 104 can be implemented and transmitted to them or complementary TFT combinations can be used. Although NMOS TFT may work for T4 and T5, the use of PMOS for these TFTs and NMOS for WR and RD (eg, S2 and S3) is recommended (but not required).

The pixel circuit 104 in 34 comprises a driver transistor T1 connected to a light emitting device (OLED), a memory device (C _S ) coupled to the driver transistor T1 which stores programming information for causing the OLED to emit light in accordance with the programming information via T1. C _S may, but need not, be directly connected via a gate and a first terminal of T1 (source or drain depending on whether T1 is NMOS or PMOS). A second terminal of T1 (the other of source or drain) may be connected to the OLED.

The pixel circuit 104 out 34 includes a first switch S2 connected between T1 and a first line (which may carry programming information Vdata or a reference voltage Vref) for connecting T1 to the first line in accordance with a first signal (eg, WR). The pixel circuit 104 comprises a second switch S3 connected between T1 and a second line (having at least two functions) for connecting the second line to T1 according to a second signal (eg RD). The second line may be used as a monitor line to monitor a current or voltage read from one or more components of the pixel circuit. The second line may also be used to provide a reference voltage Vref or programming information Vdata to an internal node B of the pixel circuit.

The pixel circuit off 34 comprises a third switch (S4) and a fourth switch (S5) connected in series between T1 and a power source Vdd. The third switch S4 and the fourth switch S5 and their respective control signals have an inverse function of the first switch S2 and the second switch S3 and their respective control signals. This means that S2 and S3 can be n-type transistors while S4 and S5 are p-type. Or S2 and S3 may be p-type transistors while S4 and S5 are n-type. Or S2-S5 may be the same type of transistor, n-type or p-type, but S4 and S5 are controlled by signals that are the inverse of a signal that controls S2 or S3. For example, S4 may be controlled by / WR or / RD and S5 may be controlled by / RD or / WR while S2 is controlled by WR and S3 is controlled by RD. Or, instead of the two switches S4 and S5, a single switch can be used with its own control signal. In other words, the inverse function is an opposite state. For example, when the first and second switches are on or controlled by the respective control signals to turn on, the third and fourth switches are off or are controlled by the respective control signals to turn off.

In this example, a minimum of only two control signals are required, RD and WR (and their inverses, which can be derived directly from RD and WR, respectively) to provide both in-pixel compensation and external compensation by reading the pixel circuit current or to reach voltage through the second line. The first line may provide the memory device C _{S with} a program voltage (Vdata) or a reference voltage (Vref) when the first switch S2 is closed.

To internally compensate for shifts in a parameter such as the threshold voltage of T1, the first line sets Vref through the closed S2 (WR is active) to charge the internal node B to Vref. The charge stored in C _S is allowed to discharge for a discharge period until the charge indicates at least a threshold voltage of T 1. WR is deactivated, whereupon the voltage across C _S becomes a function of Vdata - Vdischarge, which is a function of T1 and the OLED.

To read a current or voltage from a device (eg, T1 or the OLED, or both) of the pixel circuit, RD is active to close S3, allowing the current or voltage to be read from the second line (monitor function) , The second line may also be used during a program cycle to provide Vdata to C _S when S3 is closed. In this way, the pixel circuit can be compensated externally by the pixel circuit for variations or aging of the pixel circuit by extracting a circuit parameter using the second line and externally storing the circuit parameter from the pixel circuit. The circuit parameter may be a current or a voltage of at least To or at least the OLED or at least T1 and the OLED.

It is noted that in the pixel circuit in 34 a reference voltage Vref may be provided from either the first line or the second line (but not simultaneously). The charge associated with the provided Vref is held in C _S. Likewise, also a programming voltage Vdata from either the first line or the second line (but not simultaneously) may be provided, and Vdata is stored at least initially in C _S. The OLED emits light in accordance with at least a portion of the stored Vdata. Internal and external compensation can add to or subtract from the programming voltage. This flexibility allows the sharing of one or both lines among multiple columns in the pixel array. The control signals RD and WR may also be shared by a plurality of rows of pixel circuits.

34 also relates to a method of extracting a circuit parameter from a pixel circuit and providing in-pixel compensation of variations or aging of the pixel circuit. The method includes causing an in-pixel compensation to compensate for a variation or aging of the driving device (T1) or the light-emitting device (OLED) or both in the pixel circuit itself by applying a reference voltage (Vref) from a first line or a line second line is applied to a memory device (C _S ) in the pixel circuit to charge the memory device (C _S ) based on the reference voltage (Vref). The method includes extracting the circuit parameter from the pixel circuit using circuitry external to the pixel circuit by closing a switch (S2 or S3) in the pixel circuit to facilitate readout of the circuit parameter (eg, current or voltage through T1, OLED, or T1 and OLED) from the first line or from the second line. The method includes subsequently driving the pixel circuit using programming information (eg, derived from Vdata) that has been compensated based on at least the extracted circuit parameter. The drive cycle is performed while the pixel circuit is disconnected from both the first line and the second line, and two switches (S4 and S5) connected between the drive device (T1) and a power source (VDD) are closed.

Sharing the switches through columns and / or rows

35 shows a pixel circuit according to the prior art. In operation, during programming, EM is off and WR is on.

A current is applied to the pixel by Iref and a program voltage (VP) is applied to Vdata. Biasing is developed at nodes A and B (VB), which is a function of Iref and T1 characteristics. The voltage stored in C _S is VP - VB.

During the drive / emission cycle: an emission signal EM is on and a write signal WR is off. The node C changes from the programming voltage VP to provide a supply voltage VDD. The node A is supplied by the capacitor C _S by bootstrapping and moves with the same value (VDD - VP). Thus, the voltage at node A will be VB + VDD - VP. During this cycle, a VP proportional current compensated for VB will pass through the driver transistor T1 and the OLED.

Operation of in 36 will now be described. The switches can be shared by columns and rows. Tc and Td can be shared with the lines. Ta and Tb can be shared with rows and columns.

If sharing only affects the columns, SEM and SWR can be the same as EM and WR.

If there is also a shared line usage, SEM and SWR act as global signals.

While programming the lines connected to the same SEM and SWR, the SEM is off and SWR is on. During the driving / emission of these lines, SEM is on and SWR off.

The condition of sharing in 37 is the same as the pixel circuit in 36 but the programming cycle is different. During the programming cycle, SEM / EM are off and SWR / WR are on. RD is at the beginning and resets nodes B and A to Vref. RD then turns off and nodes B and A are charged with T1. The charge amount is a function of T1 parameters. Thus, the voltage developed at node A is a function of T1 and is compensated for non-uniformity / aging during the drive / emission cycle.

The operation of the pixel circuit in 36 and the principle of sharing are the same as in 37 ,

38 shows a 3-transistor pixel circuit that can use charge-based compensation. Vdata includes a programming voltage and Vref provides a reference voltage at T3. The control signals RD and WR control T3 and T2, respectively, for each pixel circuit, and the control signals SEM and SWR are global. SR is shared by columns and SEM can be shared by rows / columns.

39A - 49B show various pixel circuits and corresponding timing diagrams for compensating for variations in a parameter of the pixel circuit (eg aging, nonuniformity in the process). Those skilled in the art will understand how to connect the various components shown in the figures. The reference numbers used are consistent with those used throughout the application. T1 is usually the driver transistor which is used to drive the OLED in accordance with a current corresponding to a charge stored in a capacitor C _s . This charge may be self-compensated for effects such as shifts in the threshold voltage of the driver transistor T1. Other transistors are designated T2, T3, T4, etc. The control signals are marked, where RD = read, WR = write, EM = emission. The EM signal controls whether the OLED is turned on for emission. Vdd is a supply voltage. Vdata is a signal line that transmits programming information in the form of a corresponding voltage that may be externally compensated, if necessary, for variations in one or more parameters of the pixel circuit. A line labeled Monitor is a signal line that is used to read or extract a current or voltage from the pixel circuit (eg, from T1, the OLED, or both T1 and the OLED). This extracted current or voltage is used externally by the pixel circuit to compensate for variations in parameters such as aging, including shifts in a threshold voltage of T1 or the OLED or both. In the timing diagrams, programming refers to a programming cycle in which programming information (in the form of a voltage or current) is applied to the Vdata line and stored in C _S. Discharging refers to a discharge period in which charge stored in C _S is allowed to at least partially discharge. During this discharge period, the final voltage of C _{S will} typically settle at a value indicative of a threshold voltage of T1 and is used to internally self-compensate the applied programming voltage Vdata for threshold voltage shifts of T1. Finally, the drive scheme refers to an emission wherein the OLED is connected to the supply voltage VDD and the current flows to the OLED in accordance with the remaining charge stored in the capacitor C _S. Programming / Comp refers to a hybrid cycle in which both programming and internal or external compensation can occur. It is preferred but not required to first compensate internally and then compensate externally. However, the present aspects are not limited to a particular order - external compensation may precede internal compensation. Reset operation refers to resetting the pixel circuit, e.g. B. a charge stored in C _S. A read operation refers to reading out or extracting a current or voltage from the pixel circuit (eg, T1, the OLED or both T1 and the OLED) using the monitor line.

Many different embodiments for both internal and external compensation are described and shown herein. It is to be understood that any combination of any pixel circuit and timing diagram may be used herein. Each pixel circuit described herein may function with any other timing and duty cycle shown herein in any other figure, and any timing or operating cycle may be used or modified to function with each pixel circuit described herein. All voltage levels, equations and timing are merely exemplary and should not be considered as limiting, as those skilled in the art can select any suitable voltage level or duration to implement any particular embodiment.

While certain embodiments and applications of the present invention have been illustrated and described, it is to be understood that the invention is not limited to the precise layout and compositions disclosed herein and that various modifications, changes, and variations can be seen from the foregoing descriptions without departing from the spirit and the spirit in the art Scope of the invention as defined by the following claims, depart.

Claims (17)

A pixel circuit comprising a light-emitting device, comprising: a driver transistor connected to the light-emitting device; a memory device coupled to the driver transistor and storing programming information for causing the light emitting device to emit light in accordance with the programming information via the driver transistor; a first switch connected between the driver transistor and a first line for connecting the driver transistor to the first line in accordance with a first signal; a second switch connected between the driver transistor and a second line for connecting the driver transistor to the second line in accordance with a second signal; a third switch and a fourth switch connected in series between the driver transistor and a power source, the third switch and the fourth switch and their respective control signals having an inverse function to that of the first switch and the second switch and their respective control signals. The pixel circuit of claim 1, wherein the third switch is controlled by the first signal and the fourth switch is controlled by the second signal, or wherein the third switch is controlled by an inverse of the first signal and the fourth switch is controlled by an inverse of the second signal. or wherein the third switch is controlled by the second signal and the fourth switch is controlled by the first signal, or wherein the third switch is controlled by an inverse of the second signal and the fourth switch is controlled by an intervader of the first signal. The pixel circuit of claim 1, wherein the first and second switches are n-type transistors and the third and fourth transistors are p-type transistors, or wherein the first and second switches are p-type transistors and the third and third fourth switches are n-type transistors such that when the first and second switches are turned on, the third and fourth switches are turned off and vice versa. The pixel circuit of claim 1, wherein the first, second, third and fourth switches are controlled only by the first signal and only the second signal and no further signal. The pixel circuit of claim 1, wherein the first line of the memory device provides a programming voltage or reference voltage when the first switch is closed. The pixel circuit of claim 5, wherein the reference voltage from the first line is applied to charge the memory device according to the reference voltage, and wherein the charge stored in the memory device is discharged by the driver transistor so that a voltage on the memory device is a function of at least one of Threshold voltage of the driver transistor is. The pixel circuit of claim 1, wherein the second line is used to read a voltage or current from the pixel circuit, or provides a reference voltage to the pixel circuit when the second switch is closed. The pixel circuit of claim 1, wherein the second line is used to read a voltage or current from the pixel circuit, or provides a programming voltage to the pixel circuit when the second switch is closed. The pixel circuit of claim 1, wherein the memory device is a capacitor and connected directly through a gate and a first terminal of the driver transistor. The pixel circuit of claim 9, wherein a second terminal of the driver transistor is connected to the light-emitting device. The pixel circuit of claim 1, wherein the pixel circuit internally compensates for variations in a threshold voltage of the driver transistor by charging a node connected to the driver transistor to a reference voltage and discharging through the driver transistor to store a charge in the memory device indicating the threshold voltage of the driver transistor , The pixel circuit of claim 11, wherein the pixel circuit is compensated for variations or aging of the pixel circuit external to the pixel circuit by extracting a circuit parameter using the second line and storing the circuit parameter externally of the pixel circuit. A pixel circuit according to claim 12, wherein the circuit parameter is a current or a voltage of at least the driver transistor or at least the light-emitting device or at least the driver transistor and the light-emitting device. The pixel circuit of claim 1, wherein the first switch and the second switch in the Pixel circuit are arranged so that a reference voltage from either the first line or from the second line, but not simultaneously, is provided, wherein the reference voltage charges the storage device so that it holds a charge corresponding to the reference voltage. The pixel circuit of claim 1, wherein the first switch and the second switch in the pixel circuit are arranged to provide a programming voltage from either the first line or the second line, but not simultaneously, wherein the programming voltage is stored in the memory device in that at least part of the programming voltage is used to cause the light-emitting device to emit light in accordance with at least part of the programming voltage. The pixel circuit of claim 1, wherein the inverse function is an opposite state, such that when the first and second switches are turned on or controlled by control signals to turn on, the third and fourth switches are turned off or controlled by control signals to turn off. A method of extracting a circuit parameter from a pixel circuit and providing in-pixel compensation for variations or aging of the pixel circuit, the pixel circuit comprising a light-emitting device, a drive device for providing a programmable drive current to the light-emitting device, a programming input, and a memory device for storing a programming signal, the method comprising: causing an in-pixel compensation to self-compensate for a fluctuation or aging of the driving device or the light-emitting device or both in the pixel circuit by applying a reference voltage from a first line or a second line to a memory device in the pixel circuit, based on the memory device to load on the reference voltage; extracting the circuit parameter from the pixel circuit using circuitry external to the pixel circuit by closing a switch in the pixel circuit to enable the reading of the circuit parameter from the first line or the second line; and subsequently driving the pixel circuit using programming information compensated based on at least the extracted circuit parameter, wherein the driving is performed while the pixel circuit is disconnected from both the first line and the second line and while the two switches connected between the first and second lines Control device and a power source are connected in series, are closed.

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