DE112013007770B3 - DEVICES, METHOD AND SYSTEM FOR TRANSMITTING AND RECEIVING VIA AN INTERFACE - Google Patents

Abstract

An apparatus comprising:a physical layer interface comprising:a clock line configured to support a clock signal;a control interface configured to support one or more control signals, the one or more control signals control signals to effect transitions in connection states according to a state machine;a plurality of data lines arranged to transmit data; anda valid signal line configured to support transmission of a valid signal,wherein transmission of data on the data lines is to be coordinated with transmission of the valid signal on the valid signal line,andwherein the clock line and the valid signal line are different lines.

Description

AREA

This disclosure relates to a computing system and particularly (but not exclusively) to point-to-point interconnects. In particular, the disclosure relates to devices, methods and a system for sending and receiving signals and data via an interface.

BACKGROUND

Advances in semiconductor processing and logic design have enabled an increase in the amount of logic that can reside on integrated circuit devices. As a result, computing system configurations have evolved from systems with one or more integrated circuits to those with multiple cores, multiple hardware threads, and multiple logical processors on individual integrated circuits, as well as other interfaces built into such processors. A processor or integrated circuit typically includes a single physical processor die, where the processor die may include a number of cores, hardware threads, logical processors, interfaces, memories, control hub, and so on.

As a result of the increased ability to pack more processing power into smaller packages, smaller computing devices have grown in popularity. Smartphones, tablets, ultra-thin notebooks and other end devices have grown exponentially. However, these smaller devices depend on servers for both data storage and complex processing operations that exceed the form factor. Consequently, the demand for in the high-performance computing market (i.e. server space) has also increased. For example, in modern servers, there is typically not just a single processor with multiple cores, but multiple physical processors (also known as multiple sockets) to increase processing power. However, as processing power increases along with the number of devices in your computing system, communication between sockets and other devices becomes more critical.

In fact, interconnects have evolved from more traditional multipoint buses that primarily managed electrical communications to mature interconnect architectures that enable high-speed communications. Unfortunately, as the demand for future processors consuming at even higher speeds increases, so will the demand for capacity in existing interconnect architectures.

US 2013/0007483 A1 relates to a method and apparatus for reducing idle power of a platform. In US 2013/0007483 A1 describes that a host and endpoints coupled to the host in the platform each have a low-power idle state that allows high-speed interconnect circuitry to be disabled in both the host and the coupled endpoints.

SUMMARY OF THE INVENTION

It can therefore be seen as an object of the present invention to enable a receiving device to prepare for the reception of data and to maintain synchronization even with relatively long physical connection paths.

The above object is achieved according to the invention with the device according to independent claim 1, the device according to independent claim 10, the method according to independent claim 18 and the system according to independent claim 21. The dependent claims define developments of the devices according to the invention, the method according to the invention and the system according to the invention.

character list

• 1 Figure 1 shows an embodiment of a computing system that includes an interconnect architecture.
• 2 Figure 12 shows an embodiment of an interconnect architecture comprising a layer stack.
• 3 Figure 1 shows one embodiment of a request or packet to be generated or received in an interconnect architecture.
• 4 Figure 1 shows one embodiment of a transmitter and receiver pair for an interconnect architecture.
• 5 Figure 1 shows an embodiment of a multi-chip package.
• 6 Figure 12 is a simplified block diagram of a multi-chip package interconnect (MCPL).
• 7 Figure 12 is an illustration of an example signaling on an example MCPL.
• 8th Figure 12 is a simplified block diagram showing a data lane in an example MCPL.
• 9 12 is a simplified block diagram showing example crosstalk cancellation techniques in one embodiment of an MCPL.
• 10 12 is a simplified circuit diagram showing example crosstalk cancellation components in one embodiment of an MCPL.
• 11 is a simplified block diagram of an MCPL.
• 12 Figure 12 is a simplified block diagram of an MCPL interfacing with upper layer logic of multiple protocols using a logical PHY interface (LPIF).
• 13 Figure 12 is an illustration of an example signaling on an example MCPL in connection with a connection reestablishment.
• 14A-14C are exemplary bit maps of data onto lanes of an exemplary MCPL.
• 15 Figure 12 is an illustration of a portion of an example connection state machine.
• 16 Figure 12 is an illustration of a process associated with an example centering of a connection.
• 17 Figure 12 is an illustration of an example connection state machine.
• 18 Figure 12 is an illustration of signaling for entering a low power state.
• 19 Figure 12 shows one embodiment of a block diagram for a computing system that includes a multi-core processor.
• 20 Figure 12 shows another embodiment of a block diagram for a computing system that includes a multi-core processor.
• 21 Figure 12 shows one embodiment of a block diagram for a processor.
• 22 Figure 12 shows another embodiment of a block diagram for a computing system that includes a processor.
• 23 Figure 1 shows an embodiment of a block for a computing system comprising multiple processors.
• 24 FIG. 1 shows an example system implemented as a system on chip (SoC).

Similar reference numbers and designations in the different drawings indicate similar elements.

DETAILED DESCRIPTION

In the following description, numerous specific details are set forth such as examples of specific types of processors and system configurations, specific hardware structures, specific architectural and microarchitectural details, specific register configurations, specific instruction types, specific system components, specific dimensions/heights, specific processor pipeline stages and operations, etc . to provide a thorough understanding of the present invention. However, it will be apparent to those skilled in the art that these specific details need not be employed in order to practice the present invention. In other instances, well-known components or processes, such as specific and alternative processor architectures, specific logic circuits/codes for described algorithms, specific firmware codes, specific interconnect operations, specific logic configurations, specific manufacturing techniques and materials, specific compiler implementations, specific representations of algorithms in code, specific shutdown and gating techniques/logics, and other specific operational details of a computing system have not been described in detail to avoid unnecessarily obscuring the present invention.

While the following embodiments may be described in terms of power conservation and energy efficiency in specific integrated circuits, such as computing platforms or microprocessors, other embodiments may be employed with other types of integrated circuits and logic devices. Similar methods and teachings of embodiments described herein can also be used for other types of circuits or semiconductor devices that can also benefit from better energy efficiency and energy saving. For example, the present embodiments are not limited to desktop computing systems or Ultrabooks™. They can also be used in other devices such as handhelds, tablets, other thin notebooks, systems on a chip (SOC) devices, and embedded applications. Some examples of handheld devices include cell phones, internet protocol devices, digital cameras, personal digital assistants (PDAs), and handheld PCs. Embedded applications typically include a microcontroller, digital signal processor (DSP), system on chip, network computer (NetPC), set-top box, network hub, wide area network (WAN) switch, or any other system that performs the functions and operations taught below can. Additionally, the devices, methods, and systems described herein are not limited to physical computing devices, but may also relate to software optimizations for power conservation and efficiency. As will be apparent from the description below, the embodiments of the methods, devices, and systems described herein (whether in terms of hardware, firmware, software, or a combination thereof) are critical to a future that balances green technology and performance .

With the further development of computing systems, the components they contain are becoming increasingly complex. As a result, the complexity of the interconnect architecture for coupling and communicating between the components to ensure that bandwidth requirements for optimal operation of the components are met is also increased. Also, different market segments have different requirements for providing different aspects of interconnect architectures to meet their needs. For example, servers require higher performance, while the mobile ecosystem can sometimes sacrifice overall performance to save energy. Despite this, the goal of most structures is to provide the highest possible performance with maximum energy savings. Below are a few compounds that would potentially benefit from aspects of the invention described herein.

An interconnect fabric architecture includes the Peripheral Component Interconnect (PCI) Express (PCIe) architecture. A key goal of PCIe is to allow components and devices from different vendors to interoperate in an open architecture to span multiple market segments; Clients (desktop and mobile), servers (standard and enterprise) and embedded and communication devices. PCI Express is a general-purpose, high-performance I/O interconnect defined for a variety of future computing and communications platforms. Some PCI characteristics, such as its usage model, load-memory architecture, and software interfaces, have been retained through revisions, while previous parallel bus implementations have been replaced with a highly scalable, fully serial interface. Newer versions of PCI Express take advantage of advances in point-to-point connections, switch-based technology, and packetized protocols to deliver new levels of performance and functionality. Power management, quality of service (QoS), hot-plug/hot-swap support, data integrity, and error recovery are some of the advanced features supported by PCI Express.

With reference to 1 Illustrated is an embodiment of a structure made up of point-to-point links connecting a group of components. System 100 includes a processor 105 and a system memory 110 coupled to a controller hub 115 . Processor 105 includes any processing element such as a microprocessor, host processor, embedded processor, coprocessor, or other processor. Processor 105 is coupled to controller hub 115 via front side bus (FSB) 106 . In one embodiment, FSB 106 is a point-to-point serial link, as described below. In another embodiment, link 106 includes a serial, differential interconnect architecture that conforms to various link standards.

System memory 110 includes any storage device, such as random access memory (RAM), non-volatile (NV) memory, or other memory accessible to devices in system 100 . System memory 110 is coupled to controller hub 115 through memory interface 116 . Examples of a memory interface include a double data rate (DDR) memory interface, a dual channel DDR memory interface, and a dynamic RAM (DRAM) memory interface.

In one embodiment, controller hub 115 is a root hub, root complex, or root controller in a Peripheral Interconnect Express (PCIe or PCIE) interconnect hierarchy. Examples of controller hub 115 include a chipset, a memory controller hub (MCH), a northbridge, an interconnect controller hub (ICH), a southbridge, and a root controller/hub. Often the term chipset refers to two physically separate controller hubs, i.e. a memory controller hub (MCH) coupled to an interconnect controller hub (ICH). It should be noted that current systems often have the MCH integrated into processor 105, with controller 115 used to communicate with I/O devices in a manner similar to that described below. In some embodiments, peer-to-peer routing may be supported by a root complex 115.

Here controller hub 115 is coupled to switch/bridge 120 through serial link 119 . Input/output modules 117 and 121, which may also be referred to as interfaces/ports 117 and 121, include/implement a layered protocol stack for providing communication between controller hub 115 and switch 120. In one embodiment, multiple devices may be coupled to switch 120 become.

Switch/bridge 120 routes packets/messages from device 125 upstream, i.e. up a hierarchy to a root complex, to control hub 115 and downstream, i.e. down a hierarchy away from root control, from processor 105 or system memory 110 to device 125. Switch 120 is referred to in one embodiment as a logical group of multiple virtual PCI-to-PCI bridge devices. Device 125 includes any internal or external device or component to be coupled to an electronic system, such as an I/O device, a network interface controller (NIC), a daughter card, an audio processor, a network processor, a hard drive, a storage device, a CD/DVD ROM, a monitor, a printer, a mouse, a keyboard, a router, a portable storage device, a firewire device, a universal serial bus (USB) device, a scanner, and other input/output devices. In PCIe jargon, such a device is often referred to as an end device. While not specifically shown, device 125 may include a PCIe to PCI/PCI-X bridge to support legacy or other versions of PCI devices. End device devices in PCIe are often referred to as end devices with integrated legacy, PCIe, or root complex.

Graphics accelerator 130 is also coupled to controller hub 115 through serial link 132 . In one embodiment, graphics accelerator 130 is coupled to an MCH that is coupled to an ICH. Switch 120, and accordingly I/O device 125, is then coupled to the ICH. I/O modules 131 and 118 are also used to implement a layered protocol stack for communication between graphics accelerator 130 and controller hub 115. Similar to the discussion of the MCH above, a graphics controller or the graphics accelerator 130 itself may be integrated into the processor 105.

With reference to 2 An embodiment of a layered protocol stack is shown. Layered protocol stack 200 includes any form of layered communications stack, such as a Quick Path Interconnect (QPI) stack, a PCIe stack, a next-generation high-performance computing interconnect stack, or any other layered stack. Although the explanation immediately below with reference to 1-4 refers to a PCIe stack, the same concepts can be applied to other interconnect stacks. In one embodiment, protocol stack 200 is a PCIe protocol stack that includes transaction layer 205, link layer 210, and physical layer 220. FIG. An interface, such as interface 117, 118, 121, 122, 126, and 131 in 1 , may be represented as communication protocol stack 200 . A communications protocol stack representation may also be referred to as a module or interface that implements/comprises a protocol stack.

PCI Express uses packets to transfer information between components. Packets are formed in the transaction layer 205 data link layer 210 to transfer the information from the sending component to the receiving component. As the transmitted packets travel through the outer layers, they are tagged with additional information necessary to manage packets in those layers. At the receiving end, the reverse process takes place and packets are converted from their representation in the physical layer 220 to their representation in the data link layer 210 and finally (for transaction layer packets) to the form that can be processed by the transaction layer 205 of the receiving device.

transaction layer

In one embodiment, the transaction layer 205 serves to provide an interface between the processing core of a device and the interconnect architecture, e.g. a data link layer 210 and a physical layer 220. In this context, the main task of the transaction layer 205 is to assemble packets (i.e. transaction layer packets or TLPs) and to take apart The transaction layer 205 typically manages credit-based flow control for TLPs. PCIe implements split transactions, i.e. transactions in which request and response are separated in time, allowing one connection to carry other traffic while the target device collects data for the response.

Also, PCIe uses credit-based flow control. In this scheme, a device specifies an initial amount of credits for each of the receive buffers in transaction layer 205. An external device at the opposite end of the link, such as Control Hub 115 in 1 , counts the number of credits consumed by each TLP. A transaction can be transferred if the transaction does not exceed a credit limit. Upon receipt of a response, the credit amount is reset. An advantage of a credit scheme is that the latency of credit restoration does not affect performance until the credit limit is reached.

In one embodiment, four transaction address spaces include a configuration address space, a memory address space, an input/output address space, and a message address space. Memory space transactions comprise one or more of read requests and write requests to transfer data from/to a location mapped in memory. In one embodiment, memory space transactions are capable of using two different address formats, e.g., a short address format, such as a 32-bit address, or a long address format, such as a 64-bit address. Configuration space transactions are used to access configuration space of PCIe devices. Transactions on configuration space include read requests and write requests. Message space transactions (or simply messages) are defined to support in-band communication between PCIe agents.

Therefore, in one embodiment, transaction layer 205 assembles header/payload 206. The format for current headers/payloads can be found in the PCIe specifications and on the PCIe specification webpage.

With reference to 3 1 briefly illustrates one embodiment of a PCIe transaction descriptor. In one embodiment, transaction descriptor 300 is a mechanism for carrying transaction information. In this regard, transaction descriptor 300 supports identification of transactions in a system. Other possible applications include tracking modifications to standard transaction orders and associating a transaction with channels.

Transaction descriptor 300 includes a global identifier 302 field, an attribute 304 field, and a channel identifier 306 field. In one embodiment, the global transaction identifier 302 is unique to all outstanding requests.

According to one embodiment, the local transaction identifier field 308 is a field generated by a request agent and is unique to all outstanding requests that require completion for that request agent. Also in this example, the source identifier 310 uniquely identifies the request agent within a PCIe hierarchy. Accordingly, the local transaction identifier 308, together with the source ID 310, provides global identification of a transaction within a hierarchical domain.

Attribute field 304 specifies properties and relationships of the transaction. In this context, attribute field 304 may be used to provide additional information that allows modification of the standard management of transactions. In one embodiment, attribute field 304 includes priority field 312, reserved field 314, order field 316, and eavesdrop field 318. Here, priority subfield 312 may be modified by an initiator to prioritize the transaction. The reserved attribute field 314 is reserved for future or supplier-defined use. Possible usage models using priority or security attributes can be implemented using the reserved attribute field.

In this example, the ordering attribute field 316 is used to provide optional information specifying the type of ordering that may alter the default ordering rules. According to an example implementation, an ordering attribute of "0" indicates that standard ordering rules apply, while an ordering attribute of "1" indicates relaxed ordering, where writes can propagate writes in the same direction and read completions can propagate writes in the same direction. The listening attribute field 318 is used to determine whether transactions are being listened to. As shown, channel ID field 306 identifies a channel with which a transaction is associated.

connection layer

Link layer 210, also referred to as data link layer 210, serves as an intermediary between transaction layer 205 and physical layer 220. In one embodiment, a function of data link layer 210 is to provide a reliable mechanism for exchanging transaction layer packets (TLPs) between two components of a connection. One side of the data link layer 210 accepts TLPs assembled by the transaction layer 205, applies packet sequence identifier 211, i.e. an identification number or packet number, calculates and applies an error detection code, i.e. CRC 212, and assigns the modified TLPs to the physical layer 220, to be sent via a physical to an external device.

physical layer

In one embodiment, the physical layer 220 includes a logical sub-block 221 and an electrical sub-block 222 to physically transmit a packet to an external device. Here a logical sub-block 221 is responsible for the "digital" functions of the physical layer 221. In this context, the logical sub-block comprises a transmit section for providing outgoing information for transmission by a physical sub-block 222 and a receiver section for identifying and preparing received information, before being forwarded into the link layer 210.

The physical block 222 includes a transmitter and a receiver. The sender is provided with symbols by a logical sub-block 221, which the sender serializes and transmits to an external device. The receiver is supplied with serialized symbols from an external device and converts the received signals into a bit stream. The bit stream is deserialized and passed to logical sub-block 221. In one embodiment, an 8b/10b transmission code is employed, with ten-bit symbols being transmitted/received. Special symbols are used here to enclose a packet with frame 223. In addition, in one example, the receiver also provides a symbol clock extracted from the incoming serial stream.

As noted above, while transaction layer 205, link layer 210, and physical layer 220 are discussed in relation to a specific embodiment of a PCIe protocol stack, a layered protocol stack is not so limited. In fact, any layered protocol can be included/implemented. As an example, a port/interface illustrated as a layered protocol includes: (1) a first layer for assembling packets, i.e., a transaction layer; a second layer for sequencing packets, i.e. a link layer; and a third layer for sending the packets, i.e. a physical layer. As a specific example, a layered protocol of a common standard interface (CSI) is used.

With reference to 4 Next, an embodiment of a PCIe serial point-to-point structure is presented. While one embodiment of a PCIe serial point-to-point link is illustrated, a serial point-to-point link is not limited to being everyone includes a large transmission path for sending serial data. In the illustrated embodiment, a basic PCIe link includes two differentially powered low voltage signal pairs: a transmit pair 406/411 and a receive pair 412/407. Accordingly, device 405 includes transmit logic 406 for transmitting data to device 410 and receive logic 407 for receiving data from device 410. In other words, two transmit paths, i.e. path 416 and 417, and two receive paths, i.e. path 418 and 419, are in a PCIe connection included.

A transmit path refers to any path for sending data, such as a transmit line, a copper line, an optical line, a wireless communication channel, an infrared communication link, or any other communication path. A link between two devices, e.g., device 405 and device 410, is referred to as a link, e.g., link 415. A link may support one lane - each lane represents a set of differential signal pairs (one pair to transmit, one pair to receive). To scale bandwidth, a link may aggregate multiple lanes, denoted by xN, where N is any supported link width, such as 1, 2, 4, 8, 12, 16, 32, 64, or more.

A differential pair refers to two transmit paths, such as lanes 416 and 417, for transmitting differential signals. For example, when line 416 switches from a low voltage value to a high voltage value, i.e., a rising edge, line 417 drives from a high logic level to a low logic level, i.e., a falling edge. Differential signals may have better electrical properties, such as better signal integrity, i.e. cross-coupling, voltage overshoot/undershoot, ringing, etc. This allows for a better timing window that allows for faster transmit frequencies.

5 5 is a simplified block diagram 500 showing an example multi-chip package 505 that includes two or more chips or dies (eg, 510, 515) that are connected using an example multi-chip package interconnect (MCPL) 520 for communication. In 5 While an example of two (or more) dies connected using an exemplary MCPL 520 is illustrated, it should be understood that the principles and features described herein apply to implementations of an MCPL for any interconnect or connection between a die (eg 510) and other components may be applied, including connecting two or two or more dies (e.g. 510, 515), connecting a die (or chips) to another component not on a die, connecting a die with another device or die not in the package (eg 505), the connection of a die to a BGA package, the implementation of a Patch on Interposer (POINT), as one of possible other examples.

In general, a multi-chip package (e.g., 505) can be an electronics package in which multiple integrated circuits (ICs), semiconductor dies, or other individual components (e.g., 510, 515) are packaged on a unifying substrate (e.g., silicon or other semiconductor substrate), representing the Allows the combined components to be used as a single component (e.g. as if it were a larger IC). In some cases, the larger components (e.g., 510, 515 dies) may be IC systems themselves, such as systems on a chip (SoC), multiprocessor chips, or other components that combine multiple components (e.g., 525-530 and 540-545) on the device, for example on a single die (e.g. 510, 515). Multi-chip packages 505 can provide flexibility in building complex and diverse systems from potentially multiple separate components and systems. For example, each of the dies 510, 515 may be fabricated or otherwise provided from two different units, with the silicon substrate of the package 505 being provided by a third unit, to cite one of many examples. In addition, dies and other components within a multi-chip package 505 may themselves contain interconnect or other communication structures (e.g., 535, 550) that provide the infrastructure for communication between components (e.g., 525-530 and 540-545) within the device (e.g., 510 and .515). The various components and interconnects (e.g. 535, 550) may support or utilize several different protocols. Furthermore, communication between dies (e.g. 510, 515) may potentially involve transactions between the various components on the dies over several different protocols. Designing mechanisms to provide communication between chips (or dies) on a multi-chip package can be challenging, as traditional solutions utilize highly specialized, expensive, and package-specific solutions based on specific combinations of components (and desired transactions) to be connected .

The examples, systems, algorithms, devices, logic, and features described in this specification may address at least some of the issues identified above, including possibly many others not mentioned herein. For example, in some implementations, a high-bandwidth, low-power, and low-latency interface may be provided to connect a host device (eg, a CPU) or other device to a corresponding chip contained in the same package as the host. Such a multichip package interconnect (MCPL) can support multiple package options, multiple I/O protocols, and reliability, availability and serviceability (RAS) features. Furthermore, the physical layer (PHY) may include an electrical layer and a logic layer, and may support longer channel lengths, including channel lengths of up to, and in some cases greater than, about 45 mm. In some implementations, an example MCPL can run at high data rates, including data rates in excess of 8-10 Gb/s.

In an exemplary implementation of an MCPL, a PHY electrical layer may provide an improvement over traditional multi-channel interconnect solutions (e.g., multi-channel DRAM I/O), thereby expanding the data rate and channel configuration, such as by adding a number of features, such as regulated mid-rail termination, active Low-power crosstalk suppression, circuit redundancy, per-bit duty cycle correction and skew removal, line encoding, and transmitter equalization, to name a few of many examples.

In an exemplary implementation of an MCPL, a PHY logic layer may be implemented, which may additionally support data rate extension and channel configuration (e.g., electrical layer features), while also allowing the connection to route multiple protocols through the electrical layer. Such implementations may provide and define a modular common physical layer that is protocol independent and has an architecture to work with potentially any existing or future link protocol.

On 6 Referring now to FIG. 1, a simplified block diagram 600 depicting at least a portion of a system that is an example implementation of a multi-chip package interconnect (MCPL) is presented. An MCPL may be implemented using physical electrical connections (e.g., wires implemented as traces) connecting a first device 605 (e.g., a first die that includes one or more subcomponents) to a second device 610 (e.g., a second die that includes one or more subcomponents). comprises several subcomponents) connects. In the particular example shown in the high-level representation 600, all signals (in channels 615, 620) may be unidirectional, and lanes for the data signals may be provided to receive both upstream and downstream data transmission. Block diagram 600 off 6 while referring to the first component 605 as the upstream component and to the second component 610 as the downstream component, as well as to the physical lanes of the MCPL used in sending data as the downstream channel 615, and lanes leading to the receiving data (from component 610) as downstream channel 620, however, it should be understood that the MCPL between devices 605, 610 may be used by any device to both transmit and receive data between the devices.

In an example implementation, an MCPL may provide a physical layer (PHY) that includes the electrical MCPL PHY 625a,b (or collectively 625) and the executable logic implementable MCPL logic PHY 630a,b (or collectively 630). The electrical or physical PHY 625 may provide the physical connection over which data is transmitted between devices 605,610. Signal conditioning components and logic may be implemented in conjunction with the physical PHY 625 to provide high data rate and link channel configuration capabilities, which in some applications may include densely clustered physical links with lengths of about 45 mm or more. The logical PHY 630 may include logic to facilitate clocking, link state management (e.g. for link layers 635a, 635b), and protocol multiplexing between potentially multiple, different protocols used for communications over the MCPL.

In an example implementation, the physical PHY 625 for each channel (eg, 615, 620) may include a set of data lanes over which in-band data may be sent. In this particular example, 50 data lanes are provided in each of the upstream and downstream channels 615, 620, although any other number of lanes may be used if design and power constraints, desired applications, device limitations, etc. allow. Each channel can also have one or more dedicated lanes for a scan, or clock, signal for the channel, one or more dedicated lanes for a valid signal for the channel, one or more dedicated lanes for a power signal, and one or more dedicated lanes for a link state machine management or sideband signal. The physical PHY may further include a sideband link 640, which in some examples may be a bi-directional low frequency control signal link used to coordinate state transitions and other attributes of the MCPL connecting the devices 605, 610, to cite one of several examples.

As noted above, multiple protocols can be supported using an implementation of the MCPL. Indeed, multiple independent transaction layers 650a, 650b may be provided at each device 605, 610. For example, each device 605, 610 may support and use two or more protocols such as PCI, PCIe, QPI, Intel In-Die Interconnect (IDI), among others. IDI is a coherent protocol used on the bare chip to communicate between cores, last level caches (LLCs), memory, graphics and IO controllers. Other protocols may also be supported, including Ethernet protocol, Infiniband protocols, and other protocols based on PCIe fabrics. The combination of the logic PHY and physical PHY can also be used as a die-to-die interconnect to connect a SerDes PHY (PCIe, Ethernet, Infiniband, or other high-speed SerDes) on a die to the upper layers that are implemented on the other die, to name one of several examples.

Logic PHY 630 can support multiplexing between these multiple protocols on an MCPL. For example, the dedicated data stream path can be used to assert an encoded data stream signal that identifies which protocol is to be applied to data sent substantially simultaneously on the data paths of the channel. Furthermore, logic PHY 630 can be used to automatically adjust the different types of link state transitions that the different protocols support or require. In some cases, LSM_SB signals sent over the channel's dedicated LSM_SB lane may be used in conjunction with the sideband link 640 to communicate and automatically adjust link state transitions between the devices 605, 610. Furthermore, link training, error detection, skew detection, skew removal, and other functionalities of conventional links may be partially replaced or controlled using logic PHY 630 . For example, valid signals sent over one or more dedicated valid signaling lanes in each channel can be used to signal link activity, detect skew, link errors, and implement other features, to name a few examples. In the specific example 6 multiple valid lanes are provided per channel. For example, data lanes may be bundled or clustered (physically and/or logically) within a channel, and a valid lane for each cluster may be provided. Furthermore, multiple scan lanes may be provided, in some cases also to provide a dedicated scan signal for each burst in a plurality of data lane bursts in a channel, for example.

As noted above, logic PHY 630 may be used to automatically adjust and manage link control signals sent between devices connected through the MCPL. In some implementations, logic PHY 630 may include link layer packet (LLP) generation logic 660 that may be used to send link layer control messages over the MCPL (i.e., in-band). Such messages may be sent over data lanes of the channel, the data stream identifying the data as representing link layer-to-link layer messaging, such as link layer control data, for example. Link layer messages enabled using an LLP module 660 can support the automatic adjustment and performance of link layer state transitions, power management, looping, deactivation, re-centering, scrambling, among other link layer features, between the link layers 635a, 635b of devices 605 and 610, respectively.

On 7 Referring now to FIG. 7, a diagram 700 is presented showing an example signal transmission using a set of lanes (eg, 615, 620) in a particular channel of an example MCPL. In the example off 7 two bundles of twenty-five (25) data lanes are provided for a total of fifty (50) data lanes in the channel. A portion of the traces are shown while others (eg, DATA[4-46] and a second strobe signal trace (STRB)) are omitted (eg, as redundant signals) for ease of illustration of the specific example. When the physical layer is in an active state (e.g. not powered down or in a low power mode (e.g. an L1 state)), scanning paths (STRB) can be provided with a synchronous clock signal. In some implementations, data can be sent on both the rising and falling edges of the sample. Each edge (or half-clock cycle) can delimit a unit interval (UI). Accordingly, in this example, one bit (eg, 705) can be sent on each lane, so one byte can be sent every 8 UI. A byte period 710 can be defined as 8 UI, or the time it takes to send a byte on a single one of the data lanes (eg, DATA[0-49]).

In some implementations, a valid signal transmitted on one or more dedicated valid signal channels (e.g., VALID0, VALID1) may serve as a leading indicator for the receiving device to identify, if committed (high), for the receiving device or sink that data is sent from the sending device, or source, on data lanes (e.g., DATA[0-49]) during the following time period, e.g., one byte period 710. Alternatively, if the valid signal is low, the source indicates to the sink that the sink will not send data on the data lanes for the following period of time. Accordingly, if the sink logic PHY determines that the valid signal is not asserted (e.g., on lanes VALID0 and VALID1), the sink can retrieve any data that is on the data lanes (e.g., DATA[0-49]) during the following period be detected, ignore. For example, crosstalk or other bits may appear on one or more of the data lanes when the source is not actually sending data. Based on a low, or unasserted, valid signal during the previous period (e.g., the previous byte period), the sink may determine to ignore the data lanes during the following period.

Data sent on either lane of the MCPL may be strictly aligned with the strobe signal. A time period may be defined based on the sample, such as a byte time period, and each of these durations may correspond to a defined window in which signals on the data lanes (e.g., DATA[0-49]), the valid lanes (e.g., VALID1, VALID2) and the data flow path (e.g. STREAM) are to be sent. Accordingly, matching these signals may allow identification that a valid signal in a previous time period window applies to data in the subsequent time period window and that a data stream signal applies to data in the same time period window. The data stream signal may be an encoded signal (e.g. 1 byte of data for one byte time window) encoded to identify the protocol applicable to data sent during the same time window.

For illustration, the specific example is off 7 defines a byte time window. A valid is asserted at a time period window n (715) before any data is sent onto data lanes DATA[0-49]. In the following time window n+1 (720), data is sent on at least one of these data paths. In this case, data is sent on all fifty data lanes during n+1 (720). Since a valid for the duration of the previous duration window n (715) has been asserted, the sink device can validate the data received on data lanes DATA[0-49] during the duration window n+1 (720). Also, the leading nature of the valid signal during duration window n (715) allows the receiving device to prepare for the incoming data. With the example out 7 continuing, the valid signal remains asserted (on VALID1 and VALID2) for the duration of duration window n+1 (720), resulting in the sink device awaiting the data to be sent over lanes DATA[0-49] during duration window n+ 2 (725) to be sent. If the valid signal remained asserted during duration window n+2 (725), the sink device could still expect to receive (and process) more data sent during an immediately following duration window n+3 (730). In the example off 7 however, the valid signal is deasserted during duration window n+2 (725), indicating to the sink device that no data will be sent during duration window n+3 (730) and that any bits written on data lanes DATA[0- 49] should be detected while duration windows n+3 (730) should be ignored.

As noted above, multiple valid trajectories and scan trajectories can be maintained per channel. This can, among other benefits, help preserve the simplicity of the circuitry and synchronization between the bursts of relatively long physical traces connecting the two devices. In some implementations, a set of data lanes can be divided into bundles of data lanes. In the example off 7 For example, data lanes DATA[0-49] may be divided into two twenty-five lane bundles, and each bundle may include a dedicated valid and scan lane. For example, valid lane VALID1 may be associated with data lanes DATA[0-24] and valid lane VALID2 may be associated with data lanes DATA[25-49]. The signals on each "copy" of the valid and scan trajectories for each bundle may be identical.

As introduced above, data on data stream lane STREAM can be used to indicate to the receive logic PHY which protocol to apply for corresponding data sent on data lanes DATA[0-49]. In the example off 7 a data stream signal is sent on STREAM during the same time duration window as data on data lanes DATA[0-49] to indicate the history of the data on the data lanes. In alternative implementations, the data stream signal may be sent during a previous time duration window, for example with corresponding valid signals, to name one of possible other modifications. With the example out 7 however, a data stream signal 735 encoded to indicate the protocol (e.g., PCIe, PCI, IDI, QPI, etc.) to be applied to the bits carried over data lanes DATA[0 -49] are sent during duration windows n+1 (720). Similarly, another data stream signal 740 may be sent during the subsequent duration window n+2 (725) to indicate the protocol to be applied to the bits transmitted over data lanes DATA[0-49] during duration window n+2 (725). be sent, etc. In some cases, as in the example below 7 (both data stream signals 735, 740 having the same encoding, binary FF), data in subsequent time duration windows (e.g., n+1 (720) and n+2 (725)) may belong to the same protocol. In other cases, however, data in subsequent time duration windows (e.g., n+1 (720) and n+2 (725)) may originate from different transactions employing different protocols, and data stream signals (e.g., 735, 740) may be encoded accordingly to identify the different protocols that apply to the subsequent bytes of data on the data lanes (e.g., DATA[0-49]), to give an example.

In some implementations, a low power or sleep state may be defined for the MCPL. For example, when no device on the MCPL is transmitting data, the physical layer (electrical and logical) of the MCPL may enter an idle or low power state. In the example off 7 for example, at duration window n-2 (745), the MCPL is in an inactive or idle state and sampling is off to save power. The MCPL may emerge from a low power or sleep state and enable sampling at duration window n-1 (eg, 705). The scan may complete a transmit preamble (eg, to help wash up and synchronize the individual lanes of the channel as well as the sink device) carrying the scan signal before any other signal transmission on the other non-scan lanes. After this duration window n-1 (705), the valid signal can be asserted at duration window n (715) to notify the sink that data will be coming in the following duration window n+1 (720), as explained above.

The MCPL may transition back to a low power or idle state (e.g., an L1 state) after idle states are detected on the valid lanes, data lanes, and/or other lanes of the MCPL channel. For example, a signaling transmission beginning and continuing at duration window n+3 (730) can be detected. Logic on either the source or sink device can initiate going back to a low power state, which in turn (e.g. duration window n+5 (755)) causes the sampling to go into a power saving mode, for example and principles ( including those discussed later herein).

Electrical properties of the physical PHY can include one or more of unidirectional signaling, forwarded half-rate clocking, link channel tuning, as well as on-chip transport delay of transmitter (source) and receiver (sink), optimized electrostatic discharge (ESD) protection, pad capacitance, and others characteristics include. Additionally, an MCPL can be implemented to achieve higher data rates (e.g., close to 16 Gb/s) and better power efficiency characteristics than traditional packaged I/O solutions.

8th 8 shows a portion of a simplified block diagram 800 showing a portion of an example MCPL. The chart 800 off 8th includes an illustration of an example trajectory 805 (eg, a data trajectory, valid trajectory, or data stream trajectory) and clock generation logic 810. As in the example of FIG 8th As shown, in some implementations, clock generation logic 810 may be implemented as a clock tree to send a generated clock signal to each block that implements each lane in the example MCPL, such as data lane 805. Clock reset circuitry 815 may also be provided. In some implementations, a separate clock reset circuit is not provided for each lane in which the clock signal is provided, as conventionally in at least some traditional interconnect I/O architectures a single clock reset circuit may be provided for a bundle of multiple lanes. In fact, as in the exemplary configurations in 6 and 7 , a separate scan lane and accompanying clock reset circuitry are provided for each burst of twenty-five data lanes.

With the example out 8th furthermore, in some implementations, at least the data lanes, data stream lanes, and mid-lane valid lanes may be terminated to a regulated voltage above zero (ground). In some implementations, a mid-rail voltage can be regulated to Vcc/2. In some implementations, a single voltage regulator 825 may be provided per bundle of traces. When applied to the examples below 6 and 7 For example, a first voltage regulator may be provided for a first bundle of twenty-five data lanes and a second voltage regulator for the remaining bundle of twenty-five data lanes, to cite one of possible examples. In some examples, an example voltage regulator 825 may be implemented as a linear regulator, switched capacitor circuit, to name a few examples. In some implementations, the linear regulator can be provided with an analog feedback loop or a digital feedback loop, to name a few examples.

In some implementations, crosstalk suppression circuitry may also be provided for an example MCPL. In some cases, the compact nature of long MCPL wires can introduce crosstalk interference between traces. Crosstalk cancellation logic can be implemented to address these and other issues. For example, in an example given in 9-10 1, crosstalk can be significantly reduced with an exemplary low-power active circuit, such as illustrated in plots 900 and 1000. FIG. In the example off 9 For example, a weighted high-pass filtered "aggressor" signal can be added to the "victim" signal (ie the signal suffering from crosstalk interference from the aggressor). Any signal can be considered a victim of crosstalk by any other signal in the link and can itself be the aggressor of the other signal as long as it is the source of the crosstalk interference. Such a signal can be generated and reduce crosstalk on the victim lane by more than 50% thanks to the derivative nature of crosstalk on the link. The low-pass filtered aggressor signal in the example 9 can be generated by a high pass RC filter (e.g. implemented by C and R1) which produces the filtered signal which is added using a summing circuit 905 (e.g. RX sense amp).

Similar implementations as in the example below 9 can represent particularly practical solutions for an application such as MCLP, since an implementation of the circuit can be produced with relatively little additional space, as shown in the diagram 10 is shown, which is an example schematic at the transistor level of the example 9 shown and described circuit shows. It should be noted that the illustrations in 9 and 10 are simplified representations, and that an actual implementation is multiple copies of the in 9 and 10 circuits shown would include to accommodate the network of cross-talk interference under and between lanes of a link. As an example, in a three-lane connection (e.g. lanes 0-2) a circuit similar to that in the examples could be made out 9 and 10 be provided, from lane 0 to lane 1, from lane 0 to lane 2, from lane 1 to lane 0, from lane 1 to lane 2, from lane 2 to lane 0, from lane 2 to lane 1, etc., based on the Geometry and layout of the tracks, to name an example.

Other features may be implemented at the physical PHY level of an example MCPL. For example, receiver drift can introduce significant error and limit I/O voltage limits in some cases. Circuit redundancy can be used to improve receiver sensitivity. In some implementations, circuit redundancy can be optimized to address the standard deviation of data samplers used in the MCPL. For example, an example data sampler designed with a three (3) standard deviation specification may be provided. In the examples from 6 and 7 for example, if two (2) data samplers were used for each receiver (eg, for each lane), one hundred (100) samplers would be used for a fifty (50) lane MCPL. In this example, the probability that one of the receiver (RX) traces does not meet the three standard deviation specification is 24%. A chip reference voltage generator may be provided to set the deviation upper limit and proceed to the next data sampler at the receiver when another data sampler is determined to exceed the limit. However, if four (4) data samplers are used per receiver (ie, instead of two in this example), the receiver will fail only if three out of four samplers fail. For a fifty-lane MCPL, as in the examples below 6 and 7 , adding this additional circuit redundancy can significantly reduce the failure rate by 24% to less than 0.01%.

In other examples, at very high data rates, per bit duty cycle correction (DCC) and skew removal can be used to increase baseline per burst DCC and skew removal to improve link spacing. Instead of correcting in all cases, as in conventional solutions, in some implementations a low-power Digital implementation can be used that senses and corrects the outliers where the I/O trace would fail. For example, global lane matching can be performed to identify problem lanes within clusters. These problem lanes can then be targeted for per-lane tuning to achieve the high data rates supported by the MCPL.

Other features may also be optionally implemented in some instances of an MCPL to enhance physical link performance. For example, row encoding can be provided. While center lane terminations, as described above, may allow DC data bus inversion (DBI) to be skipped, AC-DBI can still be used to reduce dynamic power. More complicated coding can also be used to eliminate the worst-case mismatch of 1's and 0's, for example to reduce the drive requirement of a center lane regulator, as well as to limit I/O switching noise, to name a few beneficial examples. Furthermore, sender equalization can also be implemented if necessary. For example, at very high data rates, insertion loss in a channel within the package can be significant. Among other things, two-tap weight transmitter equalization (e.g., during an initial power-up sequence) may be sufficient in some cases to alleviate some of these problems.

On 11 Referring now to FIG. 1, a simplified block diagram 1100 showing an example logic PHY of an example MCPL is presented. A physical PHY 1105 can be connected to a die that includes logic PHY 1110 and other logic that supports a link layer of the MCPL. The die in this example may also include logic to support multiple different protocols on the MCPL. In the example off 11 For example, PCIe logic 1115 may be provided, as well as IDI logic 1120, so that the dies can communicate using either PCIe or IDI over the same MCPL connecting the two dies, to cite one of many possible examples, including examples where more than two protocols or protocols other than PCIe and IDI are supported on the MCPL. Different protocols supported between dies can provide different levels of service and functionality.

Logic PHY 1110 may include link state machine management logic 1125 for automatically adjusting link state transitions in conjunction with requests from higher-level logic of the die (e.g., received via PCIe or IDI). Logic PHY 1110 may further include connection test and debug logic (e.g., 1130) in some implementations. As noted above, an example MCPL may support control signals sent between dies over the MCPL to provide protocol independent high performance and power efficiency features (among other example features) of the MCPL. For example, logic PHY 1110 may support generation and transmission, and reception and processing of valid signals, data stream signals, and LSM sideband signals in conjunction with the transmission and reception of data over dedicated data lanes, as described in the examples above.

In some implementations, multiplexing (e.g., 1135) and demultiplexing (e.g., 1140) logic may be included in or otherwise accessible to logic PHY 1110. For example, multiplexing logic (e.g., 1135) may be used to identify data (e.g., embodied as packets, messages, etc.) on which to send MCPLs. The multiplexing logic 1135 can identify the protocol that manages the data and generate a data stream signal that is encoded to identify the protocol. For example, in an example implementation, the data stream signal may be encoded as a byte of two hexadecimal symbols (e.g., IDI: FFh; PCIe: F0h; LLP: AAh; Sideband: 55h; etc.) and may occur during the same window (e.g., a byte-time window) of the data are sent managed by the identified protocol. Similarly, demultiplexing logic 1140 may be employed to interpret incoming data stream signals to decode the data stream signal and identify the protocol to be applied to data received on the data lanes concurrently with the data stream signal. The demultiplexing logic 1140 can then apply (or ensure) protocol-specific link layer handling and cause the data to be handled by the appropriate protocol logic (e.g., PCIe logic 1115 or IDI logic 1120).

Logic PHY 1110 may further include link-layer packet logic 1150, which may be used to handle various link control functions, including power management tasks, looping, deactivation, re-centering, scrambling, etc. LLP logic 1150 may, among other functions, transmit link-layer-to-link-layer messages over Enable MCLP. Data corresponding to LLP signaling can also be identified by a data stream signal sent on a dedicated data stream signal path and encoded to identify the data path LLP data. Multiplexing and demultiplexing logic (e.g. 1135, 1140) may also be used to generate and interpret the data stream signals corresponding to LLP traffic and to cause such traffic to be routed by the corresponding bare chip logic (e.g. LLP logic 1150) is processed. Similarly, in some implementations, an MCLP may include a dedicated sideband (eg, sideband 1155 and supporting logic), eg, an asynchronous and/or low-frequency sideband channel, to cite an example.

Logical PHY logic 1110 may further include link state machine management logic that may generate (and use) link state management messaging over a dedicated LSM sideband lane. For example, an LSM sideband trace can be used to perform tuning and speed up the link training state, exiting power management states (e.g., an L1 state), to name a few possible examples. The LSM sideband signal may be an asynchronous signal in the sense that it is not aligned with the link's data, valid, and stream signals, but instead corresponds to signaling state transitions and aligns the link state machine between two dies or chips connected by the link , to give an example. Providing a dedicated LSM sideband trace can in some cases allow transient squelch and received detection circuits of an analog front end (AFE) to be eliminated, to cite a few beneficial examples.

On 12 Referring now to FIG. 1, a simplified block diagram 1200 is shown showing another representation of logic used to implement an MCPL. For example, logical PHY 1110 is provided with a defined logical PHY interface (LPIF) 1205 through which any of a variety of different protocols (e.g., PCIe, IDI, QPI, etc.) 1210, 1215, 1220, 1225 and signaling modes ( eg sideband) can interface with the physical layer of an exemplary MCPL. Multiplexing and arbitration logic 1230 may also be provided as a separate layer from logic PHY 1110 in some implementations. In one example, LPIF 1205 may be provided as an interface on either side of this MuxArb 1230 layer. The logic PHY 1110 may interface with the physical PHY (eg, the analog front end (AFE) 1105 of the MCPL PHY) through another interface.

The LPIF can abstract the PHY (logical and electrical/analog) from the upper layers (eg 1210, 1215, 1220, 1225) so that a completely different PHY can be implemented under LPIF, transparent to the upper layers. This can help encourage modularity and reuse in design, as the upper layers can remain intact when underlying signaling technology PHY is updated, for example. Further, the LPIF may define a set of signals that enable multiplexing/demultiplexing, LSM management, error detection and recovery, and other logic PHY functionalities. For example, Table 1 summarizes at least some of the signals that can be defined for an example LPIF: TABLE 1: signal name Description Rst provision lclk Link Clock - 8UI of PHY link clock Pl_trdy The physical layer is ready to accept data, data is accepted from the physical layer when Pl_trdy and Lp_valid are both asserted. Pl_data[N-1:0][7:0] Physical layer-to-link layer data, where N equals the number of lanes. Pl_valid Physical layer-to-link layer signal indicating data validity Pl_Stream[7:0] Physical layer-to-link layer signal indicating the data stream ID received with the data Pl_error Physical layer encountered an error (e.g. frame synchronization or training) Pl_AlignReq Physical layer asks link layer to match packets with LPIF width limit Pl_in_L0 Indicates that the link state machine (LSM) is in L0 Pl_in_retrain Indicates that LSM is in retrain Pl_rejectL1 Indicates that the PHY layer rejected entry into L1 Pl_in_L12 Indicates that LSM is in L1 or L2 Pl_LSM (3:0) Current LSM status information lp_data[N-1:0][7:0] Link layer to physical layer data, where N equals the number of lanes lp_Stream[7:0] Link layer to physical layer signal indicating data stream ID to be used with data Lp_AlignAck Link layer-to-physical layer indicates that the packets are matched to the LPIF width limit lp_valid Link layer to physical layer signal indicating data validity Lp_enterL 1 Link layer request to physical layer to enter L1 lp_enterL2 Link layer request to physical layer to enter L2 Lp_Retrain Link layer request to physical layer to retrain the PHY Lp_exitL 12 Link layer request to physical layer to exit L1, L2 lp_disable Link layer request to physical layer to disable PHY

As seen in Table 1, in some implementations an alignment mechanism can be provided by an AlignReq/AlignAck handshake. For example, when the physical layer goes into reset, some protocols may lose packet frame synchronization. Matching of the packets can be corrected, for example to ensure correct frame synchronization identification by the link layer. In addition, as in 13 As shown, the physical layer asserts a StallReq signal when it enters reset, so the link layer asserts a stall signal when a new matched packet is ready for transmission. The physical layer logic can sample both Stall and Valid to determine if the packet is matched. For example, the physical layer may continue to drive trdy to derive the link layer packets until Stall and Valid are sampled as committed, to name one of possible implementations, including other alternative implementations using Valid to aid in packet matching.

Various error tolerances can be defined for signals on the MCPL. For example, error tolerances can be defined for valid, stream, LSM sideband, low frequency wideband, link layer packet, and other types of signals. Fault tolerance for packets, messages, and other data sent over the MCPL's dedicated data lanes may be based on the particular protocol managing the data. In some implementations, error detection and recovery mechanisms may be provided, such as cyclic redundancy check (CRC), retry buffers, to name a few possible examples. As examples, 32-bit CRC can be used for PCIe transaction layer packets (TLPs) for PCIe packets sent over the MCPL (with guaranteed delivery (e.g. through a replay mechanism)) and 16-bit CRC can be used for PCIe Link layer packets are used (whose architecture is lossy (e.g. where no playback is employed)). Furthermore, for PCIe frame synchronization tokens, a specific hamming distance (e.g., hamming distance four (4)) can be defined for the token identifier; Parity and 4-bit CRC can also be used, to give an example. On the other hand, IDI packets can use 16-bit CRC.

In some implementations, fault tolerances may be defined for link layer packets (LLPs) that include requesting a valid signal to transition from low to high (ie, 0 to 1). (eg to support bit and symbol locking). Further, in one example, a specified number of consecutive, identical LLPs can be defined to be sent, and responses to each request can be expected, with retries by the requestor after the response time has expired, including other defined properties that serve as a basis for Determination of errors in LLP data on the MCPL can be used. In other examples, error tolerance may be provided for a valid signal, for example, by extending the valid signal across an entire time duration window or symbol (eg, by holding the valid signal high for more than eight UIs). Furthermore, errors or glitches in data stream signals can be prevented by maintaining a Hamming distance for encoding values of the data stream signal, for example.

Logic PHY implementations may include error determination, error reporting, and error recovery logic. In some implementations, logic PHY of an example MCPL may include logic to determine PHY layer frame synchronization failures (e.g., on the valid and data flow path), sideband failures (e.g., related to LSM state transitions), failures in LLPs (e.g., those critical to LSM state transitions are) to name a few examples. Some error determination/resolution may be delegated to higher layer logic, such as PCIe logic that is adapted to determine PCIe specific errors, for example.

In the case of frame synchronization debugging errors, one or more mechanisms that can be provided by debugging logic may be provided in some implementations. Frame synchronization elimination errors can be eliminated based on the protocols involved. For example, in some implementations, link layers may be informed of the failure to trigger a retry. Frame sync elimination may also trigger a logic PHY frame sync elimination realignment. Furthermore, logic PHY re-centering can be performed and symbol/window locking can be re-acquired, among other techniques. Centering may, in some examples, involve the PHY moving the receiver clock phase to the sweet spot to determine the incoming data. "Optimal" in this context can mean where it has the greatest room for noise and clock jitter. Re-centering may include simplified centering functions performed when the PHY wakes up from a low power state, for example.

Other types of errors may involve other error recovery techniques. For example, errors detected in a sideband can be trapped by a timeout mechanism of an appropriate state (e.g. an LSM). The error can be logged and the connection state machine can then transition to reset. The LSM can remain in default until a restart command is received from software. In another example, LLP errors, such as a link control packet error, can be handled with a timeout mechanism that can restart the LLP sequence if no acknowledgment of the LLP sequence is received.

14A-14C Figure 12 shows representations of example bit maps on data lanes of an example MCPL for various types of data. An example MCPL may include fifty data lanes. 14A FIG. 12 shows a first bit-mapping of example 16-byte slots in a first protocol, such as IDI, that can be sent over data lanes within an 8UI symbol or window. For example, three 16-byte slots, including a header slot, can be sent within the defined 8UI window. Two bytes of data remain in this example, and the remaining two bytes can be used as CRC bits (eg, in lanes DATA[48] and DATA[49]).

In another example shows 14B Figure 12 shows a second example bit-mapping for PCIe packet data sent over the fifty data lanes of an example MCPL. In the example off 14B 16-byte packets (e.g. transaction layer (TLP) or data link layer (DLLP) PCIe packets) can be sent over the MCPL. Three packets can be sent in an 8UI window, leaving the remaining two bytes of bandwidth in the window unused. Frame synchronization tokens can be included in these symbols and used to determine the start and end of each packet. In an example of PCIe, the frame synchronization shown in the example 14B be the same as the tokens implemented for PCIe at 8 GT/s.

In another example found in 14C 1, an example bit-map of connection-to-connection packets (eg, LLP packets) sent over an example MCPL is shown. LLPs can be 4 bytes each, and each LLP (eg, LLP0, LLP1, LLP2, etc.) can be four sent consecutive times consistent with fault tolerance and fault determination within an example implementation. For example, a failure to receive four consecutive identical LLPs may indicate an error. Additionally, with other data types, a failure to receive a VALID in a processing time slot or symbol may also indicate an error. In some cases, LLPs may have fixed slots. Also in this example, unused, or "spare," bits in the byte time period may result in logical 0s being transmitted across two of the fifty lanes (eg, DATA[48-49]), for example.

On 15 Referring to this, a simplified connection state machine transition diagram 1400 is shown along with sideband handshaking used between the state transitions. For example, a Reset.Idle state (eg, when performing a phase lock loop (PLL) lock calibration) may transition to a Reset.Cal state (eg, where the link is further calibrated) through a sideband handshake. Reset.Cal can transition to a Reset.ClockDCC state (where eg duty cycle correction (DCC) and delay locked loop (DLL) locking is performed) through a sideband handshake. An additional handshake can be performed to transition from a Reset.ClockDCC to a Reset.Quiet state (eg, to deassert the Valid signal). To help align signal transmission on the lanes of the MCPL, the lanes can be centered by a Center.Pattern state.

In some implementations, as shown in the example 16 shown, during the Center.Pattern state the transmitters generate training patterns or other data. The receiver can condition its receiver circuitry to receive such training patterns, for example by adjusting the phase interpolator position and vref position and adjusting the comparator. The receiver can continuously compare the patterns received with expected patterns and store the result in a register. After a set of patterns is complete, the receiver can increase the phase interpolator setting and leave vref the same. The test pattern generation and comparison process can continue and new comparison results can be stored in the register, the process repeatedly cycling through all phase interpolator values and all vref values. The Center.Quiet state can be entered when the pattern generation and comparison process are complete. After centering the lanes through the Center.Pattern and Center.Quiet link states, a sideband handshake (e.g., using an LSM sideband signal on the link's dedicated LSM sideband lane) can be enabled to enter a Link.Init state to initialize the MCPL and allow data to be sent on the MCPL.

Briefly on the explanation of 15 Coming back, as noted above, a sideband handshake can be used to facilitate interconnect state machine transitions between dies or chips in a multichip package. For example, signals on the LSM sideband lanes of an MCPL can be used to synchronize the state machine transitions on the die. For example, if the conditions for exiting its state are met (e.g. Reset.Idle), the side that met those conditions can assert an LSM sideband signal on its outbound LSM_SB lane and wait for the other, separate die until this achieves the same condition and assures an LSM sideband signal on its LSM_SB path. If both LSM_SB signals are asserted, each die's connection state machine may transition to the next state (eg, a Reset.Cal state). A minimum overlap time can be defined during which both LSM_SB signals should remain asserted before the transition state occurs. Furthermore, a minimum sleep time can be defined after LSM_SB is de-asserted to allow accurate reversal detection. In some implementations, each connection state machine transition may be conditioned on/by such LSM_SB handshakes and simplified.

17 17 is a detailed link state machine diagram 1700 showing at least some of the additional link states and link state transitions that may be included in an example MCPL. In some implementations, in an example connection state machine, among the others, in 17 In addition to the illustrated states and state transitions, a "guided looping" transition may also be provided to place the lanes of an MCPL in digital looping. For example, the receiver lanes of an MCPL can be routed back to the transmitter lanes after the clock reset circuits. A "LB_Recenter" state can also be provided in some cases, which can be used to match the data symbols. In addition, as in 15 shown that support MCPL multiple link states finally, an active L0 state and a low-power state, such as an L1 idle state and L2 sleep state, to name a few possible examples.

18 18 is a simplified block diagram 1800 showing an example flow in a transition between an active state (eg, L0) and a low power, or idle, state (eg, L1). In this particular example, a first device 1805 and a second device 1810 are communicatively coupled using an MCPL. In the active state, data is transmitted via the lanes of the MCPL (e.g. DATA, VALID, STREAM, etc.). Link layer packets (LLPs) may be communicated over the lanes (eg, data lanes, with the data stream signal indicating the data is LLP data) to help facilitate link state transitions. For example, LLPs can be sent between the first and second devices 1805, 1810 to transition from L0 to L1 automatically. For example, upper-layer protocols supported by the MCPL are desired to communicate this entry into L1 (or some other state), and the upper-layer protocols may result in LLPs being sent over the MCPL to facilitate a link-layer handshake in order to do so the physical layer enters L1. 18 FIG. 14, for example, shows at least a portion of LLPs sent from the second (upstream) device 1810 to the first (downstream) device 1805, including an “enter L1” request LLP. In some upper level implementations and protocols, the downstream port does not initiate entry into L1. The receiving first device 1805 may send in response a change-to-L1 request LLP, which the second device 1810 may acknowledge by a change-to-L1 acknowledgment (ACK) LLP to enter a to name an example. Upon detecting completion of the handshake, the logic PHY may cause a sideband signal to be asserted on a dedicated sideband link to confirm that the ACK has been received and that the device (e.g., 1805) is ready to enter L1 and expected this. For example, the first device 1805 may assert a sideband signal 1815 that is sent to the second device 1810 to acknowledge receipt of the final ACK in the link-layer handshake. In addition, the second device 1810 may also assert a sideband signal in response to the sideband signal 1815 to notify the first device 1805 of the sideband ACK 1805 of the first device. When the link layer control and sideband handshake are complete, the MCPL PHY can be transitioned to the L1 state, resulting in all lanes of the MCPL being placed in a sleep power saving mode, including corresponding MCPL scans of 1820, 1825 of devices 1805, 1810. L1 may be exited when upper-layer logic requests one of the first and second devices 1805, 1810 to re-enter L0, for example in response to detecting data being sent over the MCPL to the other device should.

As noted above, in some implementations, an MCPL may facilitate communication between two devices that may support multiple different protocols, and the MCPL may facilitate communications according to possibly one of multiple protocols over the lanes of the MCPL. However, allowing multiple protocols may make entering and re-entering at least some connection states more difficult. For example, while some traditional connections have a single upper layer protocol that is the master of the state transitions, an implementation of MCPL with multiple different protocols effectively includes multiple masters. As in 18 by way of example, each of PCIe and IDI between two devices 1805, 1810 can be supported by an implementation of MCPL, e.g. setting the physical layer to an idle or low power state can depend on the condition that permission is first obtained from each of the supported protocols (e.g. both PCIe and IDI).

In some cases, entry into L1 (or other state) can only be requested by one of the several supported protocols supported for implementation of an MCPL. While it may be likely that the other protocols will also request entry into the same state (eg, based on an identification of similar conditions (eg, little or no traffic) on the MCPL), the logic PHY can wait for permission or instructions have been received from any upper layer protocol before the state transition is actually enabled. The logic PHY can track which upper-layer protocols requested the state change (e.g., performed a corresponding handshake) and trigger the state transition when identifying that each of the protocols requested the respective state change, such as an L0 to L1 transition or a other transition that would affect or disrupt the communications of the other protocols. In some implementations, protocols may be blind to their at least partial dependency on other protocols in the system. Further, in some cases, a protocol may expect a response (eg, from the PHY) to a request to transition to a particular state, e.g wise an acknowledgment or rejection of the requested state transition. Accordingly, in such cases, while waiting for permission from another supported protocol to enter an idle connection state, the logic PHY can generate synthetic responses to a request to enter the idle state and "trick" the requesting upper-layer protocol to do so assumes that it has entered a certain state (while in fact the lanes are still active, at least until the other protocols also request entry into the idle state). Among other potential benefits, this may simplify entry into the low power state between multiple protocols through coordination, for example.

It should be noted that the devices, methods, and systems described above may be implemented in any electrical device or system as mentioned above. As specific illustrations, the following figures provide example systems for using the invention as described herein. When the systems are described in more detail below, a number of different connections are disclosed, described, and resumed from the discussion above. And as will be readily apparent, the advantages described above can be applied to any of these connections, structures or architectures.

With reference to 19 Illustrated is one embodiment of a block diagram for a computing system that includes a multi-core processor. Processor 1900 includes a processor or processing device, such as a microprocessor, an embedded processor, a digital signal processor (DSP), a network processor, a handheld processor, an application processor, a coprocessor, a system on chip (SOC), or other device for execution of a code. Processor 1900, in one embodiment, includes at least two cores - cores 1901 and 1902, which may include asymmetric cores or symmetric cores (the illustrated embodiment). However, processor 1900 may also include a number of processing elements, which may be symmetric or asymmetric.

In one embodiment, a processing element refers to hardware or logic supporting a software thread. Examples of hardware processing elements include: a thread unit, a thread slot, a thread, a process unit, a context, a context unit, a logical processor, a hardware thread, a core, and/or any other element capable of is to hold a state of a processor, e.g., an execution state or an architectural state. In other words, a processing element in one embodiment can refer to any hardware that can be independently associated with code, such as a software thread, an operating system, an application, or other code. A physical processor (or processor socket) commonly refers to an integrated circuit that may include any number of other processing elements, such as cores or hardware threads.

A core often refers to logic residing on an integrated circuit capable of maintaining an independent architectural state, with each independently maintained architectural state being associated with at least some dedicated execution resources. In contrast to cores, a hardware thread commonly refers to any logic residing on an integrated circuit capable of maintaining an independent architectural state, where the independently maintained architectural states have common access to execution resources. As can be seen, when certain resources are shared and others are reserved for an architectural state, the boundary between the terminology for a hardware thread and for a core overlaps. Often, however, a core and a hardware thread are viewed by an operating system as individual logical processors, with the operating system being able to schedule operations on each logical processor separately.

Physical processor 1900, as in 19 shown comprises two cores - core 1901 and 1902. Here core 1901 and 1902 are seen as symmetric cores, ie cores with the same configurations, functional units and/or logic. In another embodiment, core 1901 includes an out-of-order processor core, while core 1902 includes an in-order processor core. However, cores 1901 and 1902 may be independently selected from any type of core, such as a native core, a software managed core, a core adapted to execute a native instruction set architecture (ISA), a core adapted to execute a Translated Instruction Set Architecture (ISA), a commonly designed kernel, or another known kernel. In a heterogeneous core environment (ie, asymmetric cores), some form of translation, such as binary translation, can be used to translate code on one or both cores to plan or carry out. For the sake of brevity, the functional units represented in core 1901 are described in more detail below, since the units in core 1902 operate in a similar manner in the illustrated embodiment.

As shown, core 1901 includes two hardware threads 1901a and 1901b, which may also be referred to as hardware thread slots 1901a and 1901b. Therefore, in one embodiment, software entities such as an operating system may view processor 1900 as four separate processors, i.e., four logical processors or processing elements capable of executing four software threads concurrently. As noted above, a first thread is associated with architecture state registers 1901a, a second thread is associated with architecture state registers 1901b, a third thread may be associated with architecture state registers 1902a, and a fourth thread may be associated with architecture state registers 1902b. Here, each of the architecture state registers (1901a, 1901b, 1902a, and 1902b) may be referred to as a processing element, thread slot, or thread unit, as described above. As shown, architecture state registers 1901a are replicated in architecture state registers 1901b so that individual architecture states/contexts can be stored in for logical processor 1901a and logical processor 1901b. Other small resources such as instruction pointers and renaming logic in allocator and renamer block 1930 for threads 1901a and 1901b may also be replicated in core 1901. Some resources, such as reorder buffers in reorder/retire unit 1935, ILTB 1920, load/store buffers, and queues may be shared through partitioning. Other resources such as internal general purpose registers, (a) page table based register(s), low level data caches and data TLB 1915, (a) execution unit(s) 1940 and parts of out of order unit 1935 possibly fully shared.

Processor 1900 often includes other resources that can be fully shared, shared through partitioning, or dedicated by/to processing elements. In 19 1 is an embodiment of a purely exemplary processor with illustrative logical units/resources of a processor. It is noted that a processor may or may not include any of these functional units, as well as any other known functional units, logic, or firmware that are not shown. As illustrated, core 1901 comprises a simplified out of order (OOO) processor core. But in other embodiments, an in-order processor may be used. The OOO core includes a branch target buffer 1920 to predict branches that will be taken/taken and an instruction translation buffer (I-TLB) 1920 to store address translation entries for instructions.

Core 1901 further includes a decode module 1925 coupled to fetch unit 1920 to decode fetched items. In one embodiment, fetch logic includes individual sequencers associated with thread slots 1901a and 1901b, respectively. Typically, core 1901 is associated with a first ISA that defines/specifies instructions executable on processor 1900. Often, machine code instructions that are part of the first ISA include a portion of the instruction (referred to as opcode) that references/specifies an instruction or operation to be performed. Decode logic 1925 includes circuitry that recognizes these instructions from their opcodes and passes the decoded instructions down the pipeline for processing as defined by the first ISA. For example, as discussed in more detail below, in one embodiment, decoders 1925 may include logic designed or adapted to recognize specific instructions, such as a transaction instruction. As a result of detection by decoders 1925, the architecture or core 1901 takes certain predefined actions to perform tasks associated with the appropriate instruction. It is important to note that any of the tasks, blocks, operations, and methods described herein may be performed in response to a single or multiple instructions; some of these may be new or old instructions. Note that in one embodiment, decoders 1926 recognize the same ISA (or a subset thereof). Alternatively, in a heterogeneous core environment, decoders 1926 recognize a second ISA (either a subset of a first ISA or a different ISA).

In one example, the allocator and renamer block 1930 includes an allocator for reserving resources, such as register files for storing instruction processing results. However, threads 1901a and 1901b may be capable of out-of-order execution, with allocator and renamer block 1930 also reserving other resources, such as reorder buffers for tracking instruction results. Unit 1930 may also include a register renamer for renaming program/instruction reference registers to other internal registers star of 1900 processor. Reorder/retirement unit 1935 includes components such as the reorder buffers, load buffers, and store buffers noted above to support out-of-order execution and later and in-order retirement of out-of-order instructions.

Scheduler and Execution Unit(s) Block 1940, in one embodiment, includes a scheduler unit for scheduling instructions/operations onto execution units. For example, a floating point instruction is scheduled on an execution unit port that has an available floating point execution unit. Register files associated with execution units are also included to store information about instruction processing results. Example execution units include a floating point execution unit, an integer execution unit, a branch execution unit, a load execution unit, a memory execution unit, and other known execution units.

A low level data cache and a data translation buffer (D-TLB) 1950 are coupled to execution unit(s) 1940 . The data cache is used to store recently used/edited items, such as data operands, that may be held in memory coherency states. The D-TLB is used to store recent virtual/linear-to-physical address translations. As a specific example, a processor may include a page table structure to break up physical memory into a plurality of virtual pages.

Here, cores 1901 and 1902 share access to a higher-level or more external cache, such as a second-level cache associated with an on-chip interface 1910. Note that higher level or further out refers to cache levels that are ascending or further away from the execution unit(s). In one embodiment, a higher level cache is a last level data cache - the last cache in the memory hierarchy on processor 1900 - such as a second or third level cache. However, a higher level cache is not so limited, as it may be associated with or include an instruction cache. A trace cache - a type of instruction cache - may instead be coupled after the decoder 1925 to store recently decoded runs. Here, an instruction may refer to a macro-instruction (i.e., a general instruction recognized by the decoders) that can be decoded into a series of micro-instructions (micro-operations).

In the configuration shown, processor 1900 also includes an on-chip interface module 1910. Historically, a memory controller, described in more detail below, was included in a computing system external to processor 1900. In this scenario, the on-chip interface 1910 is used to communicate with devices external to the processor 1900, e.g., a system memory 1975, a chipset (often including a memory controller hub, around memory 1975, and an I/O controller hub to connect to peripheral devices), a memory controller hub, a northbridge, or other integrated circuits. And in this scenario, bus 1905 can include any known connection, such as a multipoint bus, a point-to-point connection, a serial connection, a parallel bus, a coherent (e.g., cache-coherent) bus, a protocol layer architecture, a differential bus, and a GTL bus.

Memory 1975 may be dedicated to processor 1900 or shared with other devices in a system. Common examples of types of memory 1975 include DRAM, SRAM, non-volatile memory (NV memory), and other known memory devices. Note that device 1980 is a graphics accelerator, a processor or card coupled to a memory controller hub, a memory coupled to an I/O controller hub, a wireless transceiver, a flash device, an audio controller, a network controller, or other known device may include.

More recently, however, as more logic and devices are packaged on a single die, such as an SOC, each of these devices may be incorporated on processor 1900. For example, in one embodiment, a memory controller hub resides on the same package and/or die as processor 1900. Here, a portion of core (an on-core portion) 1910 includes one or more controllers for providing an interface with other devices , such as memory 1975 or a graphics device 1980. The configuration that includes connection and controls for interfacing with such devices is often referred to as on-core (or un-core configuration). For example, an on-chip interface 1910 includes a ring connection for on-chip communications tion and a point-to-point high-speed serial link 1905 for off-chip communications. Nonetheless, in the SOC environment, other devices such as the network interface, coprocessors, memory 1975, graphics processor 1980 and any other known computing devices/interfaces can reside on a single die or integrated circuit to provide a small form factor with high functionality and provide low energy consumption.

In one embodiment, processor 1900 is capable of executing compilation, optimization, and/or translator code 1977 to compile, translate, and/or optimize application code 1976 to support the apparatus and methods described herein or a to provide an interface with it. A compiler often includes a program or set of programs for translating source test/code into target text/code. Typically, program/application code is compiled with a compiler in multiple stages and passes to convert higher level programming language code to lower level machine or assembly language code. However, single-pass compilers can also be used for simple compilation. A compiler can use any known compilation techniques and perform any known compiler operations, such as lexical analysis, preprocessing, parsing, semantic analysis, code generation, code transformation, and code optimization.

Larger compilers often include multiple phases, but most often these phases are contained within two general phases: (1) a front-end, i.e. where generally syntactic processing, semantic processing, and some transformation/optimization can take place, and (2) a back-end , i.e. where analysis, transformation, optimization and code generation generally take place. Some compilers refer to a middle, reflecting the blurring of boundaries between a compiler's front end and back end. As a result, a reference to an insertion, allocation, generation, or other operation of a compiler may occur in any of the foregoing phases or passes, as well as any other known phases or passes of a compiler. As an illustrative example, a compiler may insert operations, calls, functions, etc. at one or more compilation phases, such as inserting calls/operations at a front-end phase of compilation and then transforming the calls/operations to lower-level code during a transformation phase. It should be noted that during dynamic compilation, compiler code or dynamic optimization code may insert such operations/calls, as well as optimize the code for execution at runtime. As a specific illustrative example, binary code (already compiled code) may be dynamically optimized at runtime. Here, the program code may include dynamic optimization code, binary code, or a combination thereof.

Similar to a compiler, a translator, such as a binary translator, translates code either statically or dynamically to optimize and/or translate the code. Therefore, a reference to execution of code, application code, program code, or other software environment may refer to: (1) execution of one or more compiler programs, optimizing code optimizer, or translator, either dynamically or statically, to create program code compile, obtain software structures to perform other operations, optimize code, or translate code; (2) to execution of main program code, including operations/calls, such as application code that has been optimized/compiled; (3) to an embodiment of other program code, such as libraries associated with the main program code, to maintain software structures, to perform other software-related operations, or to optimize code; or (4) a combination thereof.

On 20 Referring now, a block diagram of one embodiment of a multi-core processor is shown. As in the embodiment of 20 As can be seen, processor 2000 includes multiple domains. More specifically, a core domain 2030 includes a plurality of cores 2030A-2030N, a graphics domain 2060 includes one or more graphics engines with a media engine 2065 and a system agent domain 2010.

In various embodiments, system agent domain 2010 handles power control operations and power management such that individual units of domains 2030 and 2060 (e.g., cores and/or graphics engines) are independently controllable to dynamically operate an appropriate power mode/level (e.g., active, turbo, sleep, hibernation, hibernation, or other similar states as in advanced power interface configurations) with respect to the activity (or inactivity) in the respective unit. Each of the domains 2030 and 2060 can have a different voltage and/or power, and also the individual units within the domains may each be able to run at independent frequency and voltage. It should be noted that while only three domains are shown, the scope of the present invention is not limited to the context of die and other domains may be present in other embodiments.

As shown, each core 2030 also includes low-level caches in addition to various execution units and other processing elements. Here, the various cores are coupled to each other and to a shared cache made up of a plurality of units or slices of at least one last level cache (LLC) 2040A-2040N; these LLCs often include memory and cache control functionality and are shared between the cores and possibly the graphics engines as well.

As can be seen, a ring interconnect 2050 couples the cores together and provides a connection between the core domain 2030, the graphics domain 2060 and the system agent circuitry 2010 via a plurality of ring stops 2052A-2052N, each at a coupling between a core and an LLC slice . As in 20 As seen, link 2050 is used to carry various information, including address information, date information, acknowledgment information, and intercept/invalid information. Although a ring connection is shown, any known die-borne connection or structure may be employed. As an illustrative example, some of the structures discussed above (e.g., another die-borne interconnect, system on-chip fabric (OSF), an advanced microcontroller bus architecture (AMBA) interconnect, a multi-dimensional mesh fabric, or other known interconnect architecture) may be employed in a similar manner .

As further illustrated, system agent domain 2010 includes a display engine 2012 operable to provide control of and interface with an associated display. System agent domain 2010 may include other entities such as: an integrated memory controller 2020 that interfaces with system memory (e.g., DRAM implemented with multiple DIMMs); a coherency logic 2022 for performing memory coherency operations. Multiple interfaces may be present to provide a connection between the processor of another circuit. For example, in one embodiment, at least one direct media interface (DMI) 2016 is provided, as well as one or more PCIe™ interfaces 2014. The display engine and these interfaces are typically coupled to memory via a PCIe™ bridge 2018. Furthermore, one or more other interfaces may be provided to provide communication between other agents, such as additional processors or other circuitry.

On 21 Referring now, a block diagram of a representative core is presented; more specifically, logical blocks of a back-end of a core, such as core 2030 20 . In general, the in 21 The structure shown depicts an out-of-order processor that includes a front-end unit 2170 configured to fetch incoming instructions, perform various processing (eg, caching, decoding, branch prediction, etc.), and forward instructions/operations to out-of-order processors compliant (OOO) machine 2180 is used. OOO engine 2180 performs further processing on decoded instructions.

More specifically, in the embodiment includes 21 the out-of-order engine 2180 has a mapping unit 2182 for receiving decoded instructions, which may be in the form of one or more micro-instructions or uops, from the front-end unit 2170 and mapping them to appropriate resources, such as registers, etc. Next the instructions are routed to a reservation station 2184, which dedicates resources and schedules them for execution on one of a plurality of execution units 2186A-2186N. Various types of execution units may exist, such as arithmetic logic units (ALUs), load and store units, vector processing units (VPUs), floating point execution units, and others. Results from these various execution units are provided to a reorder buffer (ROB) 2188, which takes unordered results and restores the correct program ordering.

Still referring to 21 it should be noted that both the front-end unit 2170 and the out-of-order engine 2180 are coupled to different levels of a memory hierarchy. Specifically shown is an instruction level cache 2172 which in turn is coupled to a middle level cache 2176 which in turn is coupled to a top level cache 2195 . In one embodiment, the last level cache 2195 is implemented in an on-chip (sometimes referred to as an uncore) device 2190 . For example, Unit 2190 is similar to System agent 2010 off 20 . As explained above, uncore 2190 communicates with system memory 2199, which in the illustrated embodiment is implemented using ED-RAM. It should also be noted that the various execution units 2186 within the out-of-order engine 2180 are in communication with a first-level cache 2174 that is also in communication with a mid-level cache 2176 . It should also be noted that other cores 2130N-2 - 2130N may be coupled to LLC 2195 . Although in the embodiment off 21 Illustrated at this high level, it is understood that various modifications and additional components may be present.

On 22 Referring to FIG. 1, a block diagram of an exemplary computing system formed with a processor including execution units for executing an instruction, one or more of the interconnects having one or more features in accordance with an embodiment of the present invention is shown. System 2200 includes a component, such as a processor 2202, for applying execution units including logic to perform algorithms on process data in accordance with the present invention, such as in the embodiment described herein. System 2200 is illustrative of processing systems based on PENTIUM III™, PENTIUM 4™, Xeon™, Itanium, XScale™ and/or StrongARM™ microprocessors, although other systems may be used (including personal computers with other microprocessors, development workstations, consoles and the like) . In one embodiment, a sample device 2200 runs a version of the WINDOWS™ operating system available from Microsoft Corporation of Redmond, Washington, USA, although other operating systems (such as UNIX and Linux), embedded software, and/or graphical user interfaces may be used . Thus, embodiments of the present invention are not limited to any particular combination of hardware circuitry and software.

Embodiments are not limited to computing systems. Alternative embodiments of the present invention may be used in other devices, such as handheld devices and embedded applications. Some examples of handheld devices include cell phones, internet protocol devices, digital cameras, personal digital assistants (PDAs), and handheld PCs. Embedded applications may be a microcontroller, digital signal processor (DSP), system on chip, network computer (NetPC), set-top box, network hub, wide area network (WAN) switch, or any other system that implements one or more instructions according to at least one embodiment can perform include.

In this illustrated embodiment, the processor 2202 includes one or more execution units 2208 for implementing an algorithm to execute at least one instruction. An embodiment may be described in the context of a single processor desktop or server system, but alternative embodiments may be included in a multi-processor system. System 2200 is an example of a "hub" system architecture. The computing system 2200 includes a processor 2202 for processing data signals. Processor 2202 may, in one illustrative example, include a complex instruction set computer (CISC) microprocessor, a reduced instruction set computer (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, a processor that implements a combination of instruction sets , or any other processor device such as a digital signal processor. The processor 2202 is coupled to a processor bus 2210 that transfers data signals between the processor 2202 and other components in the system 2200. The elements of system 2200 (e.g., graphics accelerator 2212, memory controller hub 2216, memory 2220, I/O controller hub 2224, wireless transceiver 2226, flash BIOS 2228, network controller 2234, audio controller 2236, serial expansion port 2238, I /O controller 2240, etc.) perform their conventional functions well known to those skilled in the art.

In one embodiment, the processor 2202 includes an internal level 1 (L1) cache 2204. Depending on the architecture, the processor 2202 may have a single internal cache or multiple levels of internal caches. Other embodiments include a combination of both internal and external caches, depending on the particular implementation and requirements. Register file 2206 is used to store different types of data in various registers, including integer registers, floating point registers, vector registers, bank registers, shadow registers, checkpoint registers, status registers, and instruction pointer registers.

Execution unit 2208, including logic for performing integer and floating point operations, also resides within processor 2202. Processor 2202, in one embodiment, includes microcode (ucode) ROM for storing microcode that, when executed, is used to execute algorithms for execute specific macro instructions or handle complex scenarios. Microcode here may be updatable to handle processor 2202 logic bugs/fixes. In one embodiment, execution unit 2208 includes logic for handling a packed instruction set 2209. By including the packed instruction set 2209 in the instruction set of a general purpose processor 2202, along with associated circuitry for executing the instructions, the operations used by many multimedia applications can be performed using packed data in executed on a 2202 general purpose processor. Thus, many multimedia applications are accelerated and run more efficiently by using the full width of a processor data bus to perform operations on packed data. This potentially eliminates the need to transfer smaller units of data across the processor data bus to perform one or more operations, one element at a time.

Alternative embodiments of an execution unit 2208 may also be used in microcontrollers, embedded processors, graphics devices, DSPs, and other types of logic circuits. System 2200 includes memory 2220. Memory 2220 includes a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, or other storage device. Memory 2220 stores instructions and/or data represented by data signals to be executed by processor 2202.

It should be noted that any of the above features or aspects of the invention can be derived from one or more of the 22 connections shown can be used. For example, one or more aspects of the invention described above may be implemented on a bare die carried (ODI) interconnect, not shown, for coupling internal units of processor 2202. Or the invention is a processor bus 2210 (e.g. other known high performance computing interconnect), a high bandwidth memory path 2218 to memory 2220, a point-to-point connection to graphics accelerator 2212 (e.g. with Peripheral Component Interconnect Express (PCIe) compliant structure) , a controller hub connection 2222, an I/O or other connection (eg, USB, PCI, PCIe) for coupling the other illustrated components. Some examples of such components include audio controller 2236, firmware hub (flash BIOS) 2228, wireless transceiver 2226, data storage 2224, legacy I/O controller 2210 containing user input and keyboard interfaces 2242, an expansion serial port 2238, such as universal serial bus (USB), and a network controller 2234. The data storage device 2224 may include a hard drive, floppy disk, CD-ROM device, flash memory device, or other mass storage device.

On 23 Referring to FIG. 1, a block diagram of a second system 2300 is shown in accordance with an embodiment of the present invention. As in 23 Multiprocessor system 2300 is shown as a point-to-point connection system and includes a first processor 2370 and a second processor 2380 coupled via a point-to-point connection 2350 . Each of processors 2370 and 2380 may be a version of a processor. In one embodiment, 2352 and 2354 are part of a serial, point-to-point, coherent fabric, such as a high performance architecture. As a result, the invention can be implemented within the QPI architecture.

While only two processors 2370, 2380 are shown, it should be understood that the scope of the present invention is not so limited. In other embodiments, one or more other processors may be included in a given processor.

Processors 2370 and 2380 are shown with integrated memory controllers 2372 and 2382, respectively. Processor 2370 also includes as part of its bus control units point-to-point (PP) interfaces 2376 and 2378; similarly, the second processor 2380 includes PP interfaces 2386 and 2388. Processors 2370, 2380 may exchange information over a point-to-point (PP) interface 2350 using PP interface circuits 2378,2388. As in 23 IMCs 2372 and 2382 are shown coupling the processors to respective memories, namely memory 2332 and memory 2334, which may be portions of a main memory attached locally to the respective processors.

Processors 2370, 2380 each exchange information with a chipset 2390 via individual P-P interfaces 2352, 2354 using point-to-point interface circuits 2376, 2394, 2386, 2398. Chipset 2390 also exchanges information with a high performance graphics circuit 2338 via a interface circuit 2392 over a high performance graphics link 2339.

A shared cache (not shown) may reside on one processor or external to both processors; also connected to the processors via a PP link so that local cache information from either or both processors can be stored in the shared cache when a processor is placed in a low power mode.

Chipset 2390 can be coupled to a first bus 2316 via an interface 2396 . In one embodiment, the first bus 2316 may be a peripheral component interconnect (PCI) bus or a bus such as a PCI Express bus or other third generation I/O interconnect bus, although the scope of the present invention is not so limited.

As in 23 various I/O devices 2314 are shown coupled to the first bus 2316 along with a bus bridge 2318 coupling a first bus 2316 to a second bus 2320 . In one embodiment, the second bus 2320 comprises a low pin count (LPC) bus. Various devices are coupled to the second bus 2320, including, for example, a keyboard and/or mouse 2322, communication devices 2327, and a storage unit 2328 such as a floppy disk drive or other mass storage device, often containing instructions/code and data 2330, in one embodiment. An audio I/O 2324 coupled to the second bus 2320 is also shown. It should be noted that other architectures are possible if the components involved and interconnect architectures vary. For example, instead of the point-to-point architecture, 23 a system implementing a multidrop bus or other such architecture.

Next is on 24 Referring to FIG. 1, an embodiment of a System on Chip (SOC) design according to the inventions is shown. As a specific illustrative example, SOC 2400 is included in a user equipment (UE). In one embodiment, UE refers to any device to be used by an end user to communicate, such as a handheld phone, smartphone, tablet, ultra-thin notebook, notebook with broadband adapter, or any other similar communication device. Often a UE connects to a base station or hub, which may correspond in nature to a mobile station (MS) in a GSM network.

Here, SOC 2400 includes 2 cores - 2406 and 2407. Similar to the above, cores 2406 and 2407 may be compliant with an instruction set architecture, such as an Intel® Architecture Core™ based processor, an Advanced Micro Devices, Inc. (AMD ), a MIPS-based processor, an ARM-based processor or a customer, licensees or adopters thereof. Cores 2406 and 2407 are coupled to cache controller 2408 associated with bus interface unit 2409 and L2 cache 2411 to communicate with other parts of system 2400. Connection 2410 includes an on-chip connection, such as IOSF, AMBA, or other connection discussed above that may implement one or more aspects described herein.

Interface 2410 provides communication channels for the other components, such as a Subscriber Identity Module (SIM) 2430 to interface with a SIM card, a boot ROM 2435 to hold boot code for execution by cores 2406 and 2407 for initialization and for booting SOC 2400, SDRAM controller 2440 to interface with external memory (e.g. DRAM 2460), Flash controller 2445 to interface with non-volatile memory (e.g. Flash 2465), peripheral controller 2450 (e.g. serial peripheral interface) to provide an interface with peripheral devices. video codecs 2420 and video interface 2425 to display and receive input (e.g. touch input), GPU 2415 to perform graphics-related computations, etc. Any of these interfaces may incorporate aspects of the invention described herein.

In addition, the system shows peripherals for communication, such as a Bluetooth module 2470, 3G modem 2475, GPS 2485, and WiFi 2485. As noted above, a UE includes radio for communication. Therefore, not all of these peripheral communication modules are required. However, some form of radio for external communication must be included in a UE.

While the present invention has been described in terms of a limited number of embodiments, those skilled in the art will recognize numerous modifications and variations therefrom. It is intended that the appended claims cover all such modifications and variations as fall within the true spirit and scope of the present invention.

A design can go through different stages, from creation to simulation to production. Data representing a theme can represent the theme in different ways. First, as is useful in simulations, the hardware can be represented using a hardware description language or another functional description language. Additionally, a circuit level model with logic and/or transistor gates may be generated at some stages of the design process. In addition, most designs at some stage reach a data plane that represents the physical placement of various devices in the hardware model. When conventional semiconductor fabrication techniques are employed, the data representing the hardware model may be the data specifying the presence or absence of various features on different mask layers for masks used to fabricate the integrated circuit. In each representation of the design, the data can be stored in any form of machine-readable medium. Internal storage, or magnetic or optical storage such as a floppy disk, may be the machine-readable medium for storing information transmitted via optical or electrical waves that are modulated or otherwise generated to transmit such information. When an electrical carrier wave that indicates or carries the code or design is transmitted, so that copying, buffering, or retransmission of the electrical signal is performed, a new copy is made. Thus, a communications provider or a network provider may store on a transient, machine-readable medium, at least temporarily, an item, such as information, encoded in a carrier wave embodying techniques of embodiments of the present invention.

A module, as used herein, means any combination of hardware, software, and/or firmware. For example, a module includes hardware, such as a microcontroller, associated with a non-transitory medium for storing code adapted to be executed by the microcontroller. Therefore, in one embodiment, a reference to a module refers to hardware that is specifically configured to recognize and/or execute code held in a non-transitory medium. Furthermore, in another embodiment, the use of a module refers to the non-transitory medium containing the code that is specifically adapted to be executed by the microcontroller to perform predetermined operations. And as can be deduced, in another embodiment, the term module (in this example) may refer to the combination of the microcontroller and the non-transitory medium. Conventionally, module boundaries presented as separate vary and may overlap. For example, a first and second module may share hardware, software, firmware, or a combination thereof, while possibly retaining some hardware, software, or firmware. In one embodiment, use of the term logic includes hardware such as transistors, registers, or other hardware such as programmable logic devices.

The use of the phrase "configured to," in one embodiment, refers to arranging, assembling, manufacturing, offering for sale, importing, and/or designing a device, hardware, logic, or element to perform a designated or specific task. In this example, a device or element thereof that is not running is nevertheless "configured to" perform a designated task if it is designed, paired, and/or connected to perform the designated task. As a purely illustrative example, a logic gate may provide a 0 or a 1 during operation. But a logic gate that is “configured” to provide an enable signal to a clock does not include every possible logic gate that can provide a 1 or 0. Instead, the logic gate is one that is coupled in such a way that, during operation, the 1 or 0 is output to turn on the clock. Again, the use of the term "configured to" does not imply an operation, but instead focuses on the latent state of a device, hardware, and/or item, where the device, hardware, and/or item is designed to perform a specific task when the device, hardware and/or item is in operation.

Further, in one embodiment, use of the phrases "to," "capable of," or "operable to" refers to a device, logic, hardware, and/or element designed to enable use of the enable the device, logic, hardware and/or element in a specific way. As above, it should be noted that the use of to, able to, operable to, in one embodiment refers to the latent state of a device, logic, hardware, and/or element, where the device, the Logic, the hardware and/or element is not operational but is designed to allow a device to be used in a specific way.

A value, as described herein, includes any known representation of a number, state, logic, or binary logic state. Often the use of logic levels, logic values, or logical values is also referred to as 1's and 0's, which simply represent binary logic states. For example, a 1 represents a high logic state and a 0 represents a low logic state. In one embodiment, a memory cell, such as a transistor or flash cell, may be capable of holding a single logical value or multiple logical values. However, other representations of values in computer systems have also been used. For example, the decimal number ten can also be represented as a binary value of 1010 and the letter A in hexadecimal. Thus, a value includes any representation of information that can be held in a computer system.

In addition, states can be represented by values or parts of values. As an example, a first value, such as a logical value, may represent a default or initial state, while a second value, such as logical zero, may represent a non-default state. Additionally, in one embodiment, the terms reset and set refer to a default and updated value or state, respectively. For example, a default value potentially includes a high logical value, i. H. a reset, while an updated value potentially includes a low logic value, i.e., a fix. Note that any combination of values can be used to represent any number of states.

The method, hardware, software, firmware, or code embodiments discussed above may be implemented via instructions or code stored on a machine-accessible, machine-readable, computer-accessible, or computer-readable medium, executable by a processing element can. A non-transitory machine-accessible/readable medium includes any mechanism that provides (i.e., stores and/or transmits) information in a form readable by a machine, such as a computer. B. a computer or electronic system is readable. For example, a non-volatile, machine-accessible medium includes random access memory (RAM), such as static RAM (SRAM) or dynamic RAM (DRAM); ROME; a magnetic or optical storage medium; flash memory devices; electrical storage devices; optical storage devices; acoustic storage devices; other forms of storage devices to retain information received from transient (propagating) signals (e.g., carrier waves, infrared signals, digital signals); etc., to be distinguished from the non-volatile media capable of receiving information from them.

Instructions used to program logic to perform embodiments of the invention may reside within memory in the system, such as a memory. B. a DRAM, cache, flash memory or other memory can be stored. Additionally, the instructions may be sent over a network or other computer-readable media. Therefore, a machine-readable medium may include any mechanism to store or transmit information in a form that is readable by a machine (e.g., a computer), but is not limited to floppy disks, optical disks, compact disc Read-only memories (CD-ROMs), and magneto-optical data carriers, read-only memories (ROMs), random access memories (RAM), erasable programmable read-only memories (EPROM), electrically erasable programmable read-only memories (EEPROM), magnetic or optical cards, flash memory or a physical, machine-readable storage used in the transmission of information over the Internet using electrical, optical, acoustic or other forms of propagated signals (e.g., carrier waves, infrared signals, digital signals, etc.). Accordingly, a computer-readable medium includes any type of machine-readable medium capable of storing or transmitting electronic instructions or information in a machine (e.g., computer) readable form.

The following examples relate to embodiments consistent with this description. One or more embodiments may include an apparatus, system, machine-readable memory, machine-readable medium, hardware and/or software-based logic, and method for receiving data on one or more data lanes of one physical connection, a valid signal on another of the lanes of the physical link identifying that valid data is to follow the assertion of the valid signal on the one or more data lanes, and to receive a data stream signal on another of the lanes of the physical link identifying a type of the data on the identified one or more lanes.

In at least one example, the physical layer logic is also to send a link state machine management signal over another of the lanes of the physical link.

In at least one example, the physical layer logic is further to transmit a sideband signal over a sideband link.

In at least one example, the type includes a protocol associated with the data, where the protocol is one of a variety of protocols that utilize the physical connection.

In at least one example, the type includes link layer packet data.

In at least one example, the data is intended to enable link state transitions for the physical link.

In at least one example, the physical layer logic is further to decode the data stream signal to identify which of a plurality of different protocols the data applies to.

In at least one example, the physical layer is to further forward the data to upper layer protocol logic conforming to a particular one of the plurality of protocols identified in the data stream signal.

In at least one example, the device includes, in addition to the physical layer logic, link layer logic and other upper layer logic of each of the plurality of protocols.

In at least one example, the plurality of protocols includes at least two of Peripheral Component Interconnect (PCI), PCI Express Interconnect (PCIe), Intel In-Die Interconnect (IDI), and Quick Path Interconnect (QPI).

In at least one example, the physical layer logic is to further determine errors in each of the plurality of protocols.

In at least one example, the physical layer logic is to further determine errors in one or more of the valid signal and the data stream signal.

In at least one example, the physical layer logic shall further define a data window for data to be sent on the data lanes, and the data window corresponds to the valid signal.

In at least one example, the data window corresponds to a data symbol, and the valid data signal is to be asserted in a window immediately preceding the window in which the data is to be sent.

In at least one example, data on data lanes in a window immediately following a preceding window in which the valid signal is not asserted should be ignored.

In at least one example, the window corresponds to a byte period.

In at least one example, each of the valid data signal, data, and the data stream signal is matched according to data windows defined for the physical link.

In at least one example, the data stream signal is intended to be sent during the same window as the data.

In at least one example, the physical connection connects two devices in a multi-chip package.

In at least one example, the physical layer is also intended to re-center signals on the lanes of the physical link.

In at least one example, the lanes are to be re-centered based on the valid signal.

In at least one example, a data stream signal is received on a dedicated data stream signal path of the data connection during a second window, the data stream signal is decoded, and a protocol associated with the data is determined from the decoding of the data stream signal.

In at least one example, the data link is capable of transmitting data of a variety of different protocols.

In at least one example, data is identified to be sent on the data link, a valid signal is sent on an outgoing valid signal lane of the data link during a particular time window corresponding to the data to be sent, and the data is sent during another window, immediately succeeding the particular window is sent on dedicated outbound lanes.

In at least one example, the plurality of data lanes further includes a dedicated connection state machine sideband lane.

In at least one example, the first device includes a first die in a package and the second device includes a second die in the package.

In at least one example, the first device comprises a device on the housing and the second device comprises a device that is not on the housing.

One or more embodiments may provide an apparatus, system, machine-readable memory, machine-readable medium, hardware and/or software-based logic, and method for identifying data to be sent on dedicated data lanes of a data connection in order to during a particular window corresponding to data to be sent on the data link, to send a valid signal on a dedicated valid signal lane of the data link, to send the data on dedicated lanes of the data link during a further window immediately following the particular window, and to send a To send a data stream signal on a data stream signal link that is encoded to identify a type of data.

In at least one example, the valid signal is intended to indicate that data on the data lanes is valid data during the other window.

In at least one example, the data streaming signal connection comprises a dedicated data streaming signal connection.

In at least one example, the data stream signal is operable to identify whether a particular protocol is associated with the data.

In at least one example, the physical layer logic is included in a common physical layer, and a plurality of protocols share the common physical layer, and the particular protocol is included in the plurality of protocols.

In at least one example, the plurality of protocols includes two or more of PCI, PCIe, IDI, and QPI.

In at least one example, the data stream signal is further adapted to identify whether the data comprises link layer packets.

In at least one example, the data stream signal is further adapted to identify whether the sideband data.

In at least one example, the physical layer logic is to further determine the data type and encode the data stream signal to identify the particular type.

In at least one example, the physical layer shall also send link state machine sideband (LSM_SB) signals on a dedicated LSM_SB lane of the data link.

In at least one example, the physical layer logic is also to transmit sideband signals on a separate sideband link from the data link.

In at least one example, the physical layer is also to transmit link layer data on the data lanes, the link layer data being used to transition the data link from a first connection state to a second connection state.

In at least one example, the first connection state comprises an active connection state and the second connection state comprises a low power connection state.

In at least one example, the physical layer logic is further to identify a first data window that corresponds to the valid signal and transmit the data on the data lanes within a second data window that immediately follows the first data window.

In at least one example, failing to assert the valid signal indicates that data on the data lanes should be ignored as invalid in an immediately subsequent window.

In at least one example, each of the first and second data windows is defined to correspond to a byte period.

In at least one example, each of the valid signal, data, and data stream signal are matched according to the data windows defined for the physical connection.

In at least one example, the data stream signal is intended to be sent during the same window as the data.

In at least one example, the physical layer is further to generate each of the valid and stream signals.

In at least one example, the data link connects two devices in a multi-chip package.

In at least one example, the data link is intended to support data speeds in excess of 8 Gb/s.

One or more embodiments may provide an apparatus, system, machine-readable memory, machine-readable medium, hardware and/or software-based logic, and method for providing unidirectional signaling on a data link that includes a plurality of lanes that include a plurality of data lanes, one or more valid signal lanes, one or more data stream lanes, and to transmit a clock signal for use by the plurality of lanes, wherein signals transmitted on each of the plurality of lanes are to be aligned with the clock signal.

In at least one example, each of the data lanes is terminated to a regulated voltage at the center of the lane.

In at least one example, the regulated voltage for each of the plurality of data lanes is provided by a single voltage regulator.

In at least one example, the regulated voltage is substantially equal to Vcc/2, where Vcc includes a supply voltage.

In at least one example, the physical layer logic shall attempt to provide crosstalk rejection between two or more of the plurality of data lanes.

In at least one example, crosstalk cancellation is provided by adding a weighted high-pass filtered aggressor signal on a first of the two or more data lanes to the signal on a second of the two or more data lanes.

In at least one example, the physical layer logic is to generate the weighted high-pass filtered aggressor signal using at least part of a resistor-capacitor (RC) low-pass filter.

In at least one example, the physical layer logic is to provide per-bit duty cycle correction.

In at least one example, the physical layer logic is to detect skews on at least a particular one of the data lanes and remove the skews on the particular data lane.

In at least one example, the physical layer logic shall further apply AC data bus inversion (DBI) to at least one of the data lanes.

In at least one example, the clock signal comprises a half-rate forward clock signal.

In at least one example, the physical layer logic is to further provide ESD protection.

In at least one example, the physical layer logic is implemented at least in part by hardware circuitry.

In at least one example, valid signals are to be carried on the valid signal lanes, and each valid signal identifies that valid data is to follow the assertion of the valid signal on the plurality of data lanes, and data stream signals are to be carried on the data stream signal lanes, and each data stream signal identifies one Type of data on the one or more data lanes.

In at least one example, the data connection shall support data speeds in excess of 8 Gb/s.

One or more embodiments may provide an apparatus, system, machine-readable memory, machine-readable medium, hardware and/or software-based logic, and method for providing unidirectional signaling on a data link that includes a plurality of lanes that include a plurality of data lanes, one or more valid signal lanes, one or more data stream lanes, and one or more connection state machine sideband lanes to transmit a clock signal for use by the plurality of lanes, wherein signals transmitted on each of the plurality of lanes are associated with the clock signals are to be balanced to provide crosstalk rejection between two or more of the plurality of data lanes and to provide per-bit duty cycle correction for the data link, with each of the data lanes being terminated to a regulated voltage midway through the lane.

In at least one example, the physical layer logic is further to detect skews on at least a particular one of the data lanes and remove the skew of the particular data lane.

One or more embodiments may provide an apparatus, system, machine-readable memory, machine-readable medium, hardware and/or software-based logic, and method to identify that respective upper layers of each of a plurality of layered protocols transition a data connection from request an active link state to a low power link state, wherein each of the plurality of layered protocols is to use the data link as a physical layer, and to transition the data link from the active link state to the low power link state based on an identification that the upper layers of each of the plurality of layered protocols requests a transition to the low power connection state.

In at least one example, the physical layer logic shall further participate in a handshake with other devices to cause the data link to transition to the low power link state.

In at least one example, the handshake comprises a link layer handshake.

In at least one example, the physical layer logic is to send link layer data in the link layer handshake while the data link is in the link active state.

In at least one example, the physical layer logic shall send a data stream signal substantially concurrently with the link layer data to identify that data sent on data layers of the data link comprises link layer packets.

In at least one example, the data stream signal is sent on a dedicated data stream signal path of the data link during a particular window, and the link layer data is also sent during the particular window.

In at least one example, the physical layer logic shall send a valid signal on a dedicated valid signal lane of the data link, with the valid signal being sent in another window immediately preceding the particular window to indicate that those being sent in the particular window data are valid.

In at least one example, the handshake includes handshake communication over a sideband connection.

In at least one example, the handshake includes a link layer handshake and the handshake communication over the sideband link.

In at least one example, the handshake communication over the sideband link acknowledges the link layer handshake.

In at least one example, the physical layer logic is further to identify a request from an upper layer of a first of the plurality of layered protocols to transition the data connection from the active connection state to a low power connection state.

In at least one example, the physical layer logic shall further wait to transition the data link from the active link state to the low power link state until requests from each of the other protocols of the plurality of layered protocols are received.

In at least one example, for each of the plurality of layered protocols, the physical layer logic is to track whether the protocol has requested to transition the data link from the active link state to the low power link state.

In at least one example, the physical layer logic shall further generate a response to the request to acknowledge the transition of the data link from the active link state to the low power link state prior to the actual transition of the data link from the active link state to the low power link state.

In at least one example, the response is sent while the data link's transition from the active link state to the low power link state is pending approval of one or more of the other protocols in the plurality of layered protocols.

In at least one example, the low power connection state includes an idle connection state.

In at least one example, the plurality of layered protocols includes one or more of PCI, PCIe, IDI, and QPI.

A system may be provided to include a data link comprising a plurality of lanes, a first device, and a second device communicatively coupled to the first device using the data link, the second device having upper layer logic of a first protocol, Upper layer logic of a second protocol, each of the plurality of protocol stacks sharing a common physical layer, and physical layer logic for the common physical layer, wherein the physical layer logic is to determine that each of the protocols, including the first and second protocols, using the data link allow the data link to transition from an active link state to a low power link state before the data link is in the low power link state is transferred.

In at least one example, the plurality of lanes includes a plurality of data lanes, one or more valid signal lanes, one or more data stream lanes.

In at least one example, valid signals are to be carried on the valid signal lanes, and each valid signal identifies that valid data is to follow the assertion of the valid signal on the plurality of data lanes, and data stream signals are to be carried on the data stream signal lanes, and each data stream signal identifies one Type of data on the one or more data lanes.

In at least one example, transitioning the data connection to the low power connection state includes a handshake between the first and second devices.

In at least one example, the handshake includes a link layer handshake and a sideband handshake.

In at least one example, the first device includes a first die in a package and the second device includes a second die in the package.

In at least one example, the first device comprises a device on the housing and the second device comprises a device that is not on the housing.

Claims (26)

Device comprising: a physical layer interface comprising: a clock line configured to support a clock signal; a control interface configured to support one or more control signals, the one or more control signals comprising control signals to effect transitions in connection states according to a state machine; multiple data lines configured to transmit data; and a valid signal line configured to support transmission of a valid signal, wherein transmission of data on the data lines is to be coordinated with transmission of the valid signal on the valid signal line, and wherein the clock line and the valid signal line are different lines. device after claim 1 , further comprising physical layer logic configured to generate the valid signal. device after claim 2 , wherein the physical layer logic is configured to manage training of a connection including the plurality of data lines. device after claim 3 , wherein the link states include multiple link training states, and the link training states are used in training the link. device after claim 4 , wherein a specific one of the plurality of link training states includes a low power state where no data is to be sent on the link. device after claim 3 , wherein training the link includes sending and receiving training sequences on the link. Device according to one of Claims 1 - 6 , wherein the control signals comprise sideband control signals. Device according to one of Claims 1 - 7 , wherein the physical layer interface comprises a physical layer abstraction. Device according to one of Claims 1 - 8th , further comprising a transmitter configured to transmit the valid signal and to transmit the specific data on the plurality of data lines coordinated with the valid signal. Device comprising: an interface that includes: a clock signal line configured to receive a clock signal; a control interface configured to receive one or more control signals, the one or more control signals comprising control signals to effect transitions in connection states according to a state machine; a plurality of data lines configured to receive data transmitted by another device on a link; and a valid signal line configured to receive a valid signal corresponding to the data, wherein transmission of data on the data lines is to be coordinated with transmission of the valid signal on the valid signal line, and wherein the clock line and the valid signal line are different lines. device after claim 10 , further comprising physical layer logic configured to identify receipt of the valid signal on the valid signal line and to process the data received on the plurality of data lines based on the receipt of the valid signal. Device according to one of Claims 10 - 11 , wherein the control signal comprises a sideband signal. Device according to one of Claims 10 - 12 , wherein the valid signal is timed to an edge of the clock signal. Device according to one of Claims 10 - 13 , wherein the link states include link training states. device after Claim 14 wherein training sequences are to be transmitted and received by the device during one or more of the link training states. device after claim 15 , where the training sequences are according to a defined connection protocol. device after Claim 16 , wherein the defined connection protocol comprises one of a plurality of different connection protocols supported using the interface. Procedure, which includes: sending a clock signal on a dedicated clock line of an interface; sending a control signal on a control line, the control signal to effect transitions in connection states according to a state machine; identifying data to be sent on multiple data lines of the interface; sending a valid signal on a dedicated valid line of the interface, the valid signal corresponding to the specific data; and sending the specific data on the multiple data lines to be aligned with the valid signal, wherein the dedicated clock line and the dedicated valid line are different lines of the interface. System comprising means set up to follow the method Claim 18 to perform. system after claim 19 , the means comprising a computer-readable storage medium having instructions stored thereon, the instructions being executable by data processing means to carry out at least part of the method according to Claim 18 to perform. System that includes: a first data processing device; a second data processing device connected to the first data processing device via a connection, the second data processing device comprising a physical layer interface arranged to support the connection and the physical layer interface comprising: a clock signal line configured to receive a clock signal; a control interface configured to receive one or more control signals, the one or more control signals comprising control signals to effect transitions in connection states according to a state machine; a plurality of data lines configured to receive data transmitted by another device on a link; and a valid signal line configured to receive a valid signal corresponding to the data, wherein transmission of data on the data lines is to be coordinated with transmission of the valid signal on the valid signal line, and wherein the clock signal line and the valid signal line are different lines. system after Claim 21 , wherein the second data processing device comprises a processor. system after Claim 22 , wherein the first data processing device comprises a second processor. system after Claim 21 , wherein the second data processing device comprises a memory controller. system after Claim 21 , wherein the second data processing device comprises a graphics processor. system after Claim 21 , wherein the second data processing device comprises a network controller.

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