JP2018085129A - Multichip package link - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an interconnect architecture which enables high-speed communication in a computing system.SOLUTION: A physical layer logic receives data on one or more data lanes of a physical link, receives an effective signal for specifying that effective data continues to assertion of the effective signal on one or more data lanes on another lane of the physical link, and receives a stream signal for specifying a type of data on one or more data lanes, on another lane of the physical link.SELECTED DRAWING: Figure 7

Description

  The present disclosure relates to computing systems, and in particular (but not exclusively) to point-to-point interconnects.

  Advances in semiconductor processing and logic design have allowed an increase in the amount of logic that can exist on an integrated circuit device. As a natural consequence, computer system configurations can vary from single or multiple integrated circuits in the system to multiple cores, multiple hardware threads and multiple logical processors residing on individual integrated circuits, and within such processors. Expanded to other interfaces integrated into. A processor or integrated circuit typically comprises a single physical processor die, where the processor die can include any number of cores, hardware threads, logical processors, interfaces, memories, controller hubs, and the like.

  As a result of the increased ability to accommodate more processing power in smaller packages, smaller computing devices are becoming increasingly popular. Smartphones, tablets, ultra-thin notebooks and other user equipment are growing exponentially. On the other hand, these smaller devices rely on the server for both data storage and complex processing beyond the form factor. Therefore, there is also an increasing demand in the high performance computing market (ie server space). For example, in modern servers, there are usually not only a single processor with multiple cores, but also multiple physical processors (also called multiple sockets) to increase computing power. However, as processing power increases with the number of devices in the computing system, communication between sockets and other devices becomes more critical.

  In fact, interconnects have grown from a more traditional multi-drop bus that primarily handles telecommunications to a full-fledged interconnect architecture that facilitates high-speed communications. Unfortunately, the demand for future processors is imposed on the ability of existing interconnect architectures to consume the corresponding demand at a higher rate.

1 illustrates one embodiment of a computing system including an interconnect architecture. 1 illustrates one embodiment of an interconnect architecture that includes a layered stack. FIG. 4 illustrates one embodiment of a request or packet generated or received within an interconnect architecture. 1 illustrates one embodiment of a transmitter and receiver pair for an interconnect architecture. 1 illustrates one embodiment of a multi-chip package. FIG. 2 is a simplified block diagram of a multichip package link (MCPL). 2 is an exemplary signaling representation in an exemplary MCPL. FIG. 3 is a simplified block diagram illustrating data lanes in an exemplary MCPL. FIG. 3 is a simplified block diagram illustrating an exemplary crosstalk cancellation technique in one embodiment of MCPL. FIG. 6 is a simplified circuit diagram illustrating an exemplary crosstalk cancellation component in one embodiment of the MCPL. FIG. 3 is a simplified block diagram of MCPL. FIG. 2 is a simplified block diagram of MCPL interfacing with higher layer logic of multiple protocols using a logical PHY interface (LPIF). 2 is an exemplary signaling representation in an exemplary MCPL related to link recovery. FIG. 6 is an exemplary bit mapping of data on an exemplary MCPL lane. FIG. FIG. 6 is an exemplary bit mapping of data on an exemplary MCPL lane. FIG. FIG. 6 is an exemplary bit mapping of data on an exemplary MCPL lane. FIG. FIG. 3 is a diagram of a portion of an example link state machine. FIG. 6 is a flow diagram associated with exemplary centering of links. FIG. 3 is an illustration of an exemplary link state machine. FIG. 6 is a signaling diagram for entering a low power state. 1 illustrates one embodiment of a block diagram for a computing system comprising a multi-core processor. FIG. 6 illustrates another embodiment of a block diagram for a computing system comprising a multi-core processor. 1 illustrates one embodiment of a block diagram for a processor. FIG. 6 illustrates another embodiment of a block diagram for a computing system comprising a processor. 1 illustrates one embodiment of a block for a computing system including multiple processors. 1 illustrates an exemplary system implemented as a system on chip (SoC).

  Like reference numbers and designations in the various drawings indicate like elements.

  In the following description, to provide a thorough understanding of the present invention, specific types of processors and system configurations, specific hardware structures, specific architecture and microarchitecture details, specific register configurations, specific instruction types, Numerous specific details are shown, such as specific system components, specific measurements / heights, specific processor pipeline stages and example operations. However, it will be apparent to one skilled in the art that these specific details need not be used to practice the present invention. Other examples include specific and alternative processor architectures, specific logic circuits / codes for the described algorithm, specific firmware codes, specific interconnect operations, specific logic configurations, specific manufacturing techniques and materials, Well-known components or methods, such as specific compiler implementations, specific representations of algorithms in code, specific power-down and power-gating techniques / logic, and other specific operational details of the computing system, In order to avoid unnecessarily obscuring the invention, it has not been described in detail.

  Although the following embodiments may be described with reference to energy savings and energy efficiency in a particular integrated circuit such as a computing platform or microprocessor, other embodiments may include other types of integrated circuits and logic. Applicable to devices. Similar techniques and teachings of the embodiments described herein can be applied to other types of circuits or semiconductor devices that can also benefit from better energy efficiency and energy savings. For example, the disclosed embodiments are not limited to desktop computer systems or Ultrabooks ™. It may also be used in other devices such as handheld devices, tablets, other thin notebooks, system on chip (SOC) devices and embedded applications. Some examples of handheld devices include mobile phones, internet protocol devices, digital cameras, personal digital assistants (PDAs), and handheld PCs. Embedded applications typically perform a microcontroller, digital signal processor (DSP), system on chip, network computer (NetPC), set top box, network hub, wide area network (WAN) switch, or the functions and operations taught below. Including any other system that can. Furthermore, the apparatus, methods and systems described herein are not limited to physical computing devices, but can also relate to software optimization for energy savings and energy efficiency. As will be readily apparent in the following description, the method, apparatus and system embodiments described herein (whether referenced in hardware, firmware, software or combinations thereof) It is essential to "green technology" that is balanced with the concerns.

  As computing systems have advanced, components within computing systems have become more complex. As a result, interconnect architectures for coupling and communicating between components are also becoming increasingly complex to ensure that bandwidth requirements for optimal component operation are met. Furthermore, different market segments require different aspects of the interconnect architecture to meet market demands. For example, the server may require higher performance, while the mobile ecosystem may in some cases sacrifice overall performance to save power. However, providing the best possible performance while maximizing power savings is the single goal of most fabrics. In the following, a plurality of interconnects that will potentially benefit from aspects of the invention described herein are discussed.

  One interconnect fabric architecture comprises a peripheral component interconnect (PCI) express (PCIe) architecture. The main goal of PCIe is across multiple market segments: clients (desktop and mobile), servers (standard and enterprise), and embedded and communications devices, with components and devices from various vendors in an open architecture. It is possible to interoperate. PCI Express is a high performance general purpose I / O interconnect defined for a wide variety of future computing and communication platforms. While some PCI attributes such as usage model, load-store architecture and software interface are maintained throughout the revision, the previous parallel bus implementation has been replaced with a highly scalable and fully serial interface. Yes. More recent versions of PCI Express take advantage of advances in point-to-point interconnects, switch-based technology, and packetized protocols to bring new levels of performance and features. Power management, quality of service (QoS), hot plug / hot swap support, data integrity, and error handling are some of the evolutionary features supported by PCI Express.

  Referring to FIG. 1, there is shown one embodiment of a fabric comprised of point-to-point links that interconnect a set of components. System 100 includes a processor 105 and a system memory 110 coupled to a controller hub 115. The processor 105 includes any processing element such as a microprocessor, host processor, embedded processor, coprocessor or other processor. The processor 105 is coupled to the controller hub 115 through a front side bus (FSB) 106. In one embodiment, the FSB 106 is a serial point-to-point interconnect as described below. In another embodiment, link 106 includes a serial, differential interconnect architecture that conforms to different interconnect standards.

  The system memory 110 includes any memory device, such as random access memory (RAM), non-volatile (NV) memory, or other memory accessible by devices in the system 100. System memory 110 is coupled to controller hub 115 through memory interface 116. Examples of memory interfaces include double data rate (DDR) memory interfaces, dual channel DDR memory interfaces, and dynamic RAM (DRAM) memory interfaces.

  In one embodiment, the controller hub 115 is a root hub, root complex, or root controller in a peripheral component interconnect express (PCIe or PCIE) interconnect hierarchy. Examples of the controller hub 115 include a chipset, a memory controller hub (MCH), a north bridge, an interconnect controller hub (ICH), a south bridge, and a route controller / hub. In many cases, the term chipset refers to two physically separate controller hubs, namely a memory controller hub (MCH) coupled to an interconnect controller hub (ICH). Note that current systems often include an MCH integrated into the processor 105, while the controller 115 communicates with I / O devices in a manner similar to that described below. In some embodiments, peer-to-peer routing is optionally supported through the route complex 115.

  Here, the controller hub 115 is coupled to the switch / bridge 120 through a serial link 119. Input / output modules 117 and 121, which may also be referred to as interfaces / ports 117 and 121, include / implement a layered protocol stack for providing communication between controller hub 115 and switch 120. In one embodiment, multiple devices can be 120 coupled to the switch.

  The switch / bridge 120 moves packets / messages from the device 125 upstream, ie up the hierarchy towards the root complex, to the controller hub 115 and downstream, ie down the hierarchy away from the root controller. Route from the processor 105 or system memory 110 to the device 125. In one embodiment, switch 120 is referred to as a logic assembly of multiple virtual PCI bridge devices. The device 125 is an I / O device, network interface controller (NIC), add-in card, audio processor, network processor, hard drive, storage device, CD / DVD ROM, monitor, printer, mouse, keyboard, router, portable storage device, Includes any internal or external device or component coupled to an electronic system such as Firewire devices, Universal Serial Bus (USB) devices, scanners and other input / output devices. In PCIe, technical terms such as devices are often called endpoints. Although not shown in detail, the device 125 may include a PCIe to PCI / PCI-X bridge to support legacy PCI devices or other versions of PCI devices. Endpoint devices in PCIe are often categorized as endpoints integrating legacy, PCIe or root complexes.

  Graphic accelerator 130 is also coupled to controller hub 115 through serial link 132. In one embodiment, graphics accelerator 130 is coupled to MCH and MCH is coupled to ICH. The switch 120 and, accordingly, the I / O device 125 are coupled to the ICH. I / O modules 131 and 118 also implement a layered protocol stack to communicate between graphics accelerator 130 and controller hub 115. Similar to the MCH discussion above, the graphics controller or graphics accelerator 130 itself may be integrated into the processor 105.

  Referring to FIG. 2, one embodiment of a layered protocol stack is shown. The layered protocol stack 200 includes any form of layered communication stack, such as a quick path interconnect (QPI) stack PCIe stack, a next generation high performance computing interconnect stack, or other layered stack. Although the discussion immediately below with reference to FIGS. 1-4 relates to a PCIe stack, the same concepts may be applied to other interconnect stacks. In one embodiment, protocol stack 200 is a PCIe protocol stack that includes transaction layer 205, link layer 210, and physical layer 220. Interfaces such as interfaces 117, 118, 121, 122, 126 and 131 in FIG. 1 can be represented as a communication protocol stack 200. A representation as a communication protocol stack can also be referred to as a module or interface that implements / includes the protocol stack.

  PCI Express communicates information between components using packets. Packets are formed in transaction layer 205 and data link layer 210 to carry information from the sending component to the receiving component. As transmitted packets flow through other layers, they are expanded with the additional information needed to process the packets at these layers. On the receiving side, the reverse process takes place and the packets are converted from their physical layer 220 representation to the data link layer 210 representation and finally (in the case of transaction layer packets) processed by the transaction layer 205 of the receiving device. Can be converted into a form that can.

Transaction Layer In one embodiment, transaction layer 205 provides an interface between the processing core of the device and an interconnect architecture such as data link layer 210 and physical layer 220. In this regard, the primary role of transaction layer 205 is the assembly and disassembly of packets (ie, transaction layer packets or TLPs). Transaction layer 205 typically manages credit-based flow control for TLP. PCIe performs split transactions, i.e. transactions with time-separated requests and responses, allowing the link to carry other traffic while the target device collects data for responses.

  In addition, PCIe utilizes credit-based flow control. In this scheme, the device advertises an initial credit amount for each receive buffer in the transaction layer 205. An external device at the other end of the link, such as controller hub 115 of FIG. 1, counts the number of credits consumed by each TLP. If the transaction does not exceed the credit limit, the transaction can be sent. Upon receipt of the response, the credit amount is restored. The advantage of the credit scheme is that the credit return latency does not affect performance if the credit limit is not reached.

  In one embodiment, the four transaction address spaces include a configuration address space, a memory address space, an input / output address space, and a message address section. A memory space transaction includes one or more of a read request and a write request to transfer data to / from a location mapped by the memory. In one embodiment, the memory space transaction can use two different address formats, for example, a short address format such as a 32-bit address, or a long address format such as a 64-bit address. Configuration space transactions are used to access the configuration space of a PCIe device. Transactions to the configuration space include read requests and write requests. Message space transactions (or simply messages) are defined to support in-band communication between PCIe agents.

  Thus, in one embodiment, transaction layer 205 assembles packet header / payload 206. The format for the current packet header / payload can be obtained in the PCIe specification at the PCIe specification website.

  Turning briefly to FIG. 3, one embodiment of a PCIe transaction descriptor is shown. In one embodiment, the transaction descriptor 300 is a mechanism for carrying transaction information. In this regard, the transaction descriptor 300 supports the identification of transactions within the system. Other potential uses include tracking default transaction order and transaction-channel association changes.

  Transaction descriptor 300 includes a global identifier field 302, an attribute field 304, and a channel identifier field 306. In the example shown, a global identifier field 302 is shown that includes a local transaction identifier field 308 and a source identifier field 310. In one embodiment, the global transaction identifier 302 is unique for all outstanding requests.

  According to one embodiment, the local transaction identifier field 308 is a field generated by the requesting agent and is unique for all outstanding requests that require completion for that requesting agent. Further, in this example, the source identifier 310 uniquely identifies the requesting agent in the PCIe hierarchy. Thus, along with the source ID 310, the local transaction identifier 308 field provides a global identification of transactions within the hierarchical domain.

  An attribute field 304 specifies transaction characteristics and relationships. In this regard, the attribute field 304 is potentially used to provide additional information that allows a change in the default handling of the transaction. In one embodiment, the attribute field 304 includes a priority field 312, a reserved field 314, an ordering field 316, and a non-snoop field 318. Here, the priority subfield 312 can be changed by the initiator to assign a priority to the transaction. The reserved attribute field 314 remains reserved for future use or for vendor-defined use. A possible usage model using priority or security attributes may be implemented using reserved attribute fields.

  In this example, the ordering attribute field 316 is used to provide optional information that conveys the ordering type, which can change the default ordering rules. According to one embodiment, the ordering attribute “0” indicates that the default ordering rule is applied, and the ordering attribute “1” represents relaxed ordering. With relaxed ordering, a write can pass a write in the same direction, and a read complete can pass a write in the same direction. The snoop attribute field 318 is used to determine whether the transaction is snooped. As shown, channel ID field 306 identifies the channel with which the transaction is associated.

Link Layer The link layer 210, also referred to as the data link layer 210, serves as an intermediate stage between the transaction layer 205 and the physical layer 220. In one embodiment, the role of the data link layer 210 is to provide a reliable mechanism for exchanging transaction layer packets (TLPs) between two components as a link. One side of the data link layer 210 accepts the TLP assembled by the transaction layer 205, applies the packet sequence identifier 211, ie identification number or packet number, calculates and applies the error detection code, ie CRC 212, changes Submitted TLPs to the physical layer 220 for transmission across the physical layer to external devices.

Physical Layer In one embodiment, the physical layer 220 comprises a logical sub-block 221 and an electrical sub-block 222 for physically transmitting the packet to an external device. Here, the logical sub-block 221 is responsible for the “digital” function of the physical layer 221. In this regard, the logical sub-block includes a transmitter that prepares outgoing information for transmission by the physical sub-block 222 and a receiver that identifies and prepares the received information and then passes it to the link layer 210.

  The physical block 222 includes a transmitter and a receiver. The transmitter is provided with a symbol by logical sub-block 221, which serializes the symbol and transmits it to an external device. The receiver is supplied with serialized symbols from an external device and converts the received signal into a bit stream. The bitstream is deserialized and provided to the logical sub-block 221. In one embodiment, 8b / 10b transmission codes are used. Here, 10-bit symbols are transmitted / received. Here, the packet is framed using the frame 223 using a special symbol. In addition, in one example, the receiver also provides a recovered symbol clock from the incoming serial stream.

  As indicated above, the transaction layer 205, link layer 210, and physical layer 220 are discussed with reference to a specific embodiment of the PCIe protocol stack, but the layered protocol stack is not so limited. In fact, any layered protocol can be included / implemented. By way of example, a port / interface, represented as a layered protocol, (1) sends a packet to the first layer that assembles the packet, ie, the transaction layer, and the second layer that arranges the packet, ie, the link layer Includes a third layer, the physical layer. As a special example, a common standard interface (CSI) layered protocol is used.

  Referring now to FIG. 4, one embodiment of a PCIe serial point-to-point fabric is shown. Although one embodiment of a PCIe serial point-to-point link is shown, the serial point-to-point link is not so limited, as the serial point-to-point link includes any transmission path for transmitting serial data. In the illustrated embodiment, the basic PCIe link includes two low voltage differential drive signal pairs: a transmit pair 406/411 and a receive pair 412/407. Accordingly, device 405 includes transmit logic 406 for transmitting data to device 410 and receive logic 407 for receiving data from device 410. In other words, two transmission paths, namely paths 416 and 417, and two reception paths, ie paths 418 and 419, are included in the PCIe link.

  A transmission path refers to any path for transmitting data, such as a transmission line, copper line, optical line, wireless communication channel, infrared communication link, or other communication path. The connection between two devices, such as device 405 and device 410, is referred to as a link, such as link 415. A link can support one lane, and each lane represents a set of differential signal pairs (one pair for transmission, one pair for reception). To scale bandwidth, a link can aggregate multiple lanes represented by xN, where N is 1, 2, 4, 8, 12, 16, 32, 64 or wider Any supported link width, such as

  A differential pair refers to two transmission paths, such as lines 416 and 417, for transmitting differential signals. As an example, when line 416 switches from a low voltage level to a high voltage level, ie, a rising edge, line 417 drives from a high logic level to a low logic level, ie, a falling edge. Differential signals potentially demonstrate better electrical characteristics, such as better signal integrity, i.e., mutual coupling, voltage overshoot / undershoot, ringing, and the like. This allows for a better timing window that allows for faster transmission frequencies.

  FIG. 5 is a simplified diagram illustrating an exemplary multi-chip package 505 that includes two or more chips or dies (eg, 510, 515) that are communicatively connected using an exemplary multi-chip package link (MCPL) 520. FIG. Although FIG. 5 shows an example of two (or more) dies interconnected using an exemplary MCPL 520, the principles and features described herein with respect to the MCPL implementation are numerous potential. Among other examples, connecting two or more dies (eg, 510, 515), connecting a die (or chip) to another component that is not on the die, and not dying on a package (eg, 505). Any interconnect that connects a die (eg, 510) and other components, including connecting to another device or die, connecting the die to a BGA package, and implementing a Patch on Interposer (POINT) Or it should be understood that it may apply to links.

  Generally, a multi-chip package (eg, 505) has a plurality of integrated circuits (ICs), semiconductor dies or other discrete components (eg, 510, 515) on a unified substrate (eg, silicon or other semiconductor substrate). Packaged into an electronic package that facilitates using the combined components as a single component (eg, as if it were a larger IC). In some cases, the larger component (eg, die 510, 515) is itself on a system-on-chip (SoC), multiprocessor chip, or device, eg, on a single die (eg, 510, 515). IC components such as other components including a plurality of components (e.g., 525-530 and 540-545). The multi-chip package 505 can potentially provide the flexibility to build complex and diverse systems from multiple discrete components and systems. For example, among many examples, each of the dies 510, 515 may be manufactured or otherwise provided by two different entities, and the silicon substrate of the package 505 may be further provided by a third entity. . Further, the die and other components in the multi-chip package 505 are themselves infrastructure for communication between components (eg, 525-530 and 540-545) within the device (eg, 510, 515, respectively). Interconnects or other communication fabrics (eg, 535, 550) that provide Various components and interconnects (eg, 535, 550) can potentially support or use multiple different protocols. Further, communication between dies (eg, 510, 515) can potentially involve transactions between various components on the die via multiple different protocols. Traditional solutions using highly specialized, expensive, package specific solutions based on specific combinations of components (and desired transactions) that are required to be interconnected are chips on a multi-chip package. It may be difficult to design a mechanism that provides communication between (or dies).

  The examples, systems, algorithms, devices, logic, and features described herein can address at least some of the issues identified above. These issues potentially include many other issues not explicitly mentioned herein. For example, some embodiments provide a high bandwidth, low power, low latency interface for connecting a host device (eg, CPU) or other device to a companion chip located in the same package as the host. can do. Such a multi-chip package link (MCPL) can support multiple package options, multiple I / O protocols, and reliability, availability, and serviceability (RAS) functions. . Further, the physical layer (PHY) can include electrical and logical layers and can support longer channel lengths, including channel lengths of up to about 45 mm, and in some cases greater than about 45 mm. In some implementations, the exemplary MCPL can operate at high data rates, including data rates greater than 8 Gb / s to 10 Gb / s.

  In one exemplary implementation of MCPL, the PHY electrical layer provides improvements over conventional multi-channel interconnect solutions (eg, multi-channel DRAM I / O), for example, by way of example, a number of potential examples Among other things, data rate and channel configuration with multiple features, including coordinated intermediate rail termination, low power active crosstalk cancellation, circuit redundancy, bit-by-bit duty cycle correction and deskew, line coding and transmitter equalization Can be extended.

  One exemplary implementation of MCPL further assists in extending data rates and channel configurations (eg, electrical layer features) while also allowing the interconnect to route multiple protocols across the electrical layer. A PHY logic layer can be implemented. Such an implementation can provide and define a modular common physical layer that is designed to work with any existing or future interconnect protocol, independent of the protocol.

  Referring to FIG. 6, a simplified block diagram 600 representing at least a portion of a system including an exemplary embodiment of a multichip package link (MCPL) is shown. A physical electrical connection that connects a first device 605 (eg, a first die that includes one or more subcomponents) with a second device 610 (eg, a second die that includes one or more other subcomponents). MCPL can be mounted using (for example, a wire mounted as a lane). In the particular example shown in the high level representation of FIG. 600, all signals (in channels 615, 620) can be unidirectional and the data signal has both upstream and downstream data transfers. Lanes can be provided. The block diagram 600 of FIG. 6 refers to the first component 605 as the upstream component, the second component 610 as the downstream component, and the physical lane of the MCPL used when transmitting data as the downstream channel 615. The lane used to receive and receive data (from component 610) is referred to as upstream channel 620, but the MCPL between devices 605, 610 can be used for each device to both transmit and receive data between devices. It should be understood that can be used.

  In one exemplary implementation, the MCPL includes an electrical MCPL PHY 625a, 625b (or collectively 625) and a physical layer (including collectively MCPL logic PHYs 630a, 630b (or collectively 630) that implements executable logic). PHY) can be provided. The electrical or physical PHY 625 can provide a physical connection through which data is communicated between the devices 605, 610. Signal conditioning components and logic can be implemented in connection with the physical PHY 625 to establish a high data rate and channel configuration function for the link. This may involve a highly clustered physical connection of about 45 mm or longer in some applications. Logic PHY 630 provides logic to facilitate clocking between potentially multiple different protocols used for communication via MCPL, link state management (eg, of link layers 635a, 635b), and protocol multiplexing. Can be included.

  In one exemplary implementation, the physical PHY 625 may include a set of data lanes per channel (eg, 615, 620) and transmitting in-band data over the set of data lanes. Can do. In this particular example, 50 data lanes are provided for each of upstream channel 615 and downstream channel 620, but any as permitted by layout and power constraints, desired applications, device constraints, etc. Other numbers of lanes can be used. Each channel has one or more dedicated lanes for channel strobe or clock signals, one or more dedicated lanes for valid signals for channels, one or more dedicated lanes for stream signals, and links It may further include one or more dedicated lanes for state machine management or sideband signals. The physical PHY may further include a sideband link 640 that, in some cases, may coordinate state transitions and other attributes of the MCPL connecting the devices 605, 610, among other examples. It can be the bidirectional low frequency control signaling link used.

  As indicated above, MCPL implementations can be used to support multiple protocols. In fact, each device 605, 610 can be provided with multiple independent transaction layers 650a, 650b. For example, each of the devices 605 and 610 can support and use two or more protocols such as PCI, PCIe, QPI, and in-die interconnect (IDI), among others. IDI is a coherent protocol used on the die to communicate between the core, last level cache (LLC), memory, graphics and IO controller. Other protocols can also be supported, including Ethernet protocol, InfiniBand protocol and other PCIe fabric based protocols. The combination of logical PHY and physical PHY is, among other examples, SerDesPHY (PCIe, Ethernet, InfiniBand or other high-speed SerDes) on one die, its higher level implemented on other dies. It can also be used as an inter-die interconnect that connects to layers.

  Logical PHY 630 can also support multiplexing between these multiple protocols in MCPL. For example, a dedicated stream lane can be used to assert an encoded stream signal that specifies which protocol should be applied to data that is transmitted substantially simultaneously on the data lane of the channel. Further, the logical PHY 630 can be used to negotiate different types of link state transitions that different protocols can support or request. In some cases, the LSM_SB signal transmitted over the channel's dedicated LSM_SB lane can be used with the sideband link 640 to communicate and negotiate link state transitions between devices 605, 610. In addition, link training, error detection, skew detection, deskew, and other functions of the conventional interconnect can be exchanged or controlled in part using the logical PHY 630. For example, using a valid signal transmitted over one or more dedicated valid signal lanes within each channel, among other examples, signaling link activity, detecting skew, link errors, and other functions Can be realized. In the particular example of FIG. 6, multiple valid lanes are provided for each channel. For example, data lanes within a channel can be bundled or clustered (physically and / or logically) and valid lanes can be provided for each cluster. Further, in some cases, among a number of examples, it is possible to provide a plurality of strobe lanes that also provide dedicated strobe signals for each cluster in a plurality of data lane clusters in the channel.

  As indicated above, the logical PHY 630 can be used to negotiate and manage link control signals transmitted between devices connected by MCPL. In some implementations, the logical PHY 630 can include link layer packet (LLP) generation logic 660 that can be used to send link layer control messages via MCPL (ie, in-band). Such a message can be sent over the data lane of the channel, and the stream lane identifies that the data is link layer messaging, such as link layer control data, among other examples. Link layer messages enabled using the LLP module 660 include link layer state transitions, power management, loops, among other link layer features between the link layer 635a of the device 605 and the link layer 635b of the device 610. Can help negotiate and execute back, invalidation, re-centering and scrambling.

  Referring to FIG. 7, a diagram 700 depicting exemplary signaling using a set of lanes (eg, 615, 620) within a particular channel of the example MCPL is shown. In the example of FIG. 7, two clusters of 25 data lanes are provided for a total of 50 data lanes in the channel. Although a portion of the lane is shown, others (eg, DATA [4-46] and the second strobe signal lane (STRB)) are shown for convenience (eg, as redundant signals). ) Omitted. When the physical layer is in an active state (eg, not powered off or in a low power mode (eg, L1 state)), a synchronous clock signal can be provided to the strobe lane (STRB). In some implementations, data can be transmitted on both the rising and falling edges of the strobe. Each edge (or half clock cycle) can define a unit interval (UI). Thus, in this example, bits (eg, 705) can be transmitted on each lane, and one byte can be transmitted every 8 UI. The byte period 710 can be defined as 8 UI or as the time to transmit a byte in a single one of the data lanes (eg, DATA [0-49]).

  In some implementations, when a valid signal transmitted in one or more dedicated valid signal channels (eg, VALID0, VALID1) is asserted (high), the receiving device or sink is followed by a byte period 710, etc. Act as a lead indicator for the receiving device to identify that data is being transmitted from the transmitting device or source on the data lane (eg, DATA [0-49]) it can. Alternatively, when the valid signal is low, the source indicates to the sink that the sink will not transmit data on the data lane during subsequent periods. Thus, if the sink logic PHY detects that the valid signal is not asserted (eg, in lanes VALID0 and VALID1), the sink will detect on the data lane (eg, DATA [0-49]) during subsequent periods. Any data that is sent can be ignored. For example, crosstalk noise or other bits may appear in one or more of the data lanes when the source is not actually transmitting any data. A valid signal that is low or not asserted during a previous period (eg, the previous byte period) allows the sink to determine that the data lane is ignored during the subsequent period.

  Data transmitted in each of the MCPL lanes can be strictly aligned to the strobe signal. Periods such as byte periods can be defined based on the strobe, and each of these periods can correspond to a defined window. In this window, signals will be transmitted on data lanes (eg DATA [0-49]), valid lanes (eg VALID1, VALID2) and stream lanes (eg STREAM). Therefore, the alignment of these signals ensures that the valid signal in the previous period window is applied to the data in the subsequent period window and that the stream signal is applied to the data in the same period window. Can be possible. The stream signal can be an encoded signal (eg, 1 byte of data per byte period window) that is encoded to specify the protocol applied to the data transmitted during the same period window.

  For illustration purposes, in the particular example of FIG. 7, a byte period window is defined. Before any data is input in the data lane DATA [0-49], the valid signal is asserted in the period window n (715). In a subsequent period window n + 1 (720), data is transmitted in at least some of the data lanes. In this case, data is transmitted on all 50 data lanes in n + 1 (720). Since the valid signal was asserted for the duration of the preceding period window n (715), the sink device validates the data received on data lane DATA [0-49] during period window n + 1 (720). be able to. In addition, the leading characteristics of the valid signal during period window n (715) allow the receiving device to prepare for incoming data. Continuing the example of FIG. 7, the valid signal remains asserted (in VALID1 and VALID2) for the duration of period window n + 1 (720), and the sink device receives data lane DATA during period window n + 2 (725). Expect data to be sent over [0-49]. If the valid signal remains asserted during period window n + 2 (725), the sink device further expects to receive (and process) further data transmitted during the immediately subsequent period window n + 3 (730). be able to. On the other hand, in the example of FIG. 7, the valid signal is deasserted during the duration of the period window n + 2 (725), and no data is transmitted to the sink device during the period window n + 3 (730), and the data lane DATA [ 0-49] indicates that any bits detected on should be ignored during period window n + 3 (730).

  As indicated above, multiple valid lanes and strobe lanes can be maintained for each channel. This can help, among other advantages, maintain circuit simplicity and synchronization in a relatively long cluster of physical lanes connecting two devices. In some implementations, a set of data lanes can be divided into clusters of data lanes. For example, in the example of FIG. 7, the data lane DATA [0-49] can be divided into two clusters of 25 lanes, and each cluster can have a dedicated valid lane and strobe lane. For example, valid lane VALID1 can be associated with data lane DATA [0-24], and valid lane VALID2 can be associated with data lane DATA [25-49]. The signal in each “copy” of valid lanes and strobe lanes for each cluster may be the same.

  As introduced above, the data on the stream lane STREAM is used to indicate which protocol is applied to the corresponding data being transmitted on the data lane DATA [0-49] to the logical PHY on the receiving side. be able to. In the example of FIG. 7, a stream signal is transmitted on STREAM during the same period window as the data on data lane DATA [0-49] to indicate the protocol of the data on the data lane. In alternative implementations, the stream signal can be transmitted during the preceding period window, such as by using a corresponding valid signal, among other potential variations. On the other hand, if the example of FIG. 7 is continued, a protocol (for example, PCIe) applied to bits transmitted during the period window n + 1 (720) via the data lane DATA [0-49] during the period window n + 1 (720). , PCI, IDI, QPI, and the like) are transmitted. Similarly, during the subsequent period window n + 2 (725), another stream signal 740 is transmitted indicating the protocol applied to the bits transmitted during the period window n + 2 (725) via the data lane DATA [0-49]. The same applies hereinafter. In some cases, such as the example of FIG. 7 (both stream signals 735, 740 have the same encoding, binary FF), the continuous period windows (eg, n + 1 (720) and n + 2 (725)) belong to the same protocol Can do. On the other hand, in other cases, the data in the continuous period windows (eg, n + 1 (720) and n + 2 (725)) can come from different transactions to which different protocols are applied, and accordingly The signal (eg, 735, 740) can be encoded to identify different protocols that apply to consecutive data bytes on the data lane (eg, DATA [0-49]), among other examples.

  In some implementations, a low power state or idle state for MCPL may be defined. For example, when no device in the MCPL is transmitting data, the physical layer (electrical and logical) of the MCPL can go into an idle state or a low power state. For example, in the example of FIG. 7, in the period window n-2 (745), the MCPL is in a quiescent or idle state, and the strobe is disabled to save power. The MCPL can transition from the low power mode or the idle mode and wake the strobe in the period window n−1 (eg, 705). The strobe completes the transmit preamble (for example, to help wake and synchronize each of the channel lanes and the sink device) and initiates the strobe signal before any other signaling in other non-strobe lanes can do. As discussed above, following this period window n-1 (705), the valid signal is asserted in period window n (715) and the data arrives at the sink in the subsequent period window n + 1 (720). Can be notified.

  The MCPL may re-enter a low power state or idle state (eg, L1 state) following detection of an idle state in the MCPL channel's valid lane, data lane and / or other lanes. For example, there may be no signaling detected in the period window n + 3 (730) and progressing. Among other examples and principles (including those discussed later in this document), the logic in either the source device or sink device can initiate a transition back to a low power state, which again (eg, In the period window n + 5 (755)), the strobe will go idle in the power saving mode.

  The physical characteristics of the physical PHY include single-ended signaling, half-rate advanced clocking, interconnect channel and on-chip transport delay matching of transmitter (source) and receiver (sink), among other features, It may include one or more of optimized electrostatic discharge (ESD) protection, pad capacitance. Furthermore, MCPL can be implemented to achieve higher data rates (eg, reaching 16 Gb / s) and energy efficiency characteristics than conventional packaged I / O solutions.

  FIG. 8 shows a portion of a simplified block diagram 800 that represents a portion of an exemplary MCPL. The diagram 800 of FIG. 8 includes a representation of an exemplary lane 805 (eg, data lane, valid lane or stream lane) and clock generation logic 810. As shown in the example of FIG. 8, in some implementations, the clock generation logic 810 is for distributing the generated clock signal to each block that implements each lane of the exemplary MCPL, such as data lane 805. It can be implemented as a clock tree. Further, a clock recovery circuit 815 can be provided. In some implementations, as is customary in at least some conventional interconnect I / O architectures, rather than providing a separate clock recovery circuit for each lane where the clock signal is distributed, A single clock recovery circuit can be provided for each cluster. Indeed, when applied to the exemplary configurations of FIGS. 6 and 7, a separate strobe lane and associated clock recovery circuit can be provided for each cluster of 25 data lanes.

  Continuing with the example of FIG. 8, in some implementations, at least the data lane, stream lane, and valid lane can be terminated with an intermediate rail to a regulated voltage higher than zero (ground). In some implementations, the intermediate rail voltage can be adjusted to Vcc / 2. In some implementations, a single voltage regulator 825 can be provided for each cluster of lanes. For example, when applied to the examples of FIGS. 6 and 7, a first voltage regulator can be provided for a first cluster of 25 data lanes, among other potential examples, A second voltage regulator can be provided for the remaining clusters in the data lane. In some cases, the exemplary voltage regulator 825 can be implemented as a linear regulator, a switched capacitor circuit, among other examples. In some implementations, the linear regulator can be provided with an analog feedback loop or a digital feedback loop, among other examples.

  In some implementations, a crosstalk cancellation circuitry may be provided for the exemplary MCPL. In some cases, the compact nature of long MCPL wires can cause crosstalk interference between lanes. Crosstalk cancellation logic can be implemented to address these and other issues. For example, in one example shown in FIGS. 9-10, crosstalk can be significantly reduced using an exemplary low power active circuit such as those shown in FIGS. For example, in the example of FIG. 9, a weighted high-pass filtered “aggressor” signal can be added to a “victim” signal (ie, a signal subject to crosstalk interference from the aggressor). Each signal can be viewed as a crosstalk victim from each other's signal on the link and can itself be an aggressor for other signals, as long as this signal is a crosstalk interference source. Due to the derivative nature of crosstalk on the link, such a signal is generated, and crosstalk in victim lanes can be reduced by more than 50%. In the example of FIG. 9, a low-pass filtered aggressor signal can be generated through a high-pass RC filter (eg, implemented through C and R1). The high pass RC filter generates a filtered signal that is applied using a summing circuit 905 (eg, an RX sense amplifier).

  An embodiment similar to that described in the example of FIG. 9 may be a particularly advantageous solution for applications such as MCPL. This is because the circuit implementation can be realized with relatively low overhead, as shown in the diagram of FIG. 10 which shows an exemplary transistor level schematic of the circuit shown and described in the example of FIG. is there. The representations in FIGS. 9 and 10 are simplified representations, and the actual implementation is that multiple copies of the circuits shown in FIGS. 9 and 10 are used to accommodate the network of crosstalk interference between the lanes of the link Should be understood to include. As an example, among other examples, lane 0 to lane 1, lane 0 to lane 2, lane 1 to lane 0, lane 1 to lane 2, lane 2 to lane 0, lane 2 based on the shape and layout of the lane 3 to lane 1 can be provided which is similar to the one described in the examples of FIGS. 9 and 10 (eg, lanes 0 to 2).

  Additional features can be implemented at the physical PHY level of the exemplary MCPL. For example, in some cases, receiver offsets can cause significant errors and limit the I / O voltage margin. Circuit redundancy can be used to improve receiver sensitivity. In some implementations, circuit redundancy can be optimized to account for the standard deviation offset of the data sampler used in MCPL. For example, an exemplary data sampler designed for a three standard deviation offset specification can be provided. In the example of FIGS. 6 and 7, for example, if two data samplers are used for each receiver (eg, for each lane), 100 samplers are used for 50-lane MCPL. In this example, the probability that one of the receiver (RX) lanes will fail to specify 3 standard deviation offsets is 24%. To provide a chip reference voltage generator to set an upper offset and to move to the next data sampler at the receiver if another of the other data samplers is found to exceed this upper limit it can. On the other hand, if four data samplers are used per receiver (ie, instead of two in this example), the receiver will only fail if three of the four samplers fail. For a 50 lane MCPL as in the examples of FIGS. 6 and 7, this additional circuit redundancy can dramatically reduce the failure rate from 24% to less than 0.01%.

  In yet another example, at a very high data rate, bit-cycle duty cycle correction (DCC) and deskew can be used to extend the per-cluster cluster DCC and deskew to improve link margins. . Instead of performing corrections in all cases as in conventional solutions, some embodiments may utilize a low power digital implementation that detects and corrects outliers when an I / O lane fails. it can. For example, global tuning of lanes can be performed to identify problem lanes in the cluster. These problem lanes can then be subject to lane-by-lane tuning to achieve high data rates supported by MCPL.

  In some examples of MCPL, additional features that improve the performance characteristics of the physical link can also be implemented optionally. For example, line coding can be provided. An intermediate rail termination as described above can allow DC data bus inversion (DBI) to be omitted, but AC DBI can still be used to reduce dynamic power. Among other illustrative benefits, more complex coding is used to eliminate the worst case 1 and 0 differences, for example, reducing intermediate rail regulator drive requirements and limiting I / O switching noise You can also Furthermore, transmitter equalization can optionally be implemented. For example, at very high data rates, insertion loss can be significant for in-package channels. Among other things, 2-tap weight transmitter equalization (eg, performed during the initial startup sequence) may be sufficient to alleviate some of these problems in some cases.

  Referring to FIG. 11, a simplified block diagram 1100 illustrating an example logical PHY of an example MCPL is shown. The physical PHY 1105 may be connected to a die that includes a logical PHY 1110 and additional logic that supports the MCPL link layer. The die may further include logic that, in this example, supports multiple different protocols in MCPL. For example, in the example of FIG. 11, PCIe logic 1115 can be provided along with IDI logic 1120, thereby including a potential to include more than two protocols or protocols other than PCIe and IDI are supported via MCPL. In particular, among many other examples, dies can communicate using PCIe or IDI over the same MCPL connecting the two dies. Different protocols supported between dies can provide different levels of services and features.

  The logical PHY 1110 may include link state machine management logic 1125 for negotiating link state transitions in connection with die higher layer logic requests (eg, received via PCIe or IDI). The logic PHY 1110 may further include link test and debug logic (eg, 1130) in some implementations. As shown above, the exemplary MCPL is a die-to-die via MCPL that facilitates the MCPL's protocol-agnostic (among other exemplary features), high performance, power efficient features. The transmitted control signal can be supported. For example, the logical PHY 1110 generates, transmits, receives and processes valid signals, stream signals and LSM sideband signals in connection with transmitting and receiving data via dedicated data lanes as described in the above example. Can support.

  In some implementations, multiplexing (eg, 1135) and demultiplexing (eg, 1140) logic can be included in logical PHY 1110 or otherwise accessible to logical PHY 1110. For example, multiplexing logic (eg, 1135) can be used to identify data (eg, embodied as packets, messages, etc.) transmitted on the MCPL. Multiplexing logic 1135 identifies the protocol that governs the data and generates a stream signal. This stream signal is encoded to specify the protocol. For example, in one exemplary implementation, a stream signal can be encoded as two hexadecimal symbol bytes (eg, IDI: FFh, PCIe: F0h, LLP: AAh, sideband: 55h, etc.) It can be transmitted during the same window of data governed by the specified protocol (eg, a byte duration window). Similarly, demultiplexing logic 1140 can be used to interpret the incoming stream signal and decode the stream signal to identify the protocol to apply to the data currently received by the stream signal on the data lane. The demultiplexing logic 1140 can then be applied (or reserved) to protocol specific link layer processing to cause the data to be processed by the corresponding protocol logic (eg, PCIe logic 1115 or IDI logic 1120).

  The logical PHY 1110 can further include link layer packet logic 1150 that can be used to handle various link control functions including power management tasks, loopback, disable, re-centering, scrambling and the like. LLP logic 1150 can facilitate link layer messages via MCLP, among other functions. Data corresponding to LLP signaling can also be identified by a stream signal transmitted on a dedicated stream signal lane that is encoded to identify data lane LLP data. Multiplexing and demultiplexing logic (eg, 1135, 1140) is used to generate and interpret stream signals corresponding to LLP traffic, and such traffic is processed by appropriate die logic (eg, LLP logic 1150). It can also be made. Similarly, some implementations of MCLP may include dedicated sidebands (eg, sideband 1155 and support logic) such as asynchronous and / or low frequency sideband channels, among other examples.

  The logical PHY logic 1110 can further include link state machine management logic that can generate and receive (and use) link state management messages via a dedicated LSM sideband lane. For example, among other potential examples, a handshake can be performed using the LSM sideband lane to advance the link training state and exit the power management state (eg, L1 state). Among other examples, LSM sideband signals can be asynchronous signals in that they are not aligned with link data signals, valid signals and stream signals, but instead correspond to signaling state transitions. A link state machine between two connected dies or chips can be aligned. Among other illustrative advantages, in some instances, providing a dedicated LSM sideband lane allows the analog front end (AFE) conventional squelch and receive detection circuitry to be eliminated.

  Referring to FIG. 12, a simplified block diagram 1200 showing another representation of the logic used to implement MCPL is shown. For example, the logical PHY 1110 is provided with a defined logical PHY interface (LPIF) 1205 through which a plurality of different protocols (eg, PCIe, IDI, QPI, etc.) 1210, 1215, 1220, 1225 and signaling modes (eg, , Sideband) can interface with the physical layer of the exemplary MCPL. In some implementations, multiplexing and arbitration logic 1230 may be provided as a separate layer from logical PHY 1110. In one example, LPIF 1205 can be provided as an interface on either side of this MuxArb layer 1230. The logical PHY 1110 may interface with a physical PHY (eg, an analog front end (AFE) 1105 of the MCPL PHY) through another interface.

  The LPIF can extract PHY (logic and electrical / analog) from higher layers (eg, 1210, 1215, 1220, 1225), thereby allowing completely different PHYs to be under LPIF transparent to higher layers. Can be implemented. This helps to promote modularity and design reuse, because, among other examples, higher layers can remain intact when the underlying signaling technology PHY is updated. Can do. In addition, the LPIF can define multiple signals that enable logical PHY multiplexing / demultiplexing, LSM management, error detection and processing, and other functions. For example, Table 1 summarizes at least a portion of the signals that can be defined for an exemplary LPIF.

  As shown in Table 1, in some implementations, an alignment mechanism can be provided through an AlignReq / AlignAck handshake. For example, some protocols may lose packet framing when the physical layer enters recovery. Packet alignment can be corrected to ensure correct framing identification by, for example, the link layer. Further, as shown in FIG. 13, the physical layer can assert the StallReq signal when entering recovery, so that the link layer is ready to transfer the newly aligned packet. Assert signal. Physical layer logic can sample both Stall and Valid to determine if the packet is aligned. For example, the physical layer drives trdy until Stall and Valid are sampled and asserted, among other potential implementations, including other alternative implementations that support packet alignment using Valid. Can continue to drain link layer packets.

  Various fault tolerances can be defined for signals in MCPL. For example, fault tolerance can be defined for valid signals, stream signals, LSM sideband signals, low frequency sideband signals, link layer packet signals, and other types of signals. The resiliency of packets, messages and other data transmitted over the MCPL dedicated data lanes can be based on the specific protocol governing the data. In some implementations, among other potential examples, error detection and processing mechanisms such as cyclic redundancy check (CRC), retry buffers, etc. may be provided. As an example, for PCIe packets sent over MCPL, a 32-bit CRC can be utilized for PCIe transaction layer packets (TLPs) (delivery is guaranteed (eg, through a replay mechanism)) and the PCIe link A 16-bit CRC may be utilized for layer packets (which may be constructed to be lossy (eg, no replay is applied)). Further, for PCIe framing tokens, among other examples, a specific hamming distance (eg, hamming distance 4) can be defined for the token identifier, and parity and 4-bit CRC can also be utilized. On the other hand, in the case of an IDI packet, a 16-bit CRC can be used.

  In some embodiments, fault tolerance including requiring the valid signal to transition from low to high (ie, from 0 to 1) (eg, to help ensure bit and symbol lock). Can be defined for link layer packets (LLP). In addition, among the many defined features that can be used as a basis for determining faults in LLP data on the MCPL, in one example, defining a specific number of consecutive identical LLPs to be transmitted. And a response to each request can be expected, and the request side retries after a response timeout. In a further example, providing fault tolerance for a valid signal, for example, by extending the valid signal or symbol across the period window (eg, by keeping the valid signal high for eight UIs). it can. Further, errors or failures in the stream signal can be prevented by maintaining the Hamming distance of the encoded value of the stream signal, among other examples.

  The implementation of the logic PHY can include error detection, error reporting, and error handling logic. In some implementations, an exemplary MCPL logical PHY includes, among other examples, PHY layer deframing errors (eg, on valid lanes and stream lanes), sideband errors (eg, for LSM state transitions), Logic may be included to detect errors in the LLP (eg, important for LSM state transitions). Among other examples, some error detection / resolution can be delegated to higher layer logic such as PCIe logic adapted to detect PCIe specific errors.

  In the case of a deframing error, some implementations may provide one or more mechanisms through error handling logic. Deframing errors can be handled based on the protocol involved. For example, in some implementations, the link layer can be notified of an error to trigger a retry. Deframing can also cause realignment of logical PHY deframing. In addition, among other techniques, logical PHY re-centering can be performed and symbol / window locks can be reacquired. In some examples, centering can include the PHY moving the receiver clock phase to an optimal point in order to detect incoming data. In this context, “optimal” can refer to the location with the largest margin for noise and clock jitter. Re-centering can include, for example, a simplified centering function that is performed, for example, when the PHY wakes up from a low power state.

  Other types of errors can include other error handling techniques. For example, errors detected in the sideband can be captured through a corresponding state (eg, LSM) timeout mechanism. An error can be logged and the link state machine can then transition to Reset. The LSM can stay in Reset until a restart command is received from the software. In another example, LLP errors, such as link control packet errors, can be handled using a timeout mechanism that can restart the LLP sequence if no acknowledgment for the LLP sequence is received.

  14A-14C illustrate exemplary bit mapping representations in exemplary MCPL data lanes for various types of data. For example, an exemplary MCPL can include 50 data lanes. FIG. 14A shows a first bit mapping of an exemplary 16 byte slot in a first protocol such as IDI that can be transmitted over a data lane in an 8 UI symbol or window. For example, three 16-byte slots including header slots can be transmitted within a defined 8 UI window. In this example, two bytes of data remain, and these two remaining bytes can be used for CRC bits (for example, in lanes DATA [48] and DATA [49]).

  In another example, FIG. 14B shows a second example bit mapping for PCIe packet data transmitted over 50 data lanes of the example MCPL. In the example of FIG. 14B, a 16-byte packet (eg, transaction layer (TLP) or data link layer (DLLP) PCIe packet) can be transmitted via MCPL. In the 8UI window, three packets can be transmitted, and the remaining 2 bytes of bandwidth remain unused within the window. These symbols can include framing tokens and can be used to locate the start and end of each packet. In one example of PCIe, the framing utilized in the example of FIG. 14B can be the same as a token etc. implemented for PCIe at 8 GT / s.

  In yet another example shown in FIG. 14C, an exemplary bit mapping of an interlink packet (eg, an LLP packet) transmitted via an exemplary MCPL is shown. Each LLP can be 4 bytes, and each LLP (eg, LLP0, LLP1, LLP2, etc.) can be sent four times in succession according to fault tolerance and error detection in an exemplary implementation. For example, failure to receive four consecutive identical LLPs can indicate an error. Further, for other data types, failure to receive a VALID in an ongoing time window or symbol can also indicate an error. In some cases, the LLP can have a fixed slot. Further, among other examples, in this example, an unused or “spare” bit in the byte period results in a logical 0 transmitted over two of the 50 lanes (eg, DATA [48-49]). Will be.

  Referring to FIG. 15, a simplified link state machine transition diagram 1400 is shown with sideband handshaking utilized between state transitions. For example, Reset. The Idle state (e.g., in this state, phase lock loop (PLL) lock calibration is performed) is reset through the sideband handshake. A transition can be made to the Cal state (eg, in this state the link is further calibrated). Reset. Cal uses Reset.com through the sideband handshake. A transition can be made to the ClockDCC state (eg, in this state, duty cycle correction (DCC) and delay lock looping (DLL) lock can be performed). Reset. From ClockDCC, Reset. Additional handshaking can be performed to transition to the Quiet state (eg, deassert the valid signal). To assist in the alignment of signaling on the MCPL lane, Center. Lanes can be centered through the Pattern state.

  In some implementations, as shown in the example of FIG. During the Pattern state, the transmitter can generate a training pattern or other data. The receiver can adjust its receiver circuit to receive such a training pattern, for example, by setting the phase interpolator position and the vref position and setting the comparator. The receiver can continue to compare the received pattern with the predicted pattern and store the result in a register. After a set of patterns is completed, the receiver can increment the phase interpolator settings while keeping vref the same. The test pattern generation and comparison process can continue, new comparison results can be stored in registers, and the procedure steps through all phase interpolator values and all vref values iteratively. Once the pattern generation and comparison process is complete, Center. A Quiet state can be entered. Center. Following centering of the lanes through the Pattern and CenterQuiet link states, link. It is possible to transition to the Init state, initialize the MCPL, and enable data transmission in the MCPL.

  Returning temporarily to the discussion of FIG. 15, sideband handshaking can be used to facilitate link state machine transitions between dies or chips in a multi-chip package, as indicated above. For example, signals in the MCPL LSM sideband lane can be used to synchronize state machine transitions across dies. For example, when conditions exiting a state (eg Reset.Idle) are met, the side that met these conditions will assert an LSM sideband signal in its outbound LSM_SB lane, and the other remote die will And wait to assert the LSM sideband signal in the LSM_SB lane of that die. When both LSM_SB signals are asserted, the link state machine of each respective die can transition to the next state (eg, Reset.Cal state). A minimum overlap time can be defined that should remain asserted before both LSM_SB signals transition state. In addition, a minimum quiesce time can be defined to allow accurate turnaround detection after LSM_SB is deasserted. In some implementations, all link state machine transitions are conditional on such an LSM_SB handshake and may be facilitated by such an LSM_SB handshake.

  FIG. 17 is a more detailed link state machine diagram 1700 illustrating at least some of the additional link states and link state transitions that can be included in an exemplary MCPL. In some implementations, an exemplary link state machine may include a “Directed Loopback” transition, among the numerous states and state transitions shown in FIG. Lanes can be provided to be digital loopbacks. For example, the MCPL receiver lane can loop back to the transmitter lane after the clock recovery circuit. In some cases, an “LB_Recenter” state can also be provided. This state can be used to align data symbols. Further, as shown in FIG. 15, MCPL can support multiple link states including active L0 state and low power state, such as L1 idle state and L2 sleep state, among other potential examples. .

  FIG. 18 is a simplified block diagram 1800 illustrating an exemplary flow of transitions between an active state (eg, L0) and low power and an idle state (eg, L1). In this particular example, first device 1805 and second device 1810 are communicatively coupled using MCPL. While in the active state, data is transmitted over MCPL lanes (eg, DATA, VALID, STREAM, etc.). A link layer packet (LLP) can be communicated over a lane (eg, a data lane, and a stream signal indicates that the data is LLP data) to help facilitate link state transitions. For example, an LLP can be sent between the first device 1805 and the second device 1810 to negotiate an entry from L0 to L1. For example, an upper layer protocol supported by MCPL can communicate that an entry into L1 (or another state) is desirable, and this upper layer protocol uses LLP to cause the physical layer to enter L1. Can be transmitted via MCPL to facilitate link layer handshaking. For example, FIG. 18 illustrates at least a portion of a transmitted LLP, including a “enter L1” request LLP transmitted from a second (upstream) device 1810 to a first (downstream) device 1805. In some implementations and higher level protocols, the downstream port does not initiate entry to L1. Among other examples, the first device 1805 on the receiving side can send a “change to L1” request LLP upon response, and the second device 1810 can send this response to the “change to L1” confirmation response. (ACK) Acknowledgment can be made through LLP. Upon detecting the completion of the handshake, the logical PHY causes the sideband signal to be asserted on the dedicated sideband link, the ACK has been received, and the device (eg, 1805) is ready to enter L1. Acknowledge that it is done and expects it. For example, the first device 1805 can assert a sideband signal 1815 transmitted to the second device 1810 to confirm receipt of the final ACK in the link layer handshake. Further, the second device 1810 can also assert the sideband signal in response to the sideband signal 1815 and notify the first device 1805 of the sideband ACK 1805 of the first device. Upon completion of the link layer control and sideband handshake, the MCPL PHY can transition to the L1 state, which causes all lanes of the MCPL to be idle, including the respective MCPL strobes of the devices 1805, 1810 1820, 1825. Enter power saving mode. For example, in response to detecting data sent to another device via MCPL, one of the upper level logic of one of the first device 1805 and the second device 1810 requests re-entry to L0. , You can exit L1.

  As indicated above, in some implementations, the MCPL can facilitate communication between two devices that potentially support multiple different protocols, and the MCPL can communicate with multiple lanes of MCPL. Communication with potentially any one of the protocols can be facilitated. On the other hand, facilitating multiple protocols can complicate entry and re-entry into at least some link states. For example, some conventional interconnects have a single upper layer that assumes the role of the master in state transitions, whereas MCPL implementations with multiple different protocols involve multiple masters in effect. As an example, as shown in FIG. 18, each of PCIe and IDI can be supported between two devices 1805 and 1810 by implementing MCPL. For example, putting the physical layer into an idle or low power state can be contingent on the permissions initially obtained from each of the supported protocols (eg, both PCIe and IDI).

  In some cases, entry to L1 (or another state) can be requested by only one of a plurality of supported protocols supported for MCPL implementation. Although other protocols may request entries to the same state as well (eg, based on identifying similar conditions in MCPL (eg, little or no traffic)), the logical PHY is It can wait until a permission or command is received from each higher layer protocol before actually facilitating the state transition. The logical PHY keeps track of which upper layer protocol has requested a state change (eg, performed a corresponding handshake), and each of the protocols is in the transition from L0 to L1 or other protocol communication. Specifying that a particular state change has been requested, such as another transition that affects or interferes, can trigger a state transition. In some implementations, the protocol may be unaware of its at least partial dependencies on other protocols in the system. Further, in some cases, the protocol may expect a response (eg, from the PHY) to a request that enters a particular state, such as confirmation or rejection of the requested state transition. Thus, in such a case, while waiting for permission from another supported protocol for entry into the idle link state, the logical PHY generates a composite response for the request to enter the idle state, and the requesting upper layer protocol. Can be fooled into believing that a particular state has been entered (in fact, at least until other protocols also request entry into the idle state) . Among other potential benefits, this can simplify the coordination of entries to low power states among multiple protocols, among other examples.

  The apparatus, methods, and systems described above can be implemented in any electronic device or system as described above. As a specific example, the following figures provide an exemplary system utilizing the present invention as described herein. Although the following system is described in more detail, from the above discussion, a number of different interconnects are disclosed, described, and modified. As will be readily apparent, the advantages described above can be applied to any of these interconnects, fabrics or architectures.

  Referring to FIG. 19, one embodiment of a block diagram for a computing system that includes a multi-core processor is shown. The processor 1900 may be any processor or process such as a microprocessor, embedded processor, digital signal processor (DSP), network processor, handheld processor, application processor, coprocessor, system on chip (SOC) or other device executing code. Includes devices. In one embodiment, the processor 1900 includes at least two cores, cores 1901 and 1902. This can include an asymmetric core or a symmetric core (shown embodiment). On the other hand, the processor 1900 may include any number of processing elements that may be symmetric or asymmetric.

  In one embodiment, a processing element refers to hardware or logic that supports software threads. Examples of hardware processing elements hold thread state, thread slot, thread, process unit, context, context unit, logical processor, hardware thread, core, and / or processor state such as execution state or structural state Including any other elements that can be done. In other words, in one embodiment, a processing element refers to any hardware that can be independently associated with code, such as a software thread, operating system, application or other code. A physical processor (or processor socket) typically refers to an integrated circuit that includes potentially any number of other processing elements, such as cores or hardware threads.

  A core often refers to logic located on an integrated circuit that can maintain an independent structural state. Each structural state that is maintained independently is associated with at least some dedicated execution resources. In contrast to the core, a hardware thread usually refers to any logic located on an integrated circuit capable of maintaining an independent structural state, which is independently transferred to an execution resource. Share access. As can be seen, when certain resources are shared and other resources are dedicated to the structural state, the lines between the hardware thread and core terms overlap. More often, the core and hardware threads are considered by the operating system as individual logical processors, where the operating system can schedule operations individually in each logical processor.

  As shown in FIG. 19, the physical processor 1900 includes two cores, cores 1901 and 1902. Here, cores 1901 and 1902 are considered symmetric cores, i.e. cores having the same configuration, functional units and / or logic. In another embodiment, core 1901 includes an out-of-order processor core, whereas core 1902 includes an in-order processor core. On the other hand, the cores 1901 and 1902 execute a native core, a software management core, a core adapted to execute a native instruction set architecture (ISA), a translated instruction set architecture (ISA). It can be individually selected from any type of core, such as adapted cores, co-designed cores, or other known cores. In a heterogeneous core environment (ie, an asymmetric core), some form of transformation, such as binary transformation, can be utilized to schedule or execute code in one or both cores. Further discussion will be made and the functional unit shown in core 1901 will be described in more detail below, and the units in core 1902 will operate similarly in the embodiment shown.

  As shown, core 1901 includes two hardware threads 1901a and 1901b, sometimes referred to as hardware thread slots 1901a and 1901b. Thus, in one embodiment, a software entity, such as an operating system, potentially has processor 1900 running on four separate processors, ie four logical processors or processing elements capable of executing four software threads simultaneously. It is considered. As suggested above, the first thread can be associated with the architectural state register 1901a, the second thread can be associated with the architectural state register 1901b, the third thread can be associated with the architectural state register 1902a, Four threads can be associated with the architecture status register 1902b. Here, as described above, each of the architecture status registers (1901a, 1901b, 1902a and 1902b) can be referred to as a processing element, thread slot or thread unit. As shown, architectural state register 1901a is duplicated in architectural state register 1901b so that individual architectural states / contexts can be stored for logical processor 1901a and logical processor 1901b. In core 1901, other smaller resources such as instruction pointers and rename logic in allocator and renamer block 1930 can also be replicated for threads 1901a and 1901b. Several resources such as reorder buffers, ILTB 1920, load / store buffers and queues in the reorder / retirement unit 1935 can be shared through partitioning. Other resources such as general internal registers, page table base registers, low level data cache and data TLB 1915, execution unit 1940, and out-of-order unit 1935 portions are potentially fully shared.

  The processor 1900 often includes other resources, which can be fully shared, shared through partitioning, or dedicated to / by processing elements. In FIG. 19, one embodiment of a mere exemplary processor with exemplary logical units / resources of the processor is shown. Note that the processor may include or omit any of these functional units, and may include any other known functional units, logic or firmware not shown. As shown, core 1901 includes a simplified, typical out-of-order (OOO) processor core. However, in-order processors can be utilized in various embodiments. The OOO core includes a branch target buffer 1920 that predicts the branch to be executed / acquired, and an instruction translation buffer (I-TLB) 1920 that stores an address translation entry of the instruction.

  Core 1901 further includes a decode module 1925 coupled to fetch unit 1920 to decode the fetched elements. The fetch logic, in one embodiment, includes individual sequencers associated with thread slots 1901a, 1901b, respectively. Typically, core 1901 is associated with the first ISA. The first ISA defines / specifies instructions that can be executed on the processor 1900. Machine code instructions that are part of the first ISA often include a portion of the instruction (referred to as opcode) that references / specifies the instruction or action to be performed. The decode logic 1925 includes circuitry that recognizes these instructions from the opcode and passes the decoded instructions through a pipeline for processing as defined by the first ISA. For example, as discussed in more detail below, decoder 1925 includes logic designed or adapted to recognize specific instructions, such as transaction instructions, in one embodiment. As a result of recognition by decoder 1925, architecture or core 1901 performs certain predetermined actions to perform the tasks associated with the appropriate instructions. It is important to note that any of the tasks, blocks, operations and methods described herein can be performed in response to a single or multiple instructions. Some of those instructions may be new or old instructions. Note that decoder 1926 recognizes the same ISA (or a subset thereof) in one embodiment. Alternatively, in a heterogeneous core environment, decoder 1926 recognizes a second ISA (a subset of the first ISA or a separate ISA).

  In one example, the allocator or renamer block 1930 includes an allocator for reserving resources, such as a register file that stores instruction processing results. On the other hand, threads 1901a and 1901b are potentially capable of out-of-order execution, in which case the allocator and renamer block 1930 also reserve other resources such as a reorder buffer for tracking instruction results. Unit 1930 also includes a register renamer that renames program / instruction reference registers for other registers within processor 1900. The reorder / retirement unit 1935 includes components such as the reorder buffer, load buffer, and store buffer described above to support out-of-order execution and subsequent in-order retirement of out-of-order executed instructions.

  The scheduler and execution unit block 1940, in one embodiment, includes a scheduler unit that schedules instructions / operations on the execution unit. For example, floating point instructions are scheduled on a port of an execution unit that has an available floating point execution unit. A register file associated with the execution unit is also included for storing information instruction processing results. Exemplary execution units include a floating point execution unit, an integer execution unit, a jump execution unit, a load execution unit, a store execution unit, and other known execution units.

  A low level data cache and data conversion buffer (D-TLB) 1950 is coupled to the execution unit 1940. The data cache is for storing recently used / operated elements such as data operands that are potentially held in memory coherency state. The D-TLB is for storing recent virtual / linear to physical address translation. As a specific example, the processor may include a page table structure that divides physical memory into multiple virtual pages.

  Here, cores 1901 and 1902 share access to higher level or even outer caches such as second level caches associated with on-chip interface 1910. Note that higher or further outside refers to the cache level increasing or leaving the execution unit. In one embodiment, the higher level cache is a last level data cache, such as a second or third level data cache, ie, the last cache in the memory hierarchy in the processor 1900. On the other hand, higher level caches are not so limited. This is because this cache can be associated with or include an instruction cache. Alternatively, one type of trace cache, or instruction cache, can be combined after the decoder 1925 stores the recently decoded trace. Here, an instruction potentially refers to a macro instruction (ie, a general instruction recognized by a decoder). The macro instruction can be decoded into a plurality of micro instructions (micro operations).

  In the configuration shown, the processor 1900 also includes an on-chip interface module 1910. Traditionally, a memory controller, described in more detail below, has been included in a computing system external to processor 1900. In this scenario, the on-chip interface 1910 includes a system memory 1975, a chipset (often including a memory controller hub for connecting to the memory 1975 and an I / O controller hub for connecting to peripheral devices), a memory controller. For communication with devices external to the processor 1900, such as a hub, north bridge or other integrated circuit. And in this scenario, bus 1905 can be any known, such as multi-drop bus, point-to-point interconnect, serial interconnect, parallel bus, coherent (eg, cache coherent) bus, layered protocol architecture, differential bus, and GTL bus. Interconnects can be included.

  Memory 1975 can be dedicated to processor 1900 or can be shared with other devices in the system. Common examples of types of memory 1975 include DRAM, SRAM, non-volatile memory (NV memory) and other known storage devices. Device 1980 includes a graphics accelerator, a processor or card coupled to a memory controller hub, data storage coupled to an I / O controller hub, a wireless transceiver, a flash device, an audio controller, a network controller or other known device. Note that you can.

  On the other hand, since more logic and devices have recently been integrated on a single die, such as an SOC, each of these devices can be incorporated on the processor 1900. For example, in one embodiment, the memory controller hub is on the same package and / or die as the processor 1900. Here, a portion of the core (on-core portion) 1910 includes one or more controllers for interfacing with other devices such as memory 1975 or graphics device 1980. Configurations that include interconnects and controllers for interfacing with such devices are often referred to as on-core (or uncore configurations). By way of example, the on-chip interface 1910 includes a ring interconnect for on-chip communication and a high-speed serial point-to-point link 1905 for off-chip communication. However, in an SOC environment, more devices such as a network interface, coprocessor, memory 1975, graphics processor 1980, and any other known computer device / interface are integrated on a single die or integrated circuit to provide high functionality. Can provide a small form factor with low power consumption.

  In one embodiment, the processor 1900 executes compiler, optimization and / or converter code 1977 to provide application code 1976 to support the devices and methods described herein and interfaces therewith. It can be compiled, transformed and / or optimized. Compilers often include a program or set of programs that convert source text / code into target text / code. Typically, compiling program / application code with a compiler is done in multiple phases and passes, converting high-level programming language code into low-level machine or assembly language code. However, single pass compilers may still be used for simple compilation. The compiler can use any known compilation technique to perform any known compiler operations such as lexical analysis, preprocessing, parsing, semantic analysis, code generation, code conversion, and code optimization.

  Larger compilers often include multiple phases, but most often these phases are roughly two phases: (1) the front end, ie usually syntax processing, semantic processing and Included in where several transformations / optimizations can be performed and (2) the backend, ie, where analysis, transformation, optimization and code generation are performed. Some compilers refer to the middle, which indicates that the boundary between the compiler front end and back end is ambiguous. As a result, compiler insertions, associations, generations, or other behavior references can be made in any of the phases or paths described above, and in any other known phase or path of the compiler. As an illustrative example, the compiler potentially inserts actions, calls, functions, etc. in one or more phases of compilation, such as inserting calls / actions in the front end phase of compilation, and then during the transformation phase Convert call / motion to lower level code. Note that during dynamic compilation, compiler code or dynamically optimized code can insert such operations / calls to optimize the code for execution during runtime. As a specific example for illustration, binary code (already compiled code) can be dynamically optimized during runtime. Here, the program code may include dynamic optimization code, binary code, or a combination thereof.

  Similar to a compiler, a converter, such as a binary converter, converts code statically or dynamically to optimize and / or convert the code. Thus, references to the execution of code, application code, program code or other software environment are: (1) whether the compiler program, optimizing code optimizer or translator is executed dynamically or statically to compile the program code Maintain software structure, perform other operations, optimize code or convert code, (2) main program code including operations / calls such as optimized / compiled application code (3) Run other program code, such as a library associated with the main program code, to maintain the software structure, perform other software-related operations, or optimize the code Or (4) a combination thereof .

  Referring to FIG. 20, a block diagram of one embodiment of a multi-core processor is shown. As shown in the embodiment of FIG. 20, the processor 2000 includes multiple regions. In particular, the core domain 2030 includes a plurality of cores 2030A-2030N, and the graphics domain 2060 includes one or more graphics engines having a media engine 2065 and a system agent domain 2010.

  In various embodiments, the system agent domain 2010 allows individual units (eg, cores and / or graphic engines) in domains 2030 and 2060 to take into account the activity (or inactivity) that occurs in a given unit. To be independently controllable to operate dynamically in the appropriate power mode / level (eg, states such as active, turbo, sleep, hibernate, deep sleep, or other evolved configuration power interfaces) Handle power control events and power management. Each of domains 2030 and 2060 can operate at different voltages and / or powers, and each individual unit in the domain operates at a potentially independent frequency and voltage, respectively. It should be noted that although only three domains are shown, the scope of the invention is not limited in this regard, and additional domains may exist in other embodiments.

  As shown, each core 2030 further includes a low level cache in addition to various execution units and additional processing elements. Here, the various cores are coupled together and coupled to a shared cache memory formed from multiple units or slices of last level caches (LLCs) 2040A-2040N. These LLCs often include storage and cache controller functions and are shared between cores and potentially shared between graphic engines.

  As shown, the ring interconnect 2050 couples the cores together, with a core domain 2030 and a graphics domain 2060 via a plurality of ring locks 2052A-2052N, each at the junction between the core and the LLC slice. And the system agent circuit unit 2010 are provided. As shown in FIG. 20, the interconnect 2050 is used to carry various information including address information, data information, acknowledgment information and snoop / invalid information. Although a ring interconnect is shown, any known on-die interconnect or fabric can be utilized. As an illustrative example, some of the fabrics discussed above (eg, another on-die interconnect, on-chip system fabric (OSF), evolved microcontroller bus architecture (AMBA) interconnect, multi-dimensional mesh fabric or Other known interconnect architectures) can be used as well.

  As further shown, the system agent domain 2010 includes a display engine 2012 for providing control of the associated display and an interface to this display. The system agent domain 2010 may include other units such as an integrated memory controller 2020 that provides an interface to system memory (eg, DRAM with multiple DIMMs, coherence logic 2022 that performs memory coherence operations). There can be multiple interfaces to allow interconnection between the processor and other circuitry. For example, in one embodiment, at least one direct media interface (DMI) 2016 interface and one or more PCIe ™ interfaces 2014 are provided. Display engines and their interfaces are typically coupled to memory via a PCIe ™ bridge 2018. Still further, one or more other interfaces can be provided to provide communication between other agents, such as additional processors or other circuitry.

  Referring now to FIG. 21, a block diagram of a representative core is shown, particularly a core back-end logic block such as core 2030 from FIG. In general, the structure shown in FIG. 21 includes an out-of-order processor having a front-end unit 2170. This front end unit 2170 is used to fetch incoming instructions, perform various processing (eg, cache, decode, branch prediction, etc.) and pass instructions / actions along an out-of-order (OOO) engine 2180. It is done. The OOO engine 2180 performs further processing on the decoded instruction.

  In particular, in the embodiment of FIG. 21, the out-of-order engine 2180 receives decoded instructions, which can take the form of one or more microinstructions or μops, from the front end unit 2170 and stores them in registers, etc. Allocation unit 2182 that allocates to the appropriate resources. The instructions are then provided to a reservation station 2184 that reserves resources and schedules these resources for execution in one of a plurality of execution units 2186A-2186N. For example, there can be various types of execution units including an arithmetic logic unit (ALU), a load and store unit, a vector processing unit (VPU), and a floating point execution unit, among others. Results from these different execution units can be provided to a reorder buffer (ROB) 2188. ROB 2188 takes unordered results and returns these results to correct the program order.

  Still referring to FIG. 21, it should be noted that both front end unit 2170 and out-of-order engine 2180 are coupled to different levels of the memory hierarchy. Specifically shown is an instruction level cache 2172, which is coupled to an intermediate level cache 2176, which is coupled to a final level cache 2195. In one embodiment, final level cache 2195 is implemented in on-chip (sometimes referred to as uncore) unit 2190. By way of example, unit 2190 is similar to system agent 2010 of FIG. As discussed above, the uncore 2190 communicates with the system memory 2199, which in the illustrated embodiment is implemented via ED RAM. Note also that the various execution units 2186 in the out-of-order engine 2180 communicate with a first level cache 2174 that also communicates with the intermediate level cache 2176. Note also that additional cores 2130N-2 to 2130N can be coupled to LLC 2195. Although shown at this high level in the embodiment of FIG. 21, it should be understood that various alternative and additional components may exist.

  Referring to FIG. 22, a block diagram of an exemplary computer system formed using a processor including an execution unit that executes instructions is shown. Here, one or more of the interconnects implement one or more features according to one embodiment of the invention. System 2200 comprises components, such as processor 2202, that employ execution units that include logic to execute algorithms for processing data in accordance with the present invention, as in the embodiments described herein. System 2200 represents a processing system based on PENTIUM (TM) III, PENTIUM (TM) 4, Xeon (TM), Itanium, XScale (TM) and / or StrongARM (TM) microprocessors, but other systems (others) Other microprocessors, engineering workstations, PCs with set-top boxes, etc.). In one embodiment, the sample system 2200 runs a version of the WINDOWS® operating system available from Microsoft Corporation of Redmond, WA, but other operating systems (eg, UNIX® and Linux ( Registered software), embedded software, and / or a graphical user interface may also be used. Thus, embodiments of the invention are not limited to any specific combination of hardware circuitry and software.

  Embodiments are not limited to computer systems. Alternative embodiments of the present invention can be used in other devices such as handheld devices and embedded applications. Some examples of handheld devices include mobile phones, internet protocol devices, digital cameras, personal digital assistants (PDAs), and handheld PCs. The embedded application may be a microcontroller, digital signal processor (DSP), system on chip, network computer (NetPC), set top box, network hub, wide area network (WAN) switch, or one or more according to at least one embodiment Any other system capable of executing the instructions may be included.

  In the described embodiment, processor 2202 includes one or more execution units 2208 that implement algorithms that execute at least one instruction. One embodiment may be described in the context of a single processor desktop or server system, although alternative embodiments may be included in a multiprocessor system. System 2200 is an example of a “hub” system architecture. Computer system 2200 includes a processor 2202 that processes data signals. The processor 2202 includes, as an illustrative example, a compound instruction set computer (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, an instruction It includes a processor that implements the set combination, or any other processor device such as a digital signal processor. The processor 2202 is coupled to a processor bus 2210 that transmits data signals between the processor 2202 and other components in the system 2200. Elements of system 2200 (eg, graphics accelerator 2212, memory controller hub 2216, memory 2220, I / O controller hub 2224, wireless transceiver 2226, flash BIOS 2228, network controller 2234, audio controller 2236, serial expansion port 2238, I / O A controller 2240, etc.) performs conventional functions well known to those skilled in the art.

  In one embodiment, the processor 2202 includes a level 1 (L1) internal cache memory 2204. Depending on the architecture, the processor 2202 may have a single internal cache or multiple levels of internal cache. Other embodiments include a combination of both internal and external caches, depending on the particular implementation and demand. Register file 2206 is for storing various types of data in various registers including integer registers, floating point registers, vector registers, bank registers, shadow registers, checkpoint registers, status registers and instruction pointer registers. .

  There is also an execution unit 2208 in the processor 2202 that includes logic for performing integer and floating point operations. The processor 2202, in one embodiment, includes a microcode (μcode) ROM for storing microcode. When executed, this microcode executes an algorithm for a microinstruction or handles complex scenarios. Here, the microcode can potentially be updated to handle logic bugs / fixes for the processor 2202. For one embodiment, execution unit 2208 includes logic for processing packed instruction set 2209. By including the packed instruction set 2209 in the general processor 2202 instruction set with associated circuitry for executing the instructions, the operations used by many multimedia applications are within the general processor 2202. It can be implemented by using packed data. Thus, by using the full width of the processor data bus to perform operations on packed data, many multimedia applications are accelerated and executed more efficiently. This potentially eliminates the need to transfer smaller data units one data element at a time across the processor data bus in order to perform one or more operations.

  Alternative embodiments of execution unit 2208 may also be used in microcontrollers, embedded processors, graphics devices, DSPs, and other types of logic circuits. System 2200 includes memory 2220. Memory 2220 includes dynamic random access memory (DRAM) devices, static random access memory (SRAM) devices, flash memory devices, or other memory devices. Memory 2220 stores instructions and / or data represented by data signals executed by processor 2202.

  It should be noted that any of the features or aspects described above of the present invention can be utilized in one or more interconnects shown in FIG. For example, an on-die interconnect (ODI) not shown for coupling internal units of the processor 2202 implements one or more aspects of the present invention described above. Alternatively, the present invention may include a processor bus 2210 (eg, other known high performance computing interconnects), a high bandwidth memory path 2218 to memory 2220, a point-to-point link to graphics accelerator 2212 (eg, peripheral component interconnect express). (PCIe) compliant fabric), controller hub interconnect 2222, I / O, or other interconnect for coupling other indicated components (eg, USB, PCI, PCIe). Some examples of such components are: audio controller 2236, firmware hub (flash BIOS) 2228, wireless transceiver 2226, data storage 2224, legacy I / O controller 2210 including user input and keyboard interface 2242, universal serial bus A serial expansion port 2238 such as (USB) and a network controller 2234 are included. Data storage device 2224 may include a hard disk drive, floppy disk drive, CD-ROM device, flash memory device, or other mass storage device.

  Referring now to FIG. 23, a block diagram of a second system 2300 according to one embodiment of the present invention is shown. As shown in FIG. 23, the multiprocessor system 2300 is a point-to-point interconnect system and includes a first processor 2370 and a second processor 2380 coupled via a point-to-point interconnect 2350. Each of processors 2370 and 2380 may be a version of the processor. In one embodiment, 2352 and 2354 are part of a serial point-to-point coherent interconnect fabric, such as a high performance architecture. As a result, the present invention can be implemented within a QPI architecture.

  Although shown with only two processors 2370, 2380, it should be understood that the scope of the invention is not so limited. In other embodiments, there may be one or more additional processors within a given processor.

  A processor 2370 including an integrated memory controller unit 2372 and a processor 2380 including an integrated controller unit 2382 are shown. The processor 2370 also includes point-to-point (PP) interfaces 2376 and 2378 as part of the bus controller unit, and similarly, the second processor 2380 includes PP interfaces 2386 and 2388. Processors 2370, 2380 can exchange information via point-to-point (PP) interface 2350 using PP interface circuits 2378, 2388. As shown in FIG. 23, IMCs 2372 and 2382 couple processors to their respective memories, namely memory 2332 and memory 2334. Memory 2332 and memory 2334 may be part of main memory that is locally attached to the respective processor.

  Processors 2370 and 2380 exchange information with chipset 2390 via individual PP interfaces 2352 and 2354, respectively, using point-to-point interface circuits 2376, 2394, 2386, and 2398. The chipset 2390 also exchanges information with the high performance graphic circuit 2338 via the interface circuit 2392 along the high performance graphic interconnect 2339.

  A shared cache (not shown) can be included in either of the processors or outside of both processors but connected to the processor via the PP interconnect, thereby making the processor low power When entering the mode, the local cache information of either or both processors can be stored in the shared cache.

  Chipset 2390 can be coupled to first bus 2316 via interface 2396. In one embodiment, the first bus 2316 may be a peripheral component interconnect (PCI) bus, or a bus such as a PCI Express bus or another third generation I / O interconnect bus, It is not so limited.

  As shown in FIG. 23, various I / O devices 2314 are coupled to the first bus 2316 along with a bus bridge 2318 that couples the first bus 2316 to the second bus 2320. In one embodiment, the second bus 2320 includes a low pin count (LPC) bus. In one embodiment, various devices including a storage unit 2328 such as, for example, a keyboard and / or mouse 2322, a communication device 2327, and a disk drive or other mass storage device that often includes instructions / codes and data 2330. Are coupled to the second bus 2320. In addition, an audio I / O 2324 coupled to the second bus 2320 is shown. Note that other architectures are possible where the included components and interconnect architectures vary. For example, instead of the point-to-point architecture of FIG. 23, the system can implement a multi-drop bus or other such architecture.

  Referring now to FIG. 24, one embodiment of a system on chip (SOC) design according to the present invention is shown. As a specific example for illustration, SOC 2400 is included in the user equipment (UE). In one embodiment, the UE is any device used for communication by the end user, such as a handheld phone, smartphone, tablet, ultra-thin notebook, notebook with broadband adapter, or any other similar communication device. Point to. In many cases, the UE connects to a base station or node. A base station or node potentially corresponds in nature to a mobile station (MS) in a GSM network.

  Here, the SOC 2400 includes two cores, 2406 and 2407. Similar to the discussion above, the cores 2406 and 2407 are Intel® Architecture Core ™ -based processors, Advanced Micro Devices, Inc. It can be adapted to (AMD) processors, MIPS based processors, ARM based processor designs or their customers, and their licenses or users. Cores 2406 and 2407 are coupled to a cache control 2408 associated with bus interface unit 2409 and L2 cache 2411 for communicating with the rest of system 2400. Interconnect 2410 includes an on-chip interconnect, such as IOSF, AMBA or other interconnect discussed above. These potentially implement one or more aspects described herein.

  The interface 2410 includes a boot ROM 2435 that holds boot code executed by the SIM 2340 for interfacing with a subscriber identity module (SIM) card, cores 2406 and 2407 for initializing and booting the SOC 2400, external memory (eg, DRAM 2460). SDRAM controller 2440 for interfacing with non-volatile memory (eg flash 2465), peripheral controller 2450 for interfacing with peripheral devices (eg serial peripheral interface), video codec 2420, And a video interface 2425 for displaying and receiving input (eg, touch-enabled input), graphics related calculations Of GPU2415 like for row, it provides a communication channel to the other components. Any of these interfaces can incorporate aspects of the invention described herein.

  In addition, the system shows peripherals for communication such as the Bluetooth® module 2470, 3G modem 2475, GPS 2485, and WiFi 2485. Note that as indicated above, the UE includes a radio for communication. As a result, not all of these peripheral communication modules are required. Meanwhile, some form of radio for external communication is included in the UE.

  Although the present invention has been described with respect to a limited number of embodiments, those skilled in the art will appreciate numerous modifications and variations therefrom. The appended claims are intended to cover all modifications and variations that fall within the true spirit and scope of the invention.

  Design can go through various stages, from creation to simulation and manufacturing. Data representing a design can represent the design in multiple ways. First, as useful in simulation, hardware can be represented using a hardware description language or another functional description language. In addition, circuit level models with logic and / or transistor gates can be generated at several stages of the design process. In addition, most designs reach a data level that represents the physical arrangement of various devices in the hardware model in several stages. When conventional semiconductor manufacturing techniques are used, the data representing the hardware model can be data specifying the presence or absence of various features in various mask layers for the mask used to fabricate the integrated circuit. . In any representation of the design, the data can be stored on any form of machine-readable medium. Memory such as a disk or magnetic or optical storage is a machine-readable medium for storing information that is modulated to transmit such information or otherwise transmitted via light waves or radio waves It can be. When an electrical carrier is sent that indicates or carries a code or design, a new copy is made as long as the electrical signal is copied, buffered, or retransmitted. Thus, a communication provider or network provider can store information encoded in a carrier wave or the like that at least temporarily embodies the techniques of embodiments of the present invention on a tangible machine readable medium.

  As used herein, a module refers to any combination of hardware, software, and / or firmware. By way of example, a module includes hardware such as a microcontroller associated with a non-transitory medium that stores code adapted to be executed by the microcontroller. Thus, a reference to a module, in one embodiment, refers to hardware that is specifically configured to recognize and / or execute code held on non-transitory media. Furthermore, in another embodiment, the use of a module refers to a non-transitory medium that includes code that is specifically adapted to be executed by a microcontroller to perform a predetermined operation. And, as can be inferred, in yet another embodiment, the term module (in this example) can refer to a combination of a microcontroller and a non-transitory medium. In many cases, the module boundaries shown as being distinct vary in common and potentially overlap. For example, the first module and the second module may share hardware, software, firmware, or a combination thereof, while potentially holding some independent hardware, software, or firmware. In one embodiment, use of the term logic includes transistors, registers, or other hardware such as programmable logic devices.

  The use of the phrase “configured as” is, in one embodiment, the arrangement, assembly, manufacture, and sale of equipment, hardware, logic, or elements to perform a designated or determined task. Refers to offer, import and / or design. In this example, a non-operating device or element thereof is still configured to perform this specified task when it is designed, coupled and / or interconnected to perform the specified task. " By way of example only, logic gates can provide 0 or 1 during operation. However, logic gates “configured to” provide an enable signal to the clock do not include all potential logic gates that can provide 1 or 0. Instead, the logic gates are coupled in some manner such that during operation, an output of 1 or 0 enables the clock. Again, it should be noted that the term “configured as” does not require action, but instead focuses on the latent state of the device, hardware and / or elements. In a latent state, a device, hardware and / or element is designed to perform a specific task when the device, hardware and / or element is operating.

  Further, the use of the phrases “to do”, “can do” and / or “operable to do” in one embodiment is the use of devices, logic, hardware and / or elements. Any device, logic, hardware, and / or element designed to allow use in a particular manner. As above, in one embodiment, the use of “do”, “can do” or “operable to do” is the potential of the device, logic, hardware and / or elements. Where the device, logic, hardware and / or elements are not operating, but are designed to allow the device to be used in a particular manner.

  As used herein, a value includes any known representation of a number, state, logic state or binary logic state. In many cases, the use of logic levels, logic values or logic values is also referred to as 1 and 0, which simply represents a binary logic state. For example, 1 refers to a high logic level and 0 refers to a low logic level. In one embodiment, a storage cell such as a transistor or flash cell may be capable of holding a single logic value or multiple logic values. On the other hand, other representations of values in computer systems are used. For example, the decimal number 10 can also be represented as the binary value 1010 and the hexadecimal character A. Thus, a value includes any representation of information that can be held in a computer system.

  Further, a state can be represented by a value or a portion of a value. By way of example, a first value such as logic 1 can represent a default or initial state, while a second value such as logic zero can represent a non-default state. Further, the terms reset and set refer to a default value or state and an updated value or state, respectively, in one embodiment. For example, the default value includes a potentially high logic value, ie reset, while the updated value includes a potentially low logic value, ie set. Note that any number of states can be represented using any combination of values.

  Embodiments of the method, hardware, software, firmware, or code shown above are by machine-accessible, machine-readable, computer-accessible, or instructions or code stored on a computer-readable medium that can be executed by a processing element. Can be implemented. A non-transitory machine-accessible / readable medium includes any mechanism that provides (ie, stores and / or transmits) information in a form readable by a machine, such as a computer or electronic system. For example, the non-transitory machine accessible medium is a random access memory (RAM) such as static RAM (SRAM) or dynamic RAM (DRAM), ROM, magnetic or optical storage medium, flash memory device, electrical storage device, optical storage device. , Acoustic storage devices, other forms of storage devices for holding information received from temporary (propagation) signals (eg, carrier waves, infrared signals, digital signals), and the like. These are distinguished from non-transitory media from which information can be received.

  The instructions used to program the logic to perform the embodiments of the present invention may be stored in system memory, such as DRAM, cache, flash memory or other storage. Further, the instructions can be distributed over a network or by other computer readable media. Thus, a machine-readable medium can include any mechanism for storing or transmitting information in a form readable by a machine (eg, a computer), including, but not limited to, a floppy diskette, Optical disk, compact disk read only memory (CD-ROM) and magnetic optical disk, read only memory (ROM), random access memory (RAM), erasable programmable read only memory (EPROM), electrically erasable programmable For transmitting information over the Internet with read-only memory (EEPROM), magnetic or optical cards, flash memory, or electrical, optical, acoustic or other forms of propagation signals (eg carrier waves, infrared signals, digital signals, etc.) Tangible machine-readable stray used It is. Accordingly, a computer readable medium includes any type of tangible machine readable medium suitable for storing or transmitting electronic instructions or information in a form readable by a machine (eg, a computer).

  The following examples relate to embodiments according to the present description. One or more embodiments may receive data on one or more data lanes of a physical link, and on another lane of the physical link, valid data may follow assertion of a valid signal on one or more data lanes. An apparatus, system, machine readable storage, machine readable medium, for receiving a valid signal to identify and receiving a stream signal identifying a type of data on one or more data lanes on another lane of a physical link, Hardware and / or software based logic and methods can be provided.

  In at least one example, the physical layer logic further transmits a link state machine management signal over another lane of the physical link.

  In at least one example, the physical layer logic further transmits a sideband signal over the sideband link.

  In at least one example, the type includes a protocol associated with the data, and the protocol is one of a plurality of protocols that utilize physical links.

  In at least one example, the type includes link layer packet data.

  In at least one example, the data facilitates link state transitions for the physical link.

  In at least one example, the physical layer logic further decodes the stream signal to identify which of a plurality of different protocols to apply to the data.

  In at least one example, the physical layer logic further passes data to higher layer protocol logic corresponding to a particular one of the plurality of protocols identified in the stream signal.

  In at least one example, the device includes, in addition to physical layer logic, each link layer logic and other upper layer logic of the plurality of protocols.

  In at least one example, the plurality of protocols includes at least two of a peripheral component interconnect (PCI), a PCI Express (PCIe), an Intel intra-die interconnect (IDI), and a quick path interconnect (QPI).

  In at least one example, the physical layer logic further determines an error in each of the plurality of protocols.

  In at least one example, the physical layer logic further determines an error in one or more of the valid signal and the stream signal.

  In at least one example, the physical layer logic further defines a data window of data transmitted on the data lane, the data window corresponding to a valid signal.

  In at least one example, the data window corresponds to a data symbol and the valid signal is asserted in the window immediately preceding the window in which data is to be transmitted.

  In at least one example, the data is ignored in the data lane in the window immediately following the previous window where no valid signal is asserted.

  In at least one example, the window corresponds to a byte period.

  In at least one example, each of the valid signal, data, and stream signal is aligned according to a data window defined for the physical link.

  In at least one example, the stream signal is transmitted as data in the same window.

  In at least one example, a physical link connects two devices in a multichip package.

  In at least one example, the physical layer logic further re-centers the signal in the lane of the physical link.

  In at least one example, the lane is re-centered based on the valid signal.

  In at least one example, a stream signal is received on a dedicated stream signal lane of the data link in the second window, the stream signal is decoded, and from the decoding of the stream signal, the protocol associated with the data is determined.

  In at least one example, the data link is adapted to transmit data of a plurality of different protocols.

  In at least one example, data to be transmitted on a data link is identified, and during a particular window corresponding to the data to be transmitted, a valid signal is transmitted on the outgoing valid signal lane of the data link, Data is transmitted on a dedicated outgoing data lane in another window immediately after.

  In at least one example, the plurality of data lanes further includes a dedicated link state machine sideband lane.

  In at least one example, the first device includes a first die in the package and the second device includes a second die in the package.

  In at least one example, the first device includes an on-package device and the second device includes an off-package device.

  One or more embodiments identify data to be transmitted on a dedicated data lane of the data link, and a valid signal on the dedicated valid signal lane of the data link during a particular window corresponding to the data transmitted on the data link. To transmit data on a dedicated data lane of a data link during another window immediately after a specific window, and to transmit a stream signal on a stream signal link encoded to identify the type of data Devices, systems, machine readable storage, machine readable media, hardware and / or software based logic, and methods can be provided.

  In at least one example, the valid signal indicates that the data on the data lane in the other window is valid data.

  In at least one example, the stream signal link includes a dedicated stream signal link.

  In at least one example, the stream signal is adapted to identify whether a particular protocol is associated with the data.

  In at least one example, physical layer logic is included in a common physical layer, multiple protocols utilize this common physical layer, and a particular protocol is included in multiple protocols.

  In at least one example, the plurality of protocols includes two or more of PCI, PCIe, IDI, and QPI.

  In at least one example, the stream signal is further adapted to identify whether the data includes a link layer packet.

  In at least one example, the stream signal is further adapted to identify whether the data is sideband data.

  In at least one example, the physical layer logic further determines a data type and encodes a stream signal that identifies the determined type.

  In at least one example, the physical layer logic further transmits a link state machine sideband (LSM_SB) signal on a dedicated LSM_SB lane of the data link.

  In at least one example, the physical layer logic further transmits sideband signals on a sideband link that is separate from the data link.

  In at least one example, the physical layer logic further transmits link layer data on the data lane, and the link layer data is used to transition the data link from the first link state to the second link state.

  In at least one example, the first link state includes an active link state and the second link state includes a low power link state.

  In at least one example, the physical layer logic further identifies a first data window corresponding to the valid signal and transmits data on a data lane in a second data window immediately following the first data window.

  In at least one example, not asserting a valid signal indicates that data on the data lane in the immediately following window is ignored as invalid.

  In at least one example, each of the first data window and the second data window is defined to correspond to a byte period.

  In at least one example, each of the valid signal, data, and stream signal is aligned according to a data window defined for the physical link.

  In at least one example, the stream signal is transmitted in the same window as the data.

  In at least one example, the physical layer logic further generates each of a valid signal and a stream signal.

  In at least one example, the data link connects two devices in a multi-chip package.

  In at least one example, the data link supports data rates in excess of 8 Gb / s.

  One or more embodiments provide single-ended signaling on a data link that includes multiple lanes, including multiple data lanes, one or more valid signal lanes, and one or more stream lanes, and a clock for use by the multiple lanes Devices, systems, machine readable storage, machine readable media, hardware and / or software based logic, and methods for distributing signals may be provided. Here, the signal transmitted in each of the plurality of lanes is aligned with the clock signal.

  In at least one example, each of the data lanes is intermediate rail terminated to a regulated voltage.

  In at least one example, the regulated voltage is provided to each of the plurality of data lanes by a single voltage regulator.

  In at least one example, the regulated voltage is substantially equal to Vcc / 2, where Vcc includes the supply voltage.

  In at least one example, physical layer logic attempts to provide crosstalk cancellation between two or more of the plurality of data lanes.

  In at least one example, the crosstalk cancellation may be a weighted high pass filtered aggressor signal in the first one of the two or more data lanes and the second one of the two or more data lanes. Provided by adding to the signal.

  In at least one example, the physical layer logic generates a weighted high pass filtered aggressor signal using at least partially a resistor-capacitor (RC) low pass filter.

  In at least one example, the physical layer logic provides bit-by-bit duty cycle correction.

  In at least one example, physical layer logic detects skew in at least a particular one of the data lanes and deskews this particular data lane.

  In at least one example, the physical layer logic further applies AC data bus inversion (DBI) to at least one of the data lanes.

  In at least one example, the clock signal includes a half-rate advanced clock signal.

  In at least one example, the physical layer logic further provides electrostatic discharge protection.

  In at least one example, physical layer logic is implemented at least partially through hardware circuitry.

  In at least one example, valid signals are transmitted on valid signal lanes, each valid signal specifies that valid data follows the assertion of valid signals on multiple data lanes, and the stream signal is a stream signal. Each stream signal transmitted on a lane identifies the type of data on one or more data lanes.

  In at least one example, the data link supports data rates in excess of 8 Gb / s.

  One or more embodiments provide single-ended signaling on a data link including multiple lanes including multiple data lanes, one or more valid signal lanes, one or more stream lanes, and one or more link state machine sideband lanes. Devices, systems, machine readable storage, machine readable media, hardware and / or software based logic, and methods can be provided for providing and distributing clock signals for use by multiple lanes. The signal transmitted in each of the multiple lanes is aligned with the clock signal, providing crosstalk cancellation between two or more of the multiple data lanes and providing bit-by-bit duty cycle correction for the data link Here, each of the data lanes is intermediate rail terminated to a regulated voltage.

  In at least one example, the physical layer logic further detects skew of at least one of the data lanes and deskews the particular data lane.

  One or more embodiments identify that each upper layer of each of the plurality of layered protocols requests a data link transition from an active link state to a low power link state, Apparatus, system, and machine readable storage for transitioning a data link from an active link state to a low power link state based on identifying that each upper layer is requesting a transition to a low power link state , Machine-readable media, hardware and / or software-based logic, and methods can be provided. Each of the plurality of layered protocols uses a data link as a physical layer.

  In at least one example, the physical layer logic further participates in a handshake with another device and transitions the data link to a low power link state.

  In at least one example, the handshake includes a link layer handshake.

  In at least one example, physical layer logic transmits link layer data in a link layer handshake while the data link is in an active link state.

  In at least one example, the physical layer logic transmits the stream signal substantially simultaneously with the link layer data and identifies that the data transmitted on the data layer of the data link includes a link layer packet.

  In at least one example, the stream signal is transmitted on a dedicated stream signal lane of the data link during a specific window, and link layer data is also transmitted during the specific window.

  In at least one example, the physical layer logic transmits a valid signal on a dedicated valid signal lane of the data link, and the valid signal is transmitted in another window immediately before the specific window and transmitted in the specific window. Indicates that the data is valid.

  In at least one example, the handshake includes handshake communication over a sideband link.

  In at least one example, the handshake includes a link layer handshake and handshake communication over a sideband link.

  In at least one example, handshake communication over the sideband link confirms the link layer handshake.

  In at least one example, the physical layer logic further identifies a data link transition request from an active link state to a low power link state from an upper layer of the first layered protocol of the plurality of layered protocols. .

  In at least one example, the physical layer logic further waits for the data link to transition from the active link state to the low power link state until a request is received from each of the other protocols in the plurality of layered protocols.

  In at least one example, the physical layer logic tracks, for each of the multiple layered protocols, whether the protocol has requested that the data link transition from an active link state to a low power link state.

  In at least one example, the physical layer logic further confirms the data link transition from the active link state to the low power link state prior to the actual transition of the data link from the active state to the low power link state. Generate a response to.

  In at least one example, a response is transmitted while the approval of the data link transition from the active link state to the low power link state is outstanding from one or more of the other protocols in the multiple layered protocols Is done.

  In at least one example, the low power link condition includes an idle link condition.

  In at least one example, the plurality of layered protocols include one or more of PCI, PCIe, IDI, and QPI.

  A system comprising a data link comprising a plurality of lanes, a first device and a second device communicatively coupled to the first device using a data link can be provided, the second device comprising: An upper layer logic of the first protocol and an upper layer logic of the second protocol, each of the plurality of protocol stacks using a common physical layer, and a physical layer logic for the common physical layer And before the physical layer logic transitions the data link to the low power link state, each of the protocols, including the first protocol and the second protocol, uses the data link to go from the active link state to the low state. And physical layer logic that determines that the data link is authorized to transition to a power link state.

  In at least one example, the plurality of lanes includes a plurality of data lanes, one or more valid signal lanes, and one or more stream lanes.

  In at least one example, valid signals are transmitted on valid signal lanes, each valid signal specifying that valid data follows the assertion of valid signals in multiple data lanes, and the stream signal is a stream signal lane. Each stream signal transmitted above identifies the type of data on one or more data lanes.

  In at least one example, transitioning the data link to a low power link state includes a handshake between the first device and the second device.

  In at least one example, the handshake includes a link layer handshake and a sideband handshake.

  In at least one example, the first device includes a first die in the package and the second device includes a second die in the package.

  In at least one example, the first device includes an on-package device and the second device includes an off-package device.

  Throughout this specification "one embodiment" or "one embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. Means. Thus, the phrases “in one embodiment” or “in one embodiment” appearing in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

  In the foregoing specification, a detailed description has been given with reference to specific exemplary embodiments. However, it will be apparent that various changes and modifications can be made without departing from the broader spirit and scope of the invention as set forth in the appended claims. The specification and drawings are, therefore, to be regarded in an illustrative sense rather than a restrictive sense. Further, the above uses of embodiments and other exemplary languages do not necessarily refer to the same embodiment or the same example, but potentially to the same embodiment or different embodiments and separate embodiments. There is also.

Claims (25)

A device comprising a physical layer interface,
The physical layer interface is
A clock lane that supports the clock signal;
A control interface that supports one or more control signals, wherein the one or more control signals include a control signal that transitions in a link state according to a state machine;
A plurality of data lanes for transmitting data;
An effective signal lane that supports transmission of an effective signal, wherein transmission of data on the data lane is aligned with transmission of the effective signal on the effective signal lane; and
An apparatus comprising:   The apparatus of claim 1, further comprising physical layer logic for generating the valid signal.   The apparatus of claim 2, wherein the physical layer logic manages training of a link comprising the plurality of data lanes.   4. The apparatus of claim 3, wherein the link state includes a plurality of link training states, and the link training state is used in training the link.   The apparatus of claim 4, wherein the particular one of the plurality of link training states includes a low power state in which no data is transmitted on the link.   6. The apparatus according to any one of claims 3 to 5, wherein training of the link includes transmitting and receiving a training sequence on the link.   The apparatus according to claim 1, wherein the control signal includes a sideband control signal.   The apparatus according to claim 1, wherein the physical layer interface comprises a physical layer abstraction.   The apparatus according to any one of claims 1 to 8, further comprising a transmitter for transmitting the valid signal and transmitting specific data on a plurality of data lanes aligned with the valid signal. A device comprising an interface,
The interface is
A clock signal lane for receiving the clock signal; and
A control interface for receiving one or more control signals, the one or more control signals including a control signal to transition in a link state according to a state machine;
A plurality of data lanes for receiving data transmitted on the link by other devices;
A valid signal lane that receives a valid signal corresponding to the data, wherein transmission of data on the data lane is aligned with transmission of the valid signal on the valid signal lane; and
An apparatus comprising:   The physical layer logic of claim 10 further comprising receiving the valid signal on the valid signal lane and processing the data received on the plurality of data lanes based on the receipt of the valid signal. Equipment.   The apparatus according to claim 10, wherein the control signal includes a sideband signal.   The apparatus according to claim 10, wherein the valid signal is aligned with an edge of the clock signal.   The apparatus according to claim 10, wherein the link state includes a link training state.   The apparatus of claim 14, wherein a training sequence is transmitted and received by the apparatus during one or more of the link training states.   The apparatus of claim 15, wherein the training sequence follows a defined interconnect protocol.   The apparatus of claim 16, wherein the defined interconnect protocol comprises one of a plurality of different interconnect protocols that support use of the interface. Sending a clock signal on the dedicated clock lane of the interface;
Transmitting a control signal on a control lane, wherein the control signal transitions in a link state according to a state machine; and
Identifying data transmitted on a plurality of data lanes of the interface;
Transmitting a valid signal on a dedicated valid lane of the interface, the valid signal transmitting a valid signal corresponding to specific data;
Transmitting the specific data on the plurality of data lanes aligned with the valid signal;
Including a method.   An apparatus comprising means for performing the method of claim 18. A first computing device;
A second computing device connected to the first computing device by a link, the second computing device comprising a physical layer interface that supports the link;
A system comprising:
The physical layer interface is
A clock signal lane for receiving the clock signal; and
A control interface for receiving one or more control signals, the one or more control signals including a control signal to transition in a link state according to a state machine;
Multiple data lanes for receiving data transmitted on the link by other devices;
A valid signal lane that receives a valid signal corresponding to the data, wherein transmission of data on the data lane is aligned with transmission of the valid signal on the valid signal lane; and
A system comprising:   The system of claim 20, wherein the second computing device comprises a processor.   The system of claim 21, wherein the first computing device comprises a second processor.   The system of claim 20, wherein the second computing device comprises a memory controller.   The system of claim 20, wherein the second computing device comprises a graphics processor.   The system of claim 20, wherein the second computing device comprises a network controller.

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