DE112010005265T5 - Increased breakdown voltage DMOS transistor and method of fabrication. - Google Patents

Abstract

The depletion mode DMOS transistor includes a gap in an electrode material that facilitates the incorporation of a well dopant species into the underlying semiconductor material. During a subsequent dopant diffusion, a contiguous well region is obtained that has an increased lateral extent without increasing a depth. The source dopant species is implanted after masking the gap. Additional channel implantation is performed prior to fabrication of the gate dielectric material.

Description

Technical area.

The claimed invention relates to a depletion type DMOS (double diffused metal-oxide-semiconductor) transistor or adapted to operate in depletion mode, wherein a conductive channel is formed without applying a voltage to the gate electrode structure.

Background.

In general, field-effect transistors (FETs) and in particular MOS transistors are semiconductor components which have a source terminal and a drain terminal and an intermediate channel region in which a conductive channel is built up on application of a suitable control voltage to a gate electrode structure. The gate electrode structure in turn includes a gate electrode and a gate dielectric layer separating the gate electrode from the channel region. Upon application of a voltage across the gate electrode and the semiconductor body which is connected to the channel region, and when the threshold voltage of the transistors is exceeded, charge carriers are increasingly accumulated at the interface formed by the gate dielectric layer and the channel region, so that a conductive Channel is established between the source region and the drain region. Thus, the current flow is caused only by a single type of charge carriers in contrast to the current flow in a bipolar transistor, in which both the minority carriers and the majority charge carriers contribute to the flow of current. Due to this unipolar current flow in field effect transistors, the switching speed is significantly shorter compared to bipolar transistors, whereby the FET and in particular a MOS transistor is a very suitable candidate for high-speed applications.

More recently, FET devices, and MOS transistors in particular, are increasingly being used in power applications. Such applications require the handling of currents up to several 10 A or more and voltages up to 100 V and much higher, since in many cases fast switching transistors in switched power supplies, motor controls and the like are needed. However, the high voltages in power applications require some adjustments in the dopant profiles of the MOS transistors to provide the desired breakdown voltage characteristics. For example, a so-called drift region is connected to the drain region and thus connects the drain region with the intended channel region. The drift region is basically a semiconductor region with the same basic doping as the drain region but with a reduced dopant concentration. This results in a substantially ohmic behavior of the drift region, causing a corresponding voltage drop across the drift region in the formation of a conductive channel. Consequently, the dopant profile in the drain region and the source region and their connection to the channel region with an intermediate drift region determine the transistor properties in "power applications".

Field effect transistors can generally be divided into enhancement transistors and depletion transistors. In an enhancement mode transistor, the channel region does not have a conductive path when zero voltage is applied to the gate electrode structure, while depletion type transistors have a conductive channel at zero gate voltage. Thus, the depletion mode transistors are conductive without the application of a gate voltage, and these depletion transistors can be turned off by applying a gate voltage. For an n-channel transistor, this voltage is negative. To this end, the depletion mode transistor receives an additional dopant concentration in the channel region, resulting in a conductive path between the drain region and the source region, which increasingly "depletes" charge carriers upon application of a negative gate to source voltage, ultimately the transistor turns off when the channel area is completely depleted.

In reference to 1 Now, a typical transistor structure of a vertical DMOS transistor 10 and discuss conventional techniques for generating an additional channel region for a depletion type transistor in more detail.

It is a schematic cross-sectional view of said DMOS transistor 10 which is shown in the form of an enhancement type transistor. The transistor 10 includes a heavily doped substrate material 1 , also called the drain region or drain of the transistor 10 acts. For an example n-type transistor, the drain region is 1 heavily n-doped. A semiconductor layer 2 is the drift region of the transistor 10 provided and is above the drainage area 1 educated. The drift area has the same conductivity as the drain area 1 but with a reduced dopant concentration. A tub area 5 is in the drift area 2 formed and has the inverse conductivity in comparison to the drift region 2 on. In the tub area 5 is a heavily doped source region 6 provided and thus forms a pn junction with the tub area 5 , An area 9 on a surface of the drift area 2 that in the tub area 5 laterally adjacent to the source region 6 disposed is referred to as a "channel region" because a conductive path is formed here when a suitable control voltage is applied to a gate electrode structure 4a is applied, which is a gate electrode 4 For example, a doped polysilicon material, and a gate dielectric layer 3 , such as a silicon dioxide material having the gate electrode 4 from the channel area 9 and the drift area 2 separates. Furthermore, the transistor comprises 10 a dielectric interlayer material or an inter-metal dielectric material 7 , the openings (not shown) for contacting the gate electrode 4 and for connecting the source region 6 and the tub area 5 has, as indicated by the reference numeral 8th is specified.

The in 1 The transistor shown is typically made by placing the substrate 1 with the desired dopant concentration while the drift region 2 the reduced dopant concentration is obtained, for example, by epitaxially producing a semiconductor material and at the same time incorporating therein the dopant species. The gate structure 4a is provided on the basis of well established deposition and / or oxidation techniques. After that, the tub area 5 produced by an implantation and annealing process. That is, the dopant species of the well area 5 is in the presence of the gate electrode structure 4a implanted, which serves as an implantation mask, creating a self-aligned position of the well area 5 with respect to the gate electrode 4 is reached. During the subsequent bake process, diffusion of the dopants is initiated, with the process parameters (temperature and process time) selected to provide the desired lateral "overlap" of the well region 5 with the gate electrode 4 is reached. It should be noted that vertical diffusion also takes place. Similarly, the dopant species of the source region 6 implanted in a self-aligned manner, wherein the gate electrode structure 4a and a resist mask may be used as an implantation mask. In another annealing process, the final shape of the source region becomes 6 and possibly the tub area 5 adjusted by causing a desired degree of diffusion. Finally, the interlayer dielectric material becomes 7 deposited and the openings are created therein to connect to the contact area 8th manufacture.

During operation of the transistor 10 Assuming an n-channel transistor is assumed, a gate-to-source voltage or gate-to-well voltage of zero or a negative value will result in a substantially non-conductive state of the channel region 9 with the exception of low leakage currents. When a positive gate-source voltage is applied, increasingly electrons accumulate at the interface that flows through the well region 5 and the gate dielectric layer 3 is formed. The electrons recombine with the majority carriers (the holes) until the gate-source voltage exceeds a threshold voltage representing the voltage level at which excess electrons remain, thereby reducing the channel area 9 "Inverted" and a conductive channel between the source region 6 and the drift area 2 through the tub area 15 through trains. It should be noted that the characteristics of the transistor, such as the on-resistance, the threshold voltage, and the like, are substantially different from the structure of the dopant profiles of the regions 2 . 5 . 6 depend.

To operate in depletion mode based on the configuration of the transistor 10 to obtain, as previously described, is in the US 4,003,071 (Sadaaki Takagi, Fujitsu) suggested to apply an additional implantation to dopants near the surface of the channel region 9 in order to increase the doping therein so that a conductive path is obtained. Thus, a conductive connection between the source region 6 and the drift area 2 obtained via the additionally introduced dopants. In the example of an n-channel transistor described above, an n-type dopant species becomes the channel region 6 , such as phosphorus, arsenic or antimony, incorporated with a moderately low implantation dose. In this way, the heavily doped drainage area 1 and the source area 6 electrically connected together in the absence of a gate voltage. On the other hand, the conductive channel depletes when a negative gate voltage is applied, causing the transistor 10 is switched off.

US 6,700,160 (Steven Merchant, Texas Instruments) discloses a DMOS transistor having an additional doped region below the gate oxide within the lightly doped drift region 2 and within a part of the tub area 5 , However, the operation mode (enrichment type or depletion type) is not changed by this change in construction.

In general, providing an additional doped region in the channel region of an enhancement mode transistor to achieve a depletion mode is a promising approach. However, implanting the additional dopants through the gate electrode or even through the gate dielectric material may result in significant damage to the gate dielectric material, thereby affecting overall transistor performance. On the other hand, incorporation of the additional dopants prior to fabrication of the gate dielectric material results in pronounced dopant diffusion during the anneal process Alignment of the tub profile. In particular, a pronounced vertical diffusion occurs in the tub area 5 in, which negatively affects the overall transistor behavior. By using suitable dopant species with a high diffusion coefficient, such as boron, for the well region and with a small diffusion coefficient for additional channel doping, such as arsenic or antimony, vertical diffusion into the well region depth can be reduced but not avoided.

However, if the transistor is turned off, a previous breakdown may occur because the effective well doping is reduced due to the additional channel doping, even if it is strongly negatively biased. Thus, the space charge zone in the well region may become the heavily doped source region 6 extend or penetrate into this.

2 schematically shows the results of a simulation in a conventional transistor of the depletion type, having an additional doped channel region, wherein the additional dopant species schematically by the reference numeral 21 is designated. The channel area with the additional doping 21 has the inverse doping of the well area 5 as previously explained. In this case, the status of a negative gate voltage (switched off state or blocking mode) is shown. As indicated by the potential lines, even a moderately low voltage between the drain region and the source region may cause the drain potential to penetrate into the source region 6 to lead. An undesirable reduction of the breakdown voltage, which is caused by the doping situation for producing the additionally doped channel region, can be compensated for by adjusting the channel length (in 1 the horizontal extent of the canal area 9 ) is increased. As previously evaluated, the total dopant profile, and thus channel length, are typically adjusted by the temperature and duration of the anneal processes. For example, a larger channel length is achieved by increasing the diffusion activity during well diffusion, which not only increases lateral diffusion and thus channel length, but also increases the vertical extent of the well region, resulting in an undesirable change in transistor characteristics ,

Overview of the invention.

It is an object of the invention to provide a depletion mode DMOS transistor having an increased breakdown voltage based on an increased channel length, while avoiding one or more of the problems described above.

The invention provides a DMOS transistor and fabrication techniques for making the same, wherein a depletion mode is achieved by providing additional implantation into the channel region of the DMOS transistor, thereby creating a doped region, also referred to as an "additional doped channel region". referred to as.

Due to the additionally doped channel region, a conducting path is generated without a gate voltage being applied. The implantation of the additional channel doping is preferably performed prior to the fabrication of the gate dielectric material, thereby avoiding implantation-induced damage in the gate dielectric material. For the subsequent implantation of the well region, the gate electrode is used as an implantation mask having a suitable structure to allow incorporation of the well dopant species into the semiconductor material laterally adjacent the gate electrode and also locally below the gate electrode structure, thereby providing more lateral diffusion of well dopant species without amplification of the vertical diffusion is possible. Thus, a desired increase in channel length may be achieved based on the increased lateral diffusion provided by the well dopant species additionally provided locally below the gate electrode structure. The larger channel length in turn compensates for the additional doped channel region with respect to the breakdown voltage without undesirably increasing a depth of the well region.

In one aspect of the invention, a depletion mode DMOS transistor is proposed (claims 1 and 22). The transistor includes a gate electrode structure formed on a semiconductor material and having a gate dielectric layer and an electrode. The electrode includes a first electrode region and a second electrode region that are laterally separated (along a current flow direction) by an insulating material. Further, a source region of a first conductivity type is formed laterally adjacent to and partially below the first electrode region in the semiconductor material. The transistor further includes an additionally doped channel region of the first conductivity type that communicates with the source region and extends below the first and second electrode regions along the current flow direction. A well region of a second conductivity type is formed in the semiconductor material so as to be in contact with the source region, the additionally doped channel region, and a first conductivity type drift region Well region extends laterally below the first and the second electrode region along the current flow direction. Further, the transistor includes a drain region of the first conductivity type that is in contact with the drift region.

As previously discussed, the transistor of this aspect includes a "split" gate electrode structure that allows for interim mounting of the well dopant species, thereby providing additional channel length without contributing to increased "vertical" expansion of the well region.

The transistor may further include a coupling region such that the first and second electrode regions are electrically connected together. Thus, the gate electrode may electrically function as a single unit, yet still achieve the improved well dopant distribution during implantation of the well dopant species.

In another embodiment, the coupling region is part of the electrode. In this case, the coupling region and the electrode regions can be made together from the electrode material, thereby avoiding additional process steps.

In a further embodiment, the coupling region comprises a metal region, which is formed in a component plane above the gate electrode structure. Thus, higher conductivity materials can be used while avoiding the ion blocking effect of any coupling regions, thereby allowing the use of a reduced implantation dose.

The well region may be made below the coupling region to provide a contiguous well region. Thus, an adverse effect of the coupling region on the final well dopant distribution can be avoided.

In a further embodiment, the electrode comprises a central opening formed over a region of the source region. This configuration of a transistor cell allows a spatially effective layout, with the cleaved configuration of the electrode providing the desired enhanced lateral diffusion under the well region. For example, the central opening in plan view has a square, a circular, a rectangular, a hexagonal or an octagonal shape.

According to another aspect of the disclosure, a semiconductor device with a depletion-mode DMOS transistor is proposed and claimed (claim 9). The semiconductor device includes a gate electrode structure formed on a semiconductor material and having a gate dielectric material and a gap electrode. The device further comprises a source region formed in the semiconductor material and extending partially below the electrode. Further, a channel region is formed in the semiconductor material and extends below the electrode and the gap from the source region to a drift region. Further, the transistor comprises a drain region communicating with the drift region.

Thus, the semiconductor device provides a laterally increased (or extended) channel length, as previously explained.

In further embodiments, the channel region includes additional channel doping with the same conductivity type as the source region.

The electrode may include at least a first electrode region and a second electrode region that are laterally separated along a current flow direction through the gap. The electrode may have a material region such that the first and second electrode regions are electrically connected.

In other embodiments, the first and second electrode regions are electrically connected by means of a connection structure that is at least partially formed in a metallization system of the semiconductor device.

In a further embodiment, the gate electrode structure comprises a central opening, and a current flow direction in the channel region is oriented outwardly from the central opening.

In yet another embodiment, the central opening has a square shape, a circular shape, a rectangular shape, a hexagonal shape, or an octagonal shape corresponding to a top view of the gate electrode structure.

According to another aspect of the invention, there is provided a method of fabricating a depletion-mode DMOS transistor in a semiconductor device (claim 20). The method includes the steps of introducing an additional channel dopant species into a semiconductor layer and forming a gate electrode structure over the semiconductor layer, wherein the gate electrode structure comprises a gate dielectric material and a gap gate electrode. The method further includes the steps of implanting a A well dope species into the semiconductor layer laterally adjacent the gate electrode structure and through the gap and performing a first anneal process to create a contiguous well region. The method further comprises forming a mask over the gap and implanting a source dopant species in the semiconductor layer using the mask and the gate electrode structure as an implantation mask. The method further includes the step of performing a second anneal process for diffusing a portion of the source dopant species below the gate electrode structure.

Based on the above method, the lateral extent of the well region can be increased without contributing to a greater vertical extent of the well region since the gap allows for local incorporation of a portion of the well dopant species which thus connects to the well dopant species during the subsequent anneal process which is implanted at the edge of the gate electrode. On the other hand, during implantation of the source dopant species, the mask ensures a contiguous ion blocking effect of the gate electrode, similar to conventional approaches as previously described.

In another embodiment, forming the gate electrode structure comprises depositing an electrode material on the gate dielectric material and patterning the electrode material such that the gap and at least one coupling region are electrically connected to each other by portions of the gate electrode separated by the gap. In this way, the electrode continues to function as an electrical unit without requiring additional process steps.

In another embodiment, forming the gate electrode structure comprises depositing an electrode material on the gate dielectric material and patterning the electrode material such that a first region and a second region are obtained that are electrically isolated from each other through the gap. In this case, improved uniformity of the well dopant distribution after implantation can be achieved, wherein the electrical connection of the separate first and second regions is achieved by making a connection structure in a wiring system of the semiconductor device.

In yet another aspect of the present invention, a method of making a DMOS transistor comprises implanting a well dopant species into a semiconductor material in the presence of a gate electrode structure having at least one gap for incorporating a portion of the well dopant species into the semiconductor material through the at least one gap. The method further comprises: masking the at least one gap and implanting a source dopant species into the semiconductor material in the presence of the gate electrode structure having the at least one masked gap. Further, the method includes: forming a well region and a source region by performing annealing processes such that diffusion of the well dopant species and the source dopant species is initiated.

Thus, due to the positioning of a portion of the well dopant species, the well dopant species may be laterally diffused at the at least one gap, which is then masked during installation of the source dopant species.

In another embodiment, an additional channel dopant species is incorporated prior to forming the gate electrode structure. In this way, a channel region for the depletion mode can be provided without unnecessarily affecting the sensitive gate dielectric material.

Reference signs in the claims serve to locate them more quickly, but are not intended to be used to interpret embodiments in the claim language.

Introduction to embodiments.

The embodiments enhance the understanding of the invention (s) as claimed. They are not "the invention" but examples (embodiments) thereof.

1 12 schematically shows a cross-sectional view of an enhancement type vertical DMOS transistor according to a conventional transistor architecture;

2 schematically shows a (voltage) potential in an off state in a known transistor having an additionally doped channel region to obtain a depletion mode DMOS transistor, thereby reducing the breakdown voltage,

3 Fig. 12 schematically shows a cross-sectional view of a new depletion mode DMOS transistor having a larger channel length while the well region has a desired vertical extension.

4 schematically shows the (reverse voltage) potential in the transistor, a additional channel region and a split gate electrode, whereby an early strike through can be avoided

5 shows schematically a perspective view of a DMOS transistor with gaps in the gate electrode,

6 12 schematically shows a top view of a gate electrode structure with gaps and coupling regions for the electrical connection of separate electrode regions,

7 schematically shows a plan view of a DMOS transistor cell with a central gate opening and

8th schematically shows a perspective view of a DMOS transistor having a gate electrode having separate electrode regions, which are electrically connected by a connection structure which is at least partially formed in the metallization of the device.

Detailed disclosure of embodiments.

With reference to the drawings, further illustrative embodiments will now be described, wherein identical or similar components are designated by the same reference numerals.

3 schematically shows a cross-sectional view of a semiconductor device 100 with a DMOS transistor 10 in the form of a depletion type transistor. The transistor comprises a semiconductor material with a heavily doped drain region 1 , a lightly doped semiconductor layer or a drift region 2 , which may have a similar construction, as previously with reference to 1 is described. Thus, for an n-channel transistor, the regions 1 and 2 n-doped areas. Further, a tub area 25 with increased lateral extension or expansion in the semiconductor material of the device 100 formed and it includes a channel area 9 that with a source area 6 communicates. Due to the enlarged lateral extent of the tub area 25 is also the length of the canal area 6 larger, as for the formation of a conductive channel between the source region 6 and the drift area 2 without applying a voltage across a gate electrode structure 22a and the source area 6 is required, as previously explained.

The gate electrode structure 22a contains a gate dielectric material 3 , which is a gate electrode 22 from the channel area 9 containing the additional channel doping, indicated schematically by the reference numeral 21 is specified, and from the source area 6 separates. The gate electrode 22 can have two or more electrode areas 22b . 22c along a current flow direction 9a separated, creating a gap or slit 23 is formed. The gap 23 is with an insulating material of a dielectric interlayer material 7 filled. As shown, the additional doped region extends 21 of the canal area 9 and the tub area 25 coherent along the direction 9a , which also "bridges" an area in the semiconductor material that underlies the gap 23 is arranged.

The component 100 with the transistor 10 is made on the basis of the following processes. First, the heavily endowed Drain area 1 by providing, for example, a heavily doped substrate or by incorporating a desired high dopant concentration. Next, the semiconductor layer 2 is prepared so that it has the desired low dopant concentration, as is required for a drift region. For this purpose, a semiconductor material may epitaxially on the material 1 are grown, whereby the desired amount of dopants is incorporated. Thereafter, isolation structures or field oxide regions (not shown) are fabricated, followed by the implantation of a dopant species for incorporation of the additional channel dopant species 21 followed. The additional channel dopant species may be limited in the lateral direction by providing an implantation mask, such as a resist mask, and the like. The gate dielectric material 3 is then prepared by, for example, a part of the layer 2 is oxidized, whereby a silicon dioxide material is generated when the layer 2 is made of silicon. It should be noted that the gate dielectric material 3 can also be additionally or alternatively prepared by depositing a dielectric material. Thereafter, the material of the gate electrode 22 deposited, for example, as a metal, as doped polysilicon, as undoped polysilicon, and the like. The electrode material is then patterned by creating an etch mask and performing appropriate and well-established etching processes. However, the patterning of the electrode material, unlike conventional approaches, is based on a design that includes one or more of the gaps 23 containing, whereby at least the first and the second electrode area 22b . 22c to be provided. During patterning, the gate dielectric material 3 be used as an etch stop material. The "length" of the gap 23 , ie its lateral extension or extension along the direction 9a , and the length of the electrode area 22b are consistent with the diffusion behavior of the well dopant species in the well area 25 selected in the layer 2 is implanted, wherein the gate electrode structure 22a is used as an implantation mask. Therefore, during tub implantation, a tub dopant species also becomes in the layer 2 through the gap 23 , thereby creating locally intermediate dopant reservoirs serving as dopant sources during the subsequent anneal process to laterally place the well dopant species below the electrode region 22b starting from the gap 23 and from the edge of the gate electrode 22 on the right side of the 3 to distribute. As previously explained, the depth of the well area can also be 25 during the annealing process, and possibly during another anneal process, but that of the entire lateral extent of the well region below the gate electrode 22 due to the presence of the additional well dopant source under the gap 23 is decoupled. Since the diffusion behavior can be determined in advance for a given type of dopant and predetermined bake parameters, the lateral size of the gap 23 and the electrode area 22b suitably set so that the contiguous area 25 reaches the desired lateral extension or expansion.

Next is a mask 11 , such as a resist mask, made so that this gap 23 what is accomplished by performing a lithography process using a suitable lithography mask. It should be noted that the adjustment of the mask 11 not critical, as long as the gap 23 is reliably covered while the edge of the gate electrode 22 remains exposed to achieve the self-aligning effect when another implantation process for incorporation of the source dopant species of the source region 6 is performed. During the source implantation thus provides the gate electrode 22 the mask effect due to the presence of the additional mask 11 , If necessary, the mask 11 also be used to form an exposed portion of the gate dielectric material 3 while removing the dielectric material 3 in the gap 23 is maintained. After removing the mask 11 For example, the source dopant species is diffused as desired by utilizing a further anneal process in which additional diffusion of the well dopant species may occur. Thereafter, the interlayer dielectric material becomes 7 deposited and patterned to create openings therein that can be filled with a suitable conductive material. Next, a metallization system (not shown) is made according to the overall device requirements.

4 schematically shows the results of a simulation of the transistor 10 out 3 when it is operated in the off state or off state. Due to the appropriate depth of the tub area 25 and the extended length of the channel 9 , which is provided therein, the negative biased state of the gate electrode 22 to a high breakdown voltage so that an early breakdown or an early penetration is avoided, as by the potential lines 20 is specified.

5 schematically shows a perspective view of the transistor 10 according to an illustrative embodiment. As shown, the gap is 23 through a coupling area or a coupling bar 24 "Interrupted", thus the electrode areas 22b and 22c connects electrically. Thus, the gate electrode 22 are electrically considered to be a single component, while still obtaining the desired dopant sources for the well dopant species, as discussed above, in view of the ion blocking effect. Around the tub area 25 near the coupling area 24 not undesirable decouple, the lateral dimension, about a width 24a set so that for the given Dotierstoffdiffusionsverhalten the Wannendotierstoffsorte and for the given Ausheizparameter the tub area is also below the range 24 extends and is contiguous with the remaining areas of the tub area 25 combines.

6 schematically shows a plan view of the gate electrode 22 , where the gap 23 along the lateral direction L through the coupling areas 24 is interrupted. For the sake of simplicity, the following description refers only to the transistor cell located on the right side of FIG 6 is shown. The lateral dimensions of the electrode area 22b and the lateral position of the gap 23 are set so that the tub area 25 is obtained in a contiguous configuration. As shown, the diffusion of the tub dopant species may become lateral extension 25s lead, if the pan dopant type initially at the periphery or the edge 22e of the area 22b is arranged after implantation. On the other hand, the diffusion can proceed from the gap 23 towards the edge 25e to an extent 25g lead, taking the combined length of the expansions 25e and 25g is greater than the distance from the gap 23 to the edge 22e , Similarly, the dimension of the coupling area 24 , as 24a is specified and which can also be understood as the distance of individual gap areas, less than twice the extent 25g ,

When the above conditions regarding the diffusion of the well dopant species are satisfied, the extent of the well region is 25 under the area 22 or below the range 22c determined by: the extent 25g , a 'width' 23 ' of gap 23 (in the current flow direction 9a ) and an offset 22e ' of the gap 23 in relation to the edge 22e , The expansion 25g , the width 23 ' and the offset 22e ' result in the sum of a "total length under the gate 22 ".

It should be noted that due to the nature of a diffusion process, the corresponding lateral dimensions, e.g. 25g . 25e , are to be understood as statements which describe a threshold value of the dopant concentration. For example, a "boundary" of a diffusion region may be understood as a location at which the concentration drops to less than 30% of a maximum concentration.

7 schematically shows a plan view of the gate electrode 22 for a transistor cell configuration in which the gate electrode has a central opening 22o which is formed over a region of the source region (not shown). Thus, the current flow direction is from the central opening 22o directed away to the outside. The source region may therefore be connected to the first electrode region 22b overlap the central opening two 22o limited. Furthermore, several columns (or gap areas) separate 23 the area 22b from the area 22c along the current flow direction 9a , In this example, the lateral dimensions of the area 22b , the column (gap areas) 23 and the coupling areas 24 in accordance with the above in relation to 6 specified considerations to obtain a contiguous well area. In other embodiments, the shape of the gate electrode differs 22 from the square shape 7 , For example, a rectangular shape, a hexagonal shape, or an octagonal shape may be provided for the central opening, thereby providing a spatially efficient configuration for a transistor cell.

8th schematically shows a perspective view of the transistor 10 according to further embodiments, in which the gate electrode 22 the electrode areas 22c . 22b as isolated areas. In this case, the gap 23 not interrupted by coupling areas provided in the gate electrode material itself. Instead, the electrical connection becomes a connection structure 27 made of the at least one part in a metallization system of the semiconductor device, which is the transistor 10 contains, is formed. For example, the connection structure contains 27 a first contact element 28b formed in the interlayer dielectric material (not shown) and connecting to the electrode region 22b manufactures. Furthermore, a second contact element 28c provided and connects to the electrode area 22c ago. The first and second contact elements may be manufactured during the standard contact process. Subsequently, a first metallization plane is generated in which a metal region 26 is provided so that it with the first and the second contact element 28b . 28c connected is. Thus, during implantation, the well dopant species is based on the uninterrupted gap 23 a better dopant distribution is achieved while the interconnect structure provides a well-conductive connection without the need for additional process steps.

It should be noted that the transistors described herein may be provided as p-channel transistors and n-channel transistors by appropriately selecting the type of dopants used for the various semiconductor regions. Thus, depletion type n-channel transistors and / or depletion type p-channel transistors may be provided in the semiconductor device depending on the overall circuit configuration. Further, if a still further increased channel length is required, two or more gaps may be provided in series along the current flow direction, the spacing of the gaps being suitably determined to provide a contiguous well region with increased lateral extent. Further, the semiconductor devices described herein may preferably be fabricated based on silicon as the base material. In other instances, however, the principles disclosed herein may also be applied to other semiconductor materials, such as germanium, silicon germanium, compound semiconductors, and the like.

Further, in the embodiments described with reference to the drawings, vertical DMOS devices are indicated. In other embodiments, the drain and source configuration is provided in a lateral or planar configuration to provide a lateral DMOS device.

QUOTES INCLUDE IN THE DESCRIPTION

This list of the documents listed by the applicant has been generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Cited patent literature

• US Pat. No. 4003071 [0009]
• US 6700160 [0010]

Claims (22)

Depletion mode DMOS transistor having a gate electrode structure ( 22a ) on a semiconductor material ( 2 . 1 ) and a gate dielectric layer ( 3 ) and an electrode ( 22 ), wherein the electrode has a first electrode region ( 22b ) and a second electrode area ( 22c ) laterally separated by an insulating material ( 7 ), wherein - a source region ( 6 ) of a first conductivity type in the semiconductor material ( 2 ) partially below the first electrode area ( 22b ) is trained; An additionally doped channel region ( 9 . 21 ) of the first conductivity type with the source region ( 6 ) and under the first and second electrode area ( 22b . 22c ) along a current flow direction ( 9a ) extends; - a bath area ( 25 ) of a second conductivity type in the semiconductor material ( 2 ) is designed so that it is connected to the source region ( 6 ) is in contact; The additionally doped channel region ( 9 . 21 ) and a drift area ( 2 ) have the first conductivity type; - the bath area ( 25 ) laterally below the first and second electrode regions ( 22b . 22c ) extends; - a drainage area ( 1 ) of the first conductivity type in contact with the drift region ( 2 ) is provided. A DMOS transistor according to claim 1, further comprising a coupling region (Fig. 24 ) such that it covers the first and second electrode regions ( 22b . 22c ) electrically connects. A DMOS transistor according to claim 2, wherein the coupling region ( 24 ) a part of the electrode ( 22 ). A DMOS transistor according to claim 2, wherein the coupling region is a metal region ( 26 ) formed in a device plane above the gate electrode structure. The DMOS transistor of claim 3, wherein the well region below the coupling region is configured to provide a contiguous well region. A DMOS transistor according to claim 1, wherein the electrode has a central opening ( 22o ) formed over a region of the source region. A DMOS transistor according to claim 6, wherein said central opening has a square shape in plan view. A DMOS transistor according to claim 6, wherein the central aperture has a circular, a rectangular, a hexagonal or an octagonal shape. Semiconductor device having a depletion mode DMOS transistor, wherein the semiconductor device comprises A gate electrode structure on a semiconductor material comprising a gate dielectric material and an electrode with a gap; A source region in the semiconductor material, the source region extending below the gate electrode structure; A channel region in the semiconductor material, the channel region extending below the gate electrode structure and the gap extending from the source region to a drift region; - a drain area associated with the drift area. The semiconductor device of claim 9, wherein the channel region has an additional channel region of the same conductivity type as the source region. The semiconductor region of claim 9, wherein the electrode has at least a first electrode region and a second electrode region laterally separated along a current flow direction through the gap. The semiconductor device according to claim 11, wherein the electrode has a material region such that the first and second electrode regions are electrically connected. The semiconductor device of claim 11, wherein the first and second electrode regions are electrically connected by a connection structure formed at least partially in a metallization system of the semiconductor device. The semiconductor device of claim 9, wherein the gate electrode structure has a central opening, and a current flow direction in the channel region is outwardly oriented from the central opening. The semiconductor device according to claim 14, wherein the central opening has a square shape, a circular shape, a rectangular shape, a hexagonal shape or an octagonal shape in plan view of the gate electrode structure. A method of fabricating a depletion-mode DMOS transistor in a semiconductor device, the method comprising - introducing an additional channel dopant species ( 21 ) in a semiconductor layer ( 2 ); Forming a gate electrode structure ( 22a ) over the semiconductor layer ( 2 ), wherein the gate electrode structure ( 22a ) a gate dielectric material ( 3 ) and a gate electrode ( 22 ) with a gap ( 23 ) having; Implanting a well dopant species in the semiconductor layer ( 2 ) laterally adjacent to the gate electrode structure ( 22 ) and through the gap ( 23 ); Performing a first annealing process to create a contiguous well region ( 25 ); - forming a mask ( 11 ) above the gap ( 23 ); Implanting a source dopant species in the semiconductor layer ( 2 ) using the mask ( 11 ) and the gate electrode structure ( 22a ) as an implantation mask; Performing a second annealing process for diffusing a portion of the source dopant species below the gate electrode structure ( 22a ). The method of claim 16, wherein forming the gate electrode structure comprises depositing an electrode material on the gate dielectric material. 3 ) and structuring the electrode material such that the gap and at least one coupling region ( 23 ) passing through the gap ( 23 ) separate areas ( 22b . 22c ) of the gate electrode ( 22 ) is electrically connected. The method of claim 16, wherein forming the gate electrode structure comprises depositing an electrode material on the gate dielectric material and patterning the electrode material such that a first region and a second region are obtained which are electrically isolated from each other by the gap. The method of claim 18, further comprising: forming a connection structure in a wiring system of the semiconductor device such that the first and second regions are electrically connected. A method of fabricating a DMOS transistor, the method comprising Implanting a well dopant species into a semiconductor material in the presence of a gate electrode structure having at least one gap for incorporating a portion of the well dopant species into the semiconductor material through the at least one gap; Masking the at least one gap; - implanting a source dopant species into the semiconductor material in the presence of the gate electrode structure containing the at least one masked gap; Forming a well region and a source region by performing annealing processes to initiate diffusion of the well dopant species and the source dopant species. The method of claim 20, further comprising incorporating an additional channel dopant species prior to forming the gate electrode structure. Depletion mode DMOS transistor having a gate electrode structure formed on a semiconductor material and having a gate dielectric layer and an electrode, the electrode having a first electrode region and a second electrode region laterally separated by an insulating material, and with A source region of a first conductivity type formed in the semiconductor material partially below the first electrode region; An additionally doped channel region of the first conductivity type connected to the source region and extending below the first and second electrode regions along a current flow direction; A well region of a second conductivity type formed in the semiconductor material so as to be in contact with the source region, - wherein the additional channel region and a drift region have the first conductivity type; Wherein the well region extends laterally below the first and second electrode regions; A drain region of the first conductivity type provided in contact with the drift region.

Images