DE112008004033T5 - Virtualized Ecc Nand - Google Patents
Virtualized Ecc Nand Download PDFInfo
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- DE112008004033T5 DE112008004033T5 DE112008004033T DE112008004033T DE112008004033T5 DE 112008004033 T5 DE112008004033 T5 DE 112008004033T5 DE 112008004033 T DE112008004033 T DE 112008004033T DE 112008004033 T DE112008004033 T DE 112008004033T DE 112008004033 T5 DE112008004033 T5 DE 112008004033T5
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0625—Power saving in storage systems
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
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- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/325—Power saving in peripheral device
- G06F1/3275—Power saving in memory, e.g. RAM, cache
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- G—PHYSICS
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- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
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- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1044—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices with specific ECC/EDC distribution
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- G—PHYSICS
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- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk
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- G—PHYSICS
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- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1072—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in multilevel memories
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- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
- G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
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- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/52—Protection of memory contents; Detection of errors in memory contents
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
Ein einziger virtualisierter ECC-NAND-Controller führt einen ECC-Algorithmus aus und verwaltet einen Stapel von NAND-Flash-Speichern. Der virtualisierte ECC-NAND-Controller ermöglichtes dem Host-Prozessor einen Stapel von FlashSpeichergeräten als einen einzigen NAND-Chip zu betreiben, wobei der Controller die Daten zu dem ausgewählten NAND-Speichergerät in dem Stapel umleitet.A single virtualized ECC NAND controller executes an ECC algorithm and manages a stack of NAND flash memories. The virtualized ECC NAND controller enables the host processor to operate a stack of flash memory devices as a single NAND chip, with the controller redirecting the data to the selected NAND memory device in the stack.
Description
Heutige Kommunikationsgeräte werden immer komplizierter und diversifizieren sich bei der Bereitstellung von vermehrter Funktionalität. Diese Geräte unterstützen Multimedia-Anwendungen, die Speicher mit höherer Kapazität erfordern, insbesondere welche, die durch Multichip-Package-Designs benötigt werden. Kommunikationsverbindungen, Busse, Chip-zu-Chip-Verbindungen und Speichermedien können mit einem hohen Niveau an intrinsischem Signal/Speicherfehlern arbeiten. Von diesen Kommunikationsgeräten wird erwartet, dass sie Fehlererkennungs- und korrekturmechanismen beinhalten. ECC (Error Correction Codes, Fehlerkorrekturcodes) haben in Speicherstrukturen Einzug gehalten, jedoch werden zusätzliche Verbesserungen benötigt.Today's communication devices are becoming more and more complicated and diversify in providing increased functionality. These devices support multimedia applications that require higher capacity storage, especially those required by multi-chip package designs. Communication links, buses, chip-to-chip connections, and storage media can operate with a high level of intrinsic signal / memory errors. These communication devices are expected to include error detection and correction mechanisms. ECC (Error Correction Codes) have been incorporated into memory structures, but additional improvements are needed.
KURZE BESCHREIBUNG DER ZEICHNUNGENBRIEF DESCRIPTION OF THE DRAWINGS
Der als Erfindung betrachtete Gegenstand wird insbesondere durch den zusammenfassenden Teil der Beschreibung hervorgehoben und deutlich sichtbar beansprucht. Die Erfindung wird jedoch sowohl als Organisationsstruktur, als auch als Betriebsverfahren, zusammen mit Objekten, Merkmalen und Vorteilen davon am Besten verstanden werden, durch auf die folgende detaillierte Beschreibung, wenn sie mit den begleitenden Zeichnungen gelesen wird, in denen:The object considered as invention is particularly emphasized by the summary part of the description and claimed clearly visible. However, the invention will be best understood both as an organizational structure and method of operation, together with objects, features and advantages thereof, by reference to the following detailed description when read in conjunction with the accompanying drawings, in which:
Es sollte erkannt werden, dass für eine einfache und klare Darstellung Elemente, die in den Figuren illustriert sind, nicht notwendigerweise maßstabsgerecht gezeichnet sind. Beispielsweise könnten für eine klare Darstellung die Dimensionen von einigen der Elemente relativ zu den anderen Elementen übertrieben dargestellt sein. Weiterhin könnten, wo es geeignet erscheint, Bezugszeichen in den Figuren wiederholt werden, um entsprechende oder analoge Elemente zu bezeichnen.It should be appreciated that for ease of illustration, elements illustrated in the figures are not necessarily drawn to scale. For example, for clarity, the dimensions of some of the elements could be exaggerated relative to the other elements. Furthermore, where appropriate, reference numerals in the figures could be repeated to designate corresponding or analogous elements.
DETAILLIERTE BESCHREIBUNGDETAILED DESCRIPTION
In der folgenden detaillierten Beschreibung werden zahlreiche spezifische Details dargestellt, um ein tiefgreifendes Verständnis der Erfindung bereitzustellen. Jedoch sollte von den Fachleuten verstanden werden, dass die vorliegende Erfindung ohne diese spezifischen Details ausgeführt werden kann. In anderen Fällen wurden wohlbekannte Verfahren, Prozeduren, Komponenten und Schaltkreise nicht im Detail beschrieben, um nicht von der vorliegenden Erfindung abzulenken.In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, it should be understood by those skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail so as not to distract from the present invention.
Die Ausführungsform die in
Die Ausführungsform zeigt die Verbindung einer Antennenstruktur
Der Systemspeicher
Im Stand der Technik ist ein ECC(Fehlerkorrekturcode)-Algorithmus, der innerhalb eines NAND-Speichers durchgeführt wird, darauf beschränkt, Fehlererkennungs- und korrekturmechanismen bereitzustellen, die nur auf dieses einzelne Speichergerät anwendbar sind. Es ist aufwändig, eine feste Host-Plattform zu erneuern, um eine neue NAND-Technologie hinsichtlich der ECC-Anforderungen, Seitengröße, Adressierungsmöglichkeiten, neuen Befehlssatzspezifikationen, etc. zu erneuern. Weiter einschränkend ist, dass der ECC-Algorithmus technologiespezifisch ist. Beispielsweise würde ein Wechsel zwischen der Single Level Cell(SLC)-Technologie und der Multi Level Cell(MLC)-Technologie den verwendeten ECC-Algorithmus unbrauchbar machen. Zusätzlich würde ein Ersatzspeicher, welcher ein unterschiedliches Produktkompressionsniveau aufweist, Modifikationen an dem existierenden ECC-Algorithmus notwendig machen. Zusätzlich rufen aktuelle Speichergärte, die eine intern eingebaute ECC aufweisen, einen Kostennachteil hervor, basierend auf dem kombinierten Chipbereich für den Flash und die ECC-Algorithmuslogik.In the prior art, an ECC (error correction code) algorithm performed within a NAND memory is limited to providing error detection and correction mechanisms that are applicable only to this single memory device. It is costly to renew a fixed host platform to renew a new NAND technology in terms of ECC requirements, page size, addressing capabilities, new instruction set specifications, etc. Further limiting is that the ECC algorithm is technology specific. For example, switching between Single Level Cell (SLC) technology and Multi Level Cell (MLC) technology would render the ECC algorithm unusable. In addition, a spare memory having a different product compression level would necessitate modifications to the existing ECC algorithm. In addition, current memory levels that have an internally incorporated ECC cause a cost penalty based on the combined chip area for the flash and the ECC algorithm logic.
Um diese Nachteile zu überwinden und in Einklang mit der vorliegenden Erfindung, ermöglicht die Architektur, die in
Der virtualisierte ECC-NAND-Controller
Durch das Entfernen der ECC-Funktionalität von den individuellen NAND-Speichergeräten in dem NAND-Stapel und durch Einbringen dieser Funktionalität in den ECC-NAND-Controller
Produkte nach dem Stand der Technik implementieren ECC zusammen mit Datenmanagementalgorithmen, wie z. B. einem Flash Translation Layer (FTL), Wear Levelling, Bad Block Management, etc. innerhalb eines gemeinsamen integrierten Schaltkreises. Im Gegensatz dazu separiert die Architektur, die in den Figuren dargestellt ist, ECC von den Datenmanagementalgorithmen. Der virtualisierte ECC-NAND-Controller
Durch die Verwendung eines virtualisierten ECC-NAND-Controllers
Die
Gleichzeitig und ohne interne Logik der Host-Plattform hinzuzufügen, stellt das ECC-NAND
Weiterhin macht diese Architektur mit dem virtualisierten ECC-NAND-Controller
Beispielsweise kann, wenn das rohe NAND-Speichergerät nicht die Mehrebenenfunktionen unterstützt, der virtualisierte ECC-NAND-Controller
Die Protokoll-Schnittstelle
Die Größe des Puffers
Die ECC-Engine
Während einer Schreibeoperation berechnet der ECC-Algorithmus die Redundanz der Daten, die durch den Host gesendet werden. Die Redundanz wird, sobald sie berechnet ist, zu den Host-Daten hinzu addiert und zu dem NAND-Flash-Seitenpuffer transferriert. Während einer Leseoperation berechnet die NAND-Engine
Ein Lesefehler wird der Host-CPU
Das NAND-Schnittstelle
Während einer Leseoperation überträgt die NAND-Schnittstelle
Wenn die Protokollschnittstelle
Durch die Verwendung eines virtualisierten ECC-NAND-Controllers
Da neue Speichertechnologien die Anzahl der Bits, die in einer einzelnen Zelle gespeichert werden, vergrößert, vergrößert sich auch die Wahrscheinlichkeit von Lese-, Schreibe- und Speicherfehlern. Dies erfordert die Verwendung von vollständigeren ECC-Algorithmen, die Codes aufweisen mit einer verbesserten Korrekturleistung. Um diese technischen Schwierigkeiten zu lösen, sollte es nun offensichtlich sein, dass die dargestellten Ausführungsformen der vorliegenden Erfindung eine Architektur bereitstellen, in der ein einziger Controller einen Stapel von NAND-Flash-Speichern verwaltet, zusammen mit dem Ausführen des ECC-Algorithmus. Diese Architektur ermöglicht es der Host-CPU, ein einziges Speichersystem zu betreiben mit einem großen fehlerfreien Adressbereich, unter Verwendung eines Standard-NAND-Protokolls. Durch Anordnen der ECC-Korrekturmöglichkeit in dem externen Controller, können Änderungen an dem ECC-Algorithmus erleichtert werden, ohne Änderungen in der Flash-Maske hervorzurufen. Der externe Controller ermöglicht auch die Verwendung von unterschiedlichen Technologien für den Controller und die NAND-Speicher und ermöglicht Speichergeräte mit unterschiedlichen Kompressionsniveaus.As new storage technologies increase the number of bits stored in a single cell, the likelihood of read, write, and memory errors also increases. This requires the use of more complete ECC algorithms having codes with improved correction performance. To solve these technical difficulties, it should now be apparent that the illustrated embodiments of the present invention provide an architecture in which a single controller manages a stack of NAND flash memories, along with performing the ECC algorithm. This architecture allows the host CPU to operate a single memory system with a large error free address space using a standard NAND protocol. By placing the ECC correction capability in the external controller, changes to the ECC algorithm can be facilitated without causing changes in the flash mask. The external controller also allows the use of different technologies for the controller and the NAND memory and allows storage devices with different compression levels.
Während bestimmte Merkmale dieser Erfindung hierin dargestellt und beschrieben wurden, können Modifikationen, Ersetzungen, Änderungen und Äquivalente nun den Fachleuten in den Sinn kommen. Es sollte daher verstanden werden, dass die beiliegenden Ansprüche alle solche Modifikationen und Änderungen abdecken sollen, die unter den wahren Geist der Erfindung fallen.While certain features of this invention have been illustrated and described herein, modifications, substitutions, changes, and equivalents may now occur to those skilled in the art. It is therefore to be understood that the appended claims are intended to cover all such modifications and changes as fall within the true spirit of the invention.
Claims (20)
Applications Claiming Priority (1)
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PCT/IB2008/002658 WO2010041093A1 (en) | 2008-10-09 | 2008-10-09 | Virtualized ecc nand |
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DE112008004033T5 true DE112008004033T5 (en) | 2012-01-19 |
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DE112008004033T Ceased DE112008004033T5 (en) | 2008-10-09 | 2008-10-09 | Virtualized Ecc Nand |
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US (4) | US8806293B2 (en) |
JP (1) | JP5650116B2 (en) |
CN (1) | CN102272730B (en) |
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- 2008-10-09 CN CN200880131514.3A patent/CN102272730B/en active Active
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2014
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2015
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US8806293B2 (en) | 2008-10-09 | 2014-08-12 | Micron Technology, Inc. | Controller to execute error correcting code algorithms and manage NAND memories |
US9213603B2 (en) | 2008-10-09 | 2015-12-15 | Micron Technology, Inc. | Controller to manage NAND memories |
US9569129B2 (en) | 2008-10-09 | 2017-02-14 | Micron Technology, Inc. | Controller to manage NAND memories |
US9971536B2 (en) | 2008-10-09 | 2018-05-15 | Micron Technology, Inc. | Controller to manage NAND memories |
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US20110307762A1 (en) | 2011-12-15 |
JP2012505458A (en) | 2012-03-01 |
CN102272730A (en) | 2011-12-07 |
JP5650116B2 (en) | 2015-01-07 |
WO2010041093A1 (en) | 2010-04-15 |
WO2010041093A8 (en) | 2011-05-26 |
US9569129B2 (en) | 2017-02-14 |
US20160098223A1 (en) | 2016-04-07 |
US8806293B2 (en) | 2014-08-12 |
US20140351675A1 (en) | 2014-11-27 |
US9213603B2 (en) | 2015-12-15 |
US20170160973A1 (en) | 2017-06-08 |
US9971536B2 (en) | 2018-05-15 |
CN102272730B (en) | 2017-05-24 |
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