DE1108813B - Process for the production of large-area blocking and blocking-free contacts on semiconductor bodies - Google Patents

Process for the production of large-area blocking and blocking-free contacts on semiconductor bodies

Info

Publication number
DE1108813B
DE1108813B DEE18391A DEE0018391A DE1108813B DE 1108813 B DE1108813 B DE 1108813B DE E18391 A DEE18391 A DE E18391A DE E0018391 A DEE0018391 A DE E0018391A DE 1108813 B DE1108813 B DE 1108813B
Authority
DE
Germany
Prior art keywords
blocking
production
semiconductor bodies
area
grid
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
DEE18391A
Other languages
German (de)
Inventor
Dipl-Phys Gerhard Bollert
Walter Ramser
Dipl-Phys Dietrich Wieland
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Eberle & Koehler KG
Original Assignee
Eberle & Koehler KG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Eberle & Koehler KG filed Critical Eberle & Koehler KG
Priority to DEE18391A priority Critical patent/DE1108813B/en
Publication of DE1108813B publication Critical patent/DE1108813B/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/24—Alloying of impurity materials, e.g. doping materials, electrode materials, with a semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3205—Shape
    • H01L2224/32057—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01051—Antimony [Sb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Printing Plates And Materials Therefor (AREA)

Description

Verfahren zur Herstellung von großflächigen sperrenden und sperrfreien Kontakten an Halbleiterkörpern Die Erfindung betrifft ein Verfahren zur Herstellung von großflächigen sperrenden und sperrfreien Kontakten an Halbleiterkörpern das durch die Verwendung eines Druckstempels mit gerasteter Oberfläche gekennzeichnet ist.Process for the production of large-area locking and non-locking Contacts on Semiconductor Bodies The invention relates to a method for production of large-area blocking and non-blocking contacts on semiconductor bodies characterized by the use of a pressure stamp with a ratcheted surface is.

Es ist bekannt, zur Herstellung des sperrenden oder sperrfreien Kontaktes, Gold oder Aluminiumfolien auf den Halbleiterkörper, beispielsweise einen Siliziumkristall mit Hilfe einer Legierungsvorrichtung aufzulegieren. Bei diesen Verfahren macht sich die nicht einwandfreie Benetzung des Kristalls bei der Legierung großer Flächen nachteilig bemerkbar. Das Legieren erfolgt lückenhaft, und das Legierungsmaterial dringt ungleichmäßig in. den Halbleiterkörper ein. Da mit glatten Folien legiert wird, müssen hohe Ansprüche an die Genauigkeit der verwendeten Legierungsform gestellt werden. Durch die Verwendung von Graphit als Material für die Legierungsform und deren Druckstempel bereitet dieses Problem erhebliche Schwierigkeiten. Zur Herstellung einer einwandfreien Legierungsflüche muß die Folie beim Legierungsvorgang unter gleichmäßigen Druck gesetzt werden, was bei großen Flächen sehr genau bearbeitete Legierungsformen, Druckstempel und äußerst plangeschliffene Kristallscheiben voraussetzt. Bei dem Verfahren nach der Erfindung wird die glatte Ausführung des Druckstempels der Legierungsform vernnieden und statt dessen ein solcher mit einem Raster verwendet. Die Rasterung des Druckstempels der Legierungsform bewirkt, daß beim Legierungsvorgang das sich verflüssigende Legierungsmetall in den Vertiefungen des Rasters lokalisiert bleibt, wodurch ein Einlegieren nur an einigen wenigen Stellen weitgehend unterbunden wird. Der Legierungsvorgang erfolgt vielmehr der Feinheit der Rasterung entsprechend, an vielen Stellen gleichzeitig. Bei hinreichend feiner Rasterung schließen sich diese Stellen zu einer lückenlosen Fläche. Außerdem wird eine Diffusion des sich im Legierungsmetall lösenden Halbleitermaterials entlang der Oberfläche des Halbleiterkörpers behindert. Es werden somit nur geringe Genauigkeitsanforderungen an die Legierungsform, die Druckstempel derselben und den Kristall gestellt, da das Raster durch das Speichervermögen seiner Vertiefungen ausgleichend wirkt. Besonders vorteilhaft ist weiterhin, daß das Rastei mechanische Spannungen durch Auflösen der Oberfläche in viele Teilgebiete mildert. Bei dem erfindungsgemäßen Verfahren findet auch eine Vergrößerung der aktiven Fläche im Inneren des Kristalls durch die Abbildung des Rasters im Kristall statt. Die Erfindung sei an Hand eines Ausführungsbeispieles in den Figuren näher erläutert.It is known to produce blocking or blocking-free contact, Gold or aluminum foils on the semiconductor body, for example a silicon crystal to be alloyed with the help of an alloying device. In these procedures it makes the imperfect wetting of the crystal when alloying large areas disadvantageously noticeable. The alloying is incomplete, and the alloy material penetrates unevenly into the semiconductor body. Because it is alloyed with smooth foils high demands must be placed on the accuracy of the alloy form used will. By using graphite as the material for the alloy mold and their pressure stamp causes this problem considerable difficulties. For the production the foil must undergo proper alloying curse during the alloying process even pressure can be set, which worked very precisely on large areas Alloy shapes, stamps and extremely flat-ground crystal disks are required. In the method according to the invention, the smooth execution of the pressure stamp the alloy form and instead use one with a grid. The rasterization of the pressure stamp of the alloy shape causes that during the alloying process the liquefying alloy metal is located in the recesses of the grid remains, as a result of which alloying is largely prevented in only a few places will. The alloying process takes place according to the fineness of the grid, in many places at the same time. If the grid is sufficiently fine, they close these places to a gapless area. There will also be a diffusion of the self in the alloy metal dissolving semiconductor material along the surface of the semiconductor body with special needs. There are therefore only low accuracy requirements for the alloy form, the printing stamp of the same and the crystal placed, as the grid through the storage capacity its depressions has a balancing effect. It is also particularly advantageous that the Rastei mechanical tensions by dissolving the surface into many sub-areas mitigates. In the method according to the invention there is also an increase in the active Area inside the crystal is held by the image of the grid in the crystal. The invention will be explained in more detail using an exemplary embodiment in the figures.

Fig. 1 zeigt einen Schnitt durch eine Legierungsform, Fig. 2 eine Draufsicht auf ein gerastertes Druckstück und Fig. 3 ein vergrößertes Raster.Fig. 1 shows a section through an alloy mold, Fig. 2 shows a Top view of a rasterized pressure piece and FIG. 3 an enlarged raster.

Zwischen dem Druckstempel 1 und dem Boden 2 der Legierungsform befindet sich der zu kontaktierende Halbleiterkörper 3. Auf die dem Druckstempel l zugekehrte Seite des Halbleiterkörpers 3 wird beispielsweise eine Gold-Antimon-Folie 4 und zwischen der anderen Seite des Halbleiterkörpers 3 und dem Boden 2 der Legierungsform wird beispielsweise eine Aluminiumfolie 5 gelegt. Beim Legierungsvorgang werden die Raster 1 a und 2 a der Druckstempel l bzw. 2 auf dem Legierungsmaterial und in dem Halbleiterkristall abgebildet. Selbstverständlich können auch Folien aus anderem Material verwendet werden.Located between the plunger 1 and the bottom 2 of the alloy mold the semiconductor body 3 to be contacted is located on the one facing the pressure stamp l Side of the semiconductor body 3 is, for example, a gold-antimony foil 4 and between the other side of the semiconductor body 3 and the bottom 2 of the alloy mold For example, an aluminum foil 5 is placed. During the alloying process the grid 1 a and 2 a of the pressure stamp l and 2 on the alloy material and imaged in the semiconductor crystal. Of course, foils can also be made from other material can be used.

Claims (2)

PATENTANSPRÜCHE: 1. Verfahren zur Herstellung von großflächigen sperrenden und sperrfreien Kontakten an Halbleiterkörpern durch Auflegieren von Metallfolien mit Hilfe von Druckstempeln, gekenn-zeichnet durch die Verwendung eines Druckstempels mit gerasteter Oberfläche. PATENT CLAIMS: 1. Process for the production of large-area blocking and non-blocking contacts on semiconductor bodies by alloying metal foils with the aid of pressure stamps , characterized by the use of a pressure stamp with a latched surface. 2. Verfahren nach Anspruch 1, dadurch gekennzeichnet, daß die Rasterung als Waffel- oder Ring-Rasterung ausgeführt wird. In Betracht gezogene Druckschriften: Deutsche Auslegeschrift Nr. 1006 977; USA.-Patentschrift Nr. 2 791524.2. The method according to claim 1, characterized in that that the grid is carried out as a waffle or ring grid. Considered Publications: German Auslegeschrift No. 1006 977; U.S. Patent No. 2,791,524.
DEE18391A 1959-10-22 1959-10-22 Process for the production of large-area blocking and blocking-free contacts on semiconductor bodies Pending DE1108813B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
DEE18391A DE1108813B (en) 1959-10-22 1959-10-22 Process for the production of large-area blocking and blocking-free contacts on semiconductor bodies

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DEE18391A DE1108813B (en) 1959-10-22 1959-10-22 Process for the production of large-area blocking and blocking-free contacts on semiconductor bodies

Publications (1)

Publication Number Publication Date
DE1108813B true DE1108813B (en) 1961-06-15

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DEE18391A Pending DE1108813B (en) 1959-10-22 1959-10-22 Process for the production of large-area blocking and blocking-free contacts on semiconductor bodies

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2926756A1 (en) * 1979-07-03 1981-01-15 Licentia Gmbh SCHOTTKY DIODE ARRANGEMENT

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1006977B (en) * 1954-06-29 1957-04-25 Gen Electric Process for the production of semiconductor devices with an inversion layer
US2791524A (en) * 1953-04-03 1957-05-07 Gen Electric Fabrication method for p-n junctions

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2791524A (en) * 1953-04-03 1957-05-07 Gen Electric Fabrication method for p-n junctions
DE1006977B (en) * 1954-06-29 1957-04-25 Gen Electric Process for the production of semiconductor devices with an inversion layer

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2926756A1 (en) * 1979-07-03 1981-01-15 Licentia Gmbh SCHOTTKY DIODE ARRANGEMENT
US4748483A (en) * 1979-07-03 1988-05-31 Higratherm Electric Gmbh Mechanical pressure Schottky contact array

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