DE1076179B - Method and circuit arrangement for storing and retrieving information content in or from memory matrix arrangements - Google Patents

Description

GERMAN

KL.21ai

INTERNAT. KX. H 03 k

PATENT OFFICE

St 13098

REGISTRATION DATE: OCTOBER 26, 1957

NOTICE
THE REGISTRATION
AND ISSUE OF THE
EDITORIAL: FEBRUARY 25, 1960

The invention relates to a method for storing and removing information content in or from memory matrix arrangements. It relates to memory matrices which are made up of memories which can assume two stable switching states and which can be tilted by pulses of a certain amplitude value, but not tiltable by pulses of an amplitude value which only has half the intensity of the effect on the memory ^; · ' are. Such memories are, for example, ferrite core memories, electromagnetic relays of suitable construction, which certainly did not respond to half the response current value, or bistable arrangements of electronic or other power supply units, ° - 'which are capable of alternately assuming two defined states and maintaining them until they are reversed.

In known arrangements of this type, a specific memory element is marked by simultaneous identification of the assigned abscissa and ordinate line to the memory element in the matrix by one pulse each. Here the difficulty arises of applying pulses of a very short duration down to about 5 \ xs when using ferrite core memories on two lines at the same time. Particularly in the case of arrangements in which conventional electromagnetic and / or mechanical switching means are used in addition to electronic ones, it is difficult to maintain the simultaneity of the pulses with the required high accuracy.

According to the invention it is proposed to use the same pulse source as the pulse source for both pulses, for the pulse to be applied to the abscissa line as well as for the pulse to be applied to the ordinate line, and a suitable circuit arrangement is given as an exemplary embodiment. Although it is known to mark one coordinate line of several ferrite core stores assigned to this coordinate line by means of an impressed pulse, in the known arrangement a special pulse source is provided for each coordinate line. The method according to the invention is accordingly characterized in that the corresponding abscissa and ordinate lines provided for identifying certain memories are each simultaneously supplied with a marking pulse generated in a common pulse generator for the purpose of switching the memories. The circuit arrangement for carrying out the method according to the invention is characterized in that switching means are provided which enable one or more memories of the matrix to be identified and in the method and circuit arrangement
for injection and withdrawal

of information content
in or out of memory array arrays

Applicant:

Standard electrical system Lorenz

Corporation,

Stuttgart-Zuffenhausen,

Hellmuth-Hirth-Str. 42

Dipl.-Ing. Werner Lange, Gerlingen via Stuttgart,
has been named as the inventor

Selected abscissa and ordinate lines of the same currents exerted on the memory to be identified Produce intensity of effect.

The advantage of the method according to the invention is not only the absolutely reliable guarantee that the Marking pulses are present at the same time on the marked memory element; it also results still a saving in pulse sources.

The drawing shows an example of a circuit arrangement for carrying out the method according to the invention, in which the memories are indicated as ferrite cores in the form of a ring of known embodiment and are arranged in the form of a matrix. To identify certain storage elements abscissa lines al ... an and ordinate lines oil ... on are provided, which, for example, through contacts zl ... zn, si. . . sη can be connected to a pulse generator. The mechanical contacts zl ... zn, si ... s η can also be controlled by electronic switching means, such as B. switching transistors, be replaced without thereby exceeding the scope of the invention.

In the exemplary embodiment according to the drawing, the pulse generator is shown as a capacitor C charged by a voltage source U via a series resistor R , which is connected to the contact part leading to the abscissa and ordinate lines through a pulse contact i. . . sn, zl ... zn can be created.

909 757/336

In the example according to the drawing, the ferrite cores are drawn onto the abscissa and ordinate lines, so that a marked storage core is subjected to a pulse current whose intensity is twice as great as that of the pulse current acting on all other storage cores assigned to the same coordinate line. To ensure the same current strengths in the coordinate lines, the resistors Wi are all provided with the same resistance value within narrow tolerances.

To ensure that the capacitor C is charged to an always constant voltage regardless of battery voltage fluctuations, a Zener diode is connected in parallel to it with a forward voltage of the appropriate size.

The exemplary embodiment according to the invention shows a memory arrangement in which a plurality of memory elements can throw marked at the same time. However, the invention can also be used for arrangements in which only one storage element can be marked.

Claims (3)

Patent claims: 1. Procedure for. Storage and retrieval of information content in or from storage matrix arrangements, which are made up of memories which assume two stable switching states can and can be tilted by pulses of a certain amplitude value, by pulses of a Amplitude value that affects the memory only that exerts half the intensity of action, but cannot be tilted, characterized in that the corresponding abscissa (al ... an) and ordinate lines (oil ... on) provided for the identification of certain memories each simultaneously receive a marking pulse from a common pulse generator (U , C, i) is supplied. 2. Circuit arrangement for performing the method according to claim 1, characterized in that switching means (contacts si ... sn, zl ... zn and resistors Wi) are provided, which enable the identification of one or more memories of the matrix and in the selected ones abscissa (al .. .an) and Ordinatenleitungen (oil on ...) currents of the same cause on the pressure applied to characterizing memory effect intensity. 3. Circuit arrangement for performing the method according to claim 1 or 2, characterized in that that the capacitor (C) provided in the pulse generator has a Zener diode (Z) with a forward voltage value in parallel is switched, which is the same voltage to which the capacitor is charged during operation will. Considered publications:
German interpretation document J 9062 VIII a / 21a ¹
made known on July 5, 1956). 1 sheet of drawings © 909 7577336 2.60