DE10345163A1 - Verfahren und Vorrichtung zur Frequenzteilung und zum Demultiplexen - Google Patents

Verfahren und Vorrichtung zur Frequenzteilung und zum Demultiplexen Download PDF

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Publication number
DE10345163A1
DE10345163A1 DE10345163A DE10345163A DE10345163A1 DE 10345163 A1 DE10345163 A1 DE 10345163A1 DE 10345163 A DE10345163 A DE 10345163A DE 10345163 A DE10345163 A DE 10345163A DE 10345163 A1 DE10345163 A1 DE 10345163A1
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DE
Germany
Prior art keywords
output clock
phase difference
clock signals
frequency division
demultiplexing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
DE10345163A
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English (en)
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DE10345163B4 (de
Inventor
Dirk Scheideler
Philipp Boerker
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Infineon Technologies AG
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Infineon Technologies AG
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Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Priority to DE10345163A priority Critical patent/DE10345163B4/de
Priority to US10/953,241 priority patent/US7215163B2/en
Publication of DE10345163A1 publication Critical patent/DE10345163A1/de
Application granted granted Critical
Publication of DE10345163B4 publication Critical patent/DE10345163B4/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/002—Switching arrangements with several input- or output terminals
    • H03K17/007—Switching arrangements with several input- or output terminals with several outputs only

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

Es wird ein Verfahren zur Frequenzteilung eines Eingangstaktsignals (d) vorgeschlagen, wobei aus dem Eingangstaktsignal mindestens zwei Ausgangstaktsignale (t1, t2) mit einer Ausgangstaktfrequenz gleich einer, um einen vorgegebenen Faktor geteilten Eingangstaktfrequenz erzeugt werden, wobei mit einem Phasendetektor (5) eine Phasendifferenz zwischen den mindestens zwei Ausgangstaktsignalen (t1, t2) gemessen wird und jedes der mindestens zwei Ausgangstaktsignale (t1, t2) in Abhängigkeit von der ermittelten Phasendifferenz entweder invertiert wird oder nicht invertiert wird. Ein derartiges Verfahren eignet sich insbesondere zum Demultiplexen eines Eingangsdatensignals (d) und kann auch mehrstufig ausgeführt werden.
DE10345163A 2003-09-29 2003-09-29 Verfahren und Vorrichtung zur Frequenzteilung und zum Demultiplexen Expired - Fee Related DE10345163B4 (de)

Priority Applications (2)

Application Number Priority Date Filing Date Title
DE10345163A DE10345163B4 (de) 2003-09-29 2003-09-29 Verfahren und Vorrichtung zur Frequenzteilung und zum Demultiplexen
US10/953,241 US7215163B2 (en) 2003-09-29 2004-09-29 Method and device for frequency division and demultiplexing

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE10345163A DE10345163B4 (de) 2003-09-29 2003-09-29 Verfahren und Vorrichtung zur Frequenzteilung und zum Demultiplexen

Publications (2)

Publication Number Publication Date
DE10345163A1 true DE10345163A1 (de) 2005-04-28
DE10345163B4 DE10345163B4 (de) 2005-09-08

Family

ID=34399025

Family Applications (1)

Application Number Title Priority Date Filing Date
DE10345163A Expired - Fee Related DE10345163B4 (de) 2003-09-29 2003-09-29 Verfahren und Vorrichtung zur Frequenzteilung und zum Demultiplexen

Country Status (2)

Country Link
US (1) US7215163B2 (de)
DE (1) DE10345163B4 (de)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7956665B2 (en) * 2008-02-29 2011-06-07 Qimonda Ag Methods and articles of manufacture for operating electronic devices on a plurality of clock signals

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0226754A2 (de) * 1985-12-24 1987-07-01 ANT Nachrichtentechnik GmbH Schaltungsanordnung zur Erzeugung mehrerer Takte
JPH03172034A (ja) * 1989-11-30 1991-07-25 Toshiba Corp データ多重化装置およびデータ分離化装置
US5128940A (en) * 1989-09-11 1992-07-07 Kabushiki Kaisha Toshiba Demultiplexer
JPH09284246A (ja) * 1996-04-11 1997-10-31 Nec Corp デマルチプレクサ
US20030174798A1 (en) * 2002-03-18 2003-09-18 Pickering Andrew J. High speed parallel link receiver

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS577634A (en) * 1980-06-16 1982-01-14 Victor Co Of Japan Ltd Frequency dividing circuit

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0226754A2 (de) * 1985-12-24 1987-07-01 ANT Nachrichtentechnik GmbH Schaltungsanordnung zur Erzeugung mehrerer Takte
US5128940A (en) * 1989-09-11 1992-07-07 Kabushiki Kaisha Toshiba Demultiplexer
JPH03172034A (ja) * 1989-11-30 1991-07-25 Toshiba Corp データ多重化装置およびデータ分離化装置
JPH09284246A (ja) * 1996-04-11 1997-10-31 Nec Corp デマルチプレクサ
US20030174798A1 (en) * 2002-03-18 2003-09-18 Pickering Andrew J. High speed parallel link receiver

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
LANG,M. u.a.: 20-40 Gb/s 0.2um GaAs HEMT Chip Set for Optical Data Receiver. In: IEEE Journal of Solid-State Circuits. September 1997, Vol.32, Nr. 9, S.1384-1393 *
THIEDE,A. u.a.: Mixed Signal Integrated Circuits Based on GaAs HEMT's. In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. März 1998, Vol.6, No.1, S.6-17 *

Also Published As

Publication number Publication date
US20050134333A1 (en) 2005-06-23
US7215163B2 (en) 2007-05-08
DE10345163B4 (de) 2005-09-08

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Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
8364 No opposition during term of opposition
R119 Application deemed withdrawn, or ip right lapsed, due to non-payment of renewal fee