DE10344356A1 - Integrated semiconductor memory e.g. for manufacture of chips such as DRAMs, has established organizational forms for data outputs - Google Patents

Integrated semiconductor memory e.g. for manufacture of chips such as DRAMs, has established organizational forms for data outputs Download PDF

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Publication number
DE10344356A1
DE10344356A1 DE2003144356 DE10344356A DE10344356A1 DE 10344356 A1 DE10344356 A1 DE 10344356A1 DE 2003144356 DE2003144356 DE 2003144356 DE 10344356 A DE10344356 A DE 10344356A DE 10344356 A1 DE10344356 A1 DE 10344356A1
Authority
DE
Germany
Prior art keywords
input terminal
data outputs
semiconductor memory
integrated semiconductor
drams
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
DE2003144356
Other languages
German (de)
Inventor
Graf V Keyserlingk
Helge Altfeld
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Priority to DE2003144356 priority Critical patent/DE10344356A1/en
Publication of DE10344356A1 publication Critical patent/DE10344356A1/en
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1045—Read-write mode select circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits

Abstract

An integrated semiconductor memory/store with established organizational forms for data outputs, has several output terminals (A1-An), an input terminal (1), a storage cells field (500) which is connected to output terminals (A1-An) depending on the organizational form for the data output, via a controlled switch (600), and a memory circuit (300) with a programmable element (101,102), in which the state of the programmable element is programmable by the input terminal taken through the housing, and a control circuit with an input terminal (23) and an input terminal (7) through which depending on the signal at the input terminal (SP1,SP2), a control signal (ST) is generated and determines the organization form for the data outputs.
DE2003144356 2003-09-24 2003-09-24 Integrated semiconductor memory e.g. for manufacture of chips such as DRAMs, has established organizational forms for data outputs Ceased DE10344356A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
DE2003144356 DE10344356A1 (en) 2003-09-24 2003-09-24 Integrated semiconductor memory e.g. for manufacture of chips such as DRAMs, has established organizational forms for data outputs

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE2003144356 DE10344356A1 (en) 2003-09-24 2003-09-24 Integrated semiconductor memory e.g. for manufacture of chips such as DRAMs, has established organizational forms for data outputs

Publications (1)

Publication Number Publication Date
DE10344356A1 true DE10344356A1 (en) 2005-04-28

Family

ID=34398914

Family Applications (1)

Application Number Title Priority Date Filing Date
DE2003144356 Ceased DE10344356A1 (en) 2003-09-24 2003-09-24 Integrated semiconductor memory e.g. for manufacture of chips such as DRAMs, has established organizational forms for data outputs

Country Status (1)

Country Link
DE (1) DE10344356A1 (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030026159A1 (en) * 2001-07-31 2003-02-06 Infineon Technologies North America Corp. Fuse programmable I/O organization
US6622197B1 (en) * 1999-06-17 2003-09-16 Samsung Electronics Co., Ltd. Dynamic random access memory device capable of programming a refresh period and a bit organization

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6622197B1 (en) * 1999-06-17 2003-09-16 Samsung Electronics Co., Ltd. Dynamic random access memory device capable of programming a refresh period and a bit organization
US20030026159A1 (en) * 2001-07-31 2003-02-06 Infineon Technologies North America Corp. Fuse programmable I/O organization

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Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
8131 Rejection