DE10342776A1 - Method for determination of correction values for positioning semiconductor wafer in photolithographic projection device uses adjustment markings covered during application of metal layer to substrate surface - Google Patents

Method for determination of correction values for positioning semiconductor wafer in photolithographic projection device uses adjustment markings covered during application of metal layer to substrate surface Download PDF

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Publication number
DE10342776A1
DE10342776A1 DE10342776A DE10342776A DE10342776A1 DE 10342776 A1 DE10342776 A1 DE 10342776A1 DE 10342776 A DE10342776 A DE 10342776A DE 10342776 A DE10342776 A DE 10342776A DE 10342776 A1 DE10342776 A1 DE 10342776A1
Authority
DE
Germany
Prior art keywords
semiconductor wafer
metal layer
substrate surface
determination
projection device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
DE10342776A
Other languages
German (de)
Other versions
DE10342776B4 (en
Inventor
Jens Staecker
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qimonda AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Priority to DE10342776A priority Critical patent/DE10342776B4/en
Publication of DE10342776A1 publication Critical patent/DE10342776A1/en
Application granted granted Critical
Publication of DE10342776B4 publication Critical patent/DE10342776B4/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
    • G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
    • G03F9/7073—Alignment marks and their environment
    • G03F9/7076—Mark details, e.g. phase grating mark, temporary mark
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
    • G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
    • G03F9/7073—Alignment marks and their environment
    • G03F9/708—Mark formation
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
    • G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
    • G03F9/7073—Alignment marks and their environment
    • G03F9/7084—Position of mark on substrate, i.e. position in (x, y, z) of mark, e.g. buried or resist covered mark, mark on rearside, at the substrate edge, in the circuit area, latent image mark, marks in plural levels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54493—Peripheral marks on wafers, e.g. orientation flats, notches, lot number
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

The method has the surface of a semiconductor wafer substrate provided with an array of circuit structures, each having adjustment markings (27) at the edges of an exposure field, at least 2 cover surfaces applied to the upper side of the semiconductor wafer (10) so that at least 2 adjustment markings are covered, before deposition of a metal layer (35) on the substrate surface, with subsequent removal of the cover surfaces for allowing the revealed adjustment markings to be used for determining the required correction of the semiconductor wafer position.
DE10342776A 2003-09-16 2003-09-16 Method for determining correction values for the adjustment of a semiconductor wafer in a projection apparatus for the photolithographic structuring of a metal layer Expired - Fee Related DE10342776B4 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
DE10342776A DE10342776B4 (en) 2003-09-16 2003-09-16 Method for determining correction values for the adjustment of a semiconductor wafer in a projection apparatus for the photolithographic structuring of a metal layer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE10342776A DE10342776B4 (en) 2003-09-16 2003-09-16 Method for determining correction values for the adjustment of a semiconductor wafer in a projection apparatus for the photolithographic structuring of a metal layer

Publications (2)

Publication Number Publication Date
DE10342776A1 true DE10342776A1 (en) 2005-04-21
DE10342776B4 DE10342776B4 (en) 2008-09-04

Family

ID=34352867

Family Applications (1)

Application Number Title Priority Date Filing Date
DE10342776A Expired - Fee Related DE10342776B4 (en) 2003-09-16 2003-09-16 Method for determining correction values for the adjustment of a semiconductor wafer in a projection apparatus for the photolithographic structuring of a metal layer

Country Status (1)

Country Link
DE (1) DE10342776B4 (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07161600A (en) * 1993-12-02 1995-06-23 Sony Corp Position measuring method
US5456756A (en) * 1994-09-02 1995-10-10 Advanced Micro Devices, Inc. Holding apparatus, a metal deposition system, and a wafer processing method which preserve topographical marks on a semiconductor wafer
FR2739975A1 (en) * 1995-10-16 1997-04-18 Sgs Thomson Microelectronics Semiconductor components on silicon wafer manufacturing method
US6171453B1 (en) * 1998-12-02 2001-01-09 Taiwan Semiconductor Manufacturing Co., Ltd Alignment mark shielding ring and method of using
US6492269B1 (en) * 2001-01-08 2002-12-10 Taiwan Semiconductor Manufacturing Company Methods for edge alignment mark protection during damascene electrochemical plating of copper

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07161600A (en) * 1993-12-02 1995-06-23 Sony Corp Position measuring method
US5456756A (en) * 1994-09-02 1995-10-10 Advanced Micro Devices, Inc. Holding apparatus, a metal deposition system, and a wafer processing method which preserve topographical marks on a semiconductor wafer
FR2739975A1 (en) * 1995-10-16 1997-04-18 Sgs Thomson Microelectronics Semiconductor components on silicon wafer manufacturing method
US6171453B1 (en) * 1998-12-02 2001-01-09 Taiwan Semiconductor Manufacturing Co., Ltd Alignment mark shielding ring and method of using
US6492269B1 (en) * 2001-01-08 2002-12-10 Taiwan Semiconductor Manufacturing Company Methods for edge alignment mark protection during damascene electrochemical plating of copper

Also Published As

Publication number Publication date
DE10342776B4 (en) 2008-09-04

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Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
8127 New person/name/address of the applicant

Owner name: QIMONDA AG, 81739 MUENCHEN, DE

8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee