DE10327882A1 - Improved reliability of solder link at semiconductor products with ball grid array (BGA) or similar components, with substrate locating chips secured by die-attach material, with substrate coated with solder stop lacquer on ball side - Google Patents
Improved reliability of solder link at semiconductor products with ball grid array (BGA) or similar components, with substrate locating chips secured by die-attach material, with substrate coated with solder stop lacquer on ball side Download PDFInfo
- Publication number
- DE10327882A1 DE10327882A1 DE10327882A DE10327882A DE10327882A1 DE 10327882 A1 DE10327882 A1 DE 10327882A1 DE 10327882 A DE10327882 A DE 10327882A DE 10327882 A DE10327882 A DE 10327882A DE 10327882 A1 DE10327882 A1 DE 10327882A1
- Authority
- DE
- Germany
- Prior art keywords
- solder
- substrate
- ball
- bga
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
- H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3452—Solder masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/099—Coating over pads, e.g. solder resist partly over pads
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/05—Patterning and lithography; Masks; Details of resist
- H05K2203/0562—Details of resist
- H05K2203/0594—Insulating resist or coating with special shaped edges
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
Description
Die Erfindung betrifft eine Anordnung zur Verbesserung der Zuverlässigkeit von Lötverbindungen an Halbleiterprodukten mit BGA- oder BGA-ähnlichen Komponenten mit einem Substrat, auf dem Chips mit einem Die-Attach-Material befestigt sind, wobei das Substrat zumindest auf der Ballseite mit einem Lötstopplack beschichtet ist und auf der dem Chip gegenüber liegenden Seite mit auf Kontaktpads montierten Lötkugeln zur elektrischen Verbindung mit Leiterplatten versehen ist und wobei das Chip und das Substrat auf der Chipseite mit einer Moldkappe verkapselt sind, sowie der Bondkanal ebenfalls mit einem Moldcompound ausgefüllt ist.The The invention relates to an arrangement for improving the reliability of solder joints Semiconductor products with BGA or BGA-like components with a Substrate, mounted on the chip with a die-attach material are, wherein the substrate at least on the ball side with a Lötstopplack is coated and on the opposite side of the chip with Contact pads mounted solder balls is provided for electrical connection with circuit boards and wherein the chip and the substrate on the chip side encapsulated with a mold cap are, as well as the bonding channel is also filled with a molding compound.
Derartige
substratbasierte IC-Packages werden auch als BGA-Package bezeichnet, wobei BGA für Ball Grid
Array steht. Aus der
Bei solchen substratbasierten Packages dient die Moldkappe (Abdeckmaterial bzw. Moldcompound), die aus einem Kunststoffmaterial besteht, dem Schutz des Chips und insbesondere dem Schutz der Chip-Kanten. Risse oder sonstige mechanische Beschädigungen, die durch das Handling während des Back End Prozesses oder auch beim Kunden verursacht werden können, würden sich auch auf die aktive Chipseite auswirken. Die Moldkappe umhüllt dabei die Chiprückseite und angrenzende Bereiche des Substrates, so dass ein hinreichender Schutz der empfindlichen Chipkanten erreicht wird.at such substrate-based packages is the mold cap (cover material or Mold compound), which consists of a plastic material, the Protection of the chip and in particular the protection of the chip edges. cracks or other mechanical damage, by the handling during The back-end process, or even the customer, could become too affect the active chip side. The mold cap envelops it the back of the chip and adjacent areas of the substrate, so that a sufficient Protection of the sensitive chip edges is achieved.
Bei
diesen Packages kann das Chip auf unterschiedliche Art und Weise
auf dem Substrat fixiert werden. So werden die Chips üblicher
Weise mittels eines Tapes oder eines gedruckten oder dispensten Klebers
unter Ausübung
einer ausreichenden Andruckkraft befestigt. Besonders effektiv ist
es, den Kleber unter Zwischenlage einer Druckschablone auf das Substrat
zu drucken und anschließend
das Chip auf das Substrat zu kleben. Danach erfolgt eine elektrischen
Verbindung der Bondpads der Chips mit Kontaktpads auf dem PCB mit
Hilfe von Drahtbrücken,
die durch einen Bondkanal im PCB gezogen werden. Der Bondkanal wird
anschließend
zum Schutz der Drahtbrücken
mit einem Moldcompound ausgefüllt
(One Step Molding) (
Unter den bereits genannten Matrixsubstraten werden Substrate verstanden, die zur Aufnahme einer Mehrzahl von Chips nebeneinander vorgesehen sind.Under the already mentioned matrix substrates are understood as substrates, provided for receiving a plurality of chips side by side are.
Bei
diesen substratbasierten Packages für integrierte Schaltkreise,
insbesondere bei Ball Grid Arrays mit Rückseitenschutz, bestehen nach
wie vor Schwierigkeiten in Bezug auf die Zuverlässigkeit. Das bezieht sich
insbesondere auf die Thermozyklen auf Modulebene. Die daraus verursachten
Ausfälle entstehen
insbesondere durch Abrisse der Lötkugeln beim
Thermozyklen, also beim Testen der Packages und auch beim normalen
Gebrauch. Diese Risse werden durch Bewegungen entlang der Lötstopp-Maskenkante
während
des Temperaturwechsels induziert (
Diese Abrisse der Lötkugeln resultieren also im wesentlichen aus den unterschiedlichen Ausdehnungskoeffizienten der einzelnen Komponenten des Packages (Chip, Lötstopplack, PCB und Leiterplatte im Makrobereich). Dieses Problem wirkt sich insbesondere bei sehr großen Chips aus, da hier die Kräfte auf die Lötkugeln in kritischen Positionen besonders groß sind.These Tear off the solder balls thus result essentially from the different expansion coefficients of the individual components of the package (chip, solder mask, PCB and PCB in the Macro range). This problem affects especially for very large chips out, because here are the forces on the solder balls are particularly large in critical positions.
Zur Reduzierung dieser Probleme wurde versucht, durch Designänderungen beim Ballout des Packages (spezielle Lötstoppmasken, bzw. Gestaltung der Lötpads) vorzunehmen und alternativ bzw. zusätzlich optimierte Montagematerialien zu verwenden. Es ist allerdings schon aus Zeitgründen nicht möglich, eine ständige Anpassung der Montagematerialien an die Chipgröße vorzunehmen, da die Anpassung von Materialien immer eine sehr große Vorlaufzeit erfordert. Wird zur Umgehung dieser Schwierigkeiten die Lötstoppmaske vom Pad zurückgezogen, also ein größerer Bereich frei gelassen, als durch die Lötkugel benötigt, oder ganz weggelassen, so entsteht das Risiko einer Fehlzentrierung der aufgebrachten Lötkugel durch Bewegung im Lötofen, oder eines Mismatches beim Aufsetzen der Lötkugel. Des weiteren kann das Pad und der hinzuführende Leiterzug vom Substrat-Basismaterial abgelöst werden.to Reduction of these problems was attempted through design changes at the Ballout of the package (special solder masks, or design the soldering pads) and alternatively or additionally optimized assembly materials to use. However, it is not possible for reasons of time, a permanent Adjusting the mounting materials to the chip size, since the adjustment of materials always requires a very long lead time. Becomes to avoid these difficulties, retract the solder mask from the pad, So a larger area left free, as by the solder ball needed or omitted entirely, the risk of incorrect centering arises the applied solder ball by movement in the soldering oven, or a mismatch when placing the solder ball. Furthermore, that can Pad and the leading circuit detached from the substrate base material become.
Der Erfindung liegt daher die Aufgabe zugrunde, ein substratbasiertes Package für integrierte Schaltkreise zu schaffen, bei den bei Temperaturwechselbelastungen auf die Lötkugeln einwirkenden Stress zu reduzieren.Of the The invention is therefore based on the object, a substrate-based Package for to create integrated circuits in the case of thermal cycling on the solder balls reduce stress.
Die der Erfindung zugrunde liegende Aufgabenstellung wird bei einer Anordnung zur Verbesserung der Zuverlässigkeit von Lötverbindungen an Halbleiterprodukten mit BGA- oder BGA-ähnlichen Komponenten mit einem Substrat, auf dem Chips mit einem Die-Attach-Material befestigt sind, wobei das Substrat zumindest auf der Ballseite mit einem Lötstopplack beschichtet ist und auf der dem Chip gegenüber liegenden Seite mit auf Kontaktpads montierten Lötkugeln zur elektrischen Verbindung mit Kontaktpads auf Leiterplatten versehen ist und wobei das Chip und das Substrat auf der Chipseite mit einer Moldkappe versehen sind, dadurch gelöst, dass die im Bereich des Kontaktpads die Lötkugeln umgebenden Strukturen des Lötstopp-Lackes derart verändert sind, dass die Spannungen aus der Lötkugel gegen gesoftete Kanten des Lötstopp-Lackes laufen, so dass der mechanische Stress deutlich verringert wird.The object underlying the invention is in an arrangement for improving the reliability of solder joints on semiconductor products with BGA or BGA-like Components with a substrate, are mounted on the chips with a die attach material, wherein the substrate is coated at least on the ball side with a solder resist and on the chip side opposite with solder pads mounted on contact pads for electrical connection to contact pads on printed circuit boards is provided and wherein the chip and the substrate are provided on the chip side with a mold cap, achieved in that surrounding the solder balls in the region of the contact pads structures of the solder resist are changed so that the voltages from the solder ball against softened edges of the solder stop -Lackes run, so that the mechanical stress is significantly reduced.
Durch diese erfindungsgemäße Lösung wird eine Reduzierung des auf die einzelnen Lötkugeln einwirkenden mechanischen Stresses durch den Abbau stressinduzierender Strukturen erreicht. Weiterhin wird durch die Erfindung eine höhere Positioniergenauigkeit beim Ball-Out gewährleistet.By this solution according to the invention becomes a Reduction of mechanical forces acting on individual solder balls Stresses achieved by breaking down stress-inducing structures. Furthermore, the invention provides a higher positioning accuracy guaranteed at the ball-out.
Vorzugsweise wird die Kante des an die Lötkugel angrenzenden Lötstopp-Lackes derart modifiziert, dass die während des Temperaturwechsels auftretende Bewegung des Lötkugel keine feste Kante trifft.Preferably gets the edge of the solder ball adjacent solder-resist paint modified so that during the temperature change occurring movement of the solder ball no solid edge hits.
In einer weiteren Fortführung der Erfindung wird das dadurch erreicht, dass die an die Lötkugel angrenzende Flanke des Lötstopp-Lackes in einem kleinen Winkel ansteigt.In another continuation the invention is achieved in that the adjacent to the solder ball Flank of the solder-stop varnish rises at a small angle.
Die Flanke des Lötstopp-Lackes kann auch eine strukturierte Oberfläche aufweisen, wie beispielsweise eine wellige Oberfläche.The Flank of the solder-stop varnish may also have a textured surface, such as a wavy surface.
Eine besondere Variante der Erfindung ist dadurch gekennzeichnet, dass die an die Lötkugel angrenzende Flanke des Lötstopp-Lackes abgerundet ist.A particular variant of the invention is characterized in that the one adjacent to the solder ball Flank of the solder-stop varnish is rounded.
Besonders beachtenswert ist, dass die aufgezeigte erfindungsgemäße Möglichkeit zur Reduzierung des auf die Lötkugeln einwirkenden Stresses sowohl auf der Seite der Halbleiterkomponente, als auch auf der Seite der die Halbleiterkomponenten tragenden Leiterplatte eingesetzt werden kann.Especially It is noteworthy that the indicated possibility according to the invention to reduce the on the solder balls acting stress both on the side of the semiconductor component, as well as on the side of the semiconductor components supporting circuit board can be used.
Die Erfindung soll nachfolgend an Ausführungsbeispielen näher erläutert werden. In den zugehörigen Zeichnungen zeigen:The Invention will be explained in more detail below by exemplary embodiments. In the associated Drawings show:
In
Die
Flanke des Keiles
In
einer weiteren Ausgestaltung der Erfindung ist die an die Lötkugel
Die Realisierung der Erfindung ist durch einfache übliche Ätzverfahren problemlos möglich.The Realization of the invention is easily possible by simple conventional etching.
- 11
- BGA-ModulBGA module
- 22
- Substratsubstratum
- 33
- Chipchip
- 44
- Die-Attach-MaterialDie attach material
- 55
- Lötstopp-LackSolder resist
- 66
- Lötkugelsolder ball
- 77
- Leitbahninterconnect
- 88th
- Drahtbrückejumper
- 99
- BondkanalBond channel
- 1010
- Glob-TopGlob top
- 1111
- Moldkappemold cap
- 1212
- Leiterplattecircuit board
- 1313
- Kanteedge
- 1414
- Keilwedge
Claims (6)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10327882A DE10327882A1 (en) | 2003-06-19 | 2003-06-19 | Improved reliability of solder link at semiconductor products with ball grid array (BGA) or similar components, with substrate locating chips secured by die-attach material, with substrate coated with solder stop lacquer on ball side |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10327882A DE10327882A1 (en) | 2003-06-19 | 2003-06-19 | Improved reliability of solder link at semiconductor products with ball grid array (BGA) or similar components, with substrate locating chips secured by die-attach material, with substrate coated with solder stop lacquer on ball side |
Publications (1)
Publication Number | Publication Date |
---|---|
DE10327882A1 true DE10327882A1 (en) | 2005-01-27 |
Family
ID=33546594
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE10327882A Ceased DE10327882A1 (en) | 2003-06-19 | 2003-06-19 | Improved reliability of solder link at semiconductor products with ball grid array (BGA) or similar components, with substrate locating chips secured by die-attach material, with substrate coated with solder stop lacquer on ball side |
Country Status (1)
Country | Link |
---|---|
DE (1) | DE10327882A1 (en) |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE4324479A1 (en) * | 1993-07-22 | 1995-03-09 | Blaupunkt Werke Gmbh | Method for producing structures which can be soldered in order to make contact with electrical modules |
DE19733123A1 (en) * | 1997-07-31 | 1998-10-29 | Siemens Nixdorf Inf Syst | Method of generating solder paste print with fine structures on substrate |
WO2002047163A2 (en) * | 2000-12-08 | 2002-06-13 | Motorola, Inc., A Corporation Of The State Of Delaware | Semiconductor device having a ball grid array and method therefor |
WO2002058443A1 (en) * | 2001-01-16 | 2002-07-25 | Delaware Capital Formation, Inc. | Contact pads and circuit boards incorporating same |
US6528407B1 (en) * | 1999-10-08 | 2003-03-04 | Stmicroelectronics S.A. | Process for producing electrical-connections on a semiconductor package, and semiconductor package |
-
2003
- 2003-06-19 DE DE10327882A patent/DE10327882A1/en not_active Ceased
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE4324479A1 (en) * | 1993-07-22 | 1995-03-09 | Blaupunkt Werke Gmbh | Method for producing structures which can be soldered in order to make contact with electrical modules |
DE19733123A1 (en) * | 1997-07-31 | 1998-10-29 | Siemens Nixdorf Inf Syst | Method of generating solder paste print with fine structures on substrate |
US6528407B1 (en) * | 1999-10-08 | 2003-03-04 | Stmicroelectronics S.A. | Process for producing electrical-connections on a semiconductor package, and semiconductor package |
WO2002047163A2 (en) * | 2000-12-08 | 2002-06-13 | Motorola, Inc., A Corporation Of The State Of Delaware | Semiconductor device having a ball grid array and method therefor |
WO2002058443A1 (en) * | 2001-01-16 | 2002-07-25 | Delaware Capital Formation, Inc. | Contact pads and circuit boards incorporating same |
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