DE10314808B4 - Sampling time determination when receiving higher-value frequency or phase-modulated received signals by correlation method - Google Patents

Abstract

Method for determining and tracking the optimal sampling time for an oversampled digital bit stream (RXDAIN) formed from a phase-modulated received signal, characterized in that a) an n-times oversampled digital sample stream is generated from a differentially phase-modulated received signal; b) sample values are each multiplied by the complex conjugate sample values spaced apart by one symbol clock and an oversampled digital bit stream (RXDAIN) is generated from the values (ri) obtained; c) a next following sample is read out from the oversampled digital sample stream (RXDAIN) at the previous optimal sampling time; d) the sample (r [k0)) is fed into a comparison sequence which is stored as a continuous bit pattern; e) a correlation between the sequence of sampled sample values and the comparison sequence is determined, an associated correlation value being determined at each sampling time; and f) a new optimal sampling time (t0) is determined from the correlation values determined at the various sampling times.

Description

The invention relates to a method for determining and tracking the optimum sampling time for an oversampled digital bit stream, which was generated from higher-quality frequency or phase modulated received signals.

In cordless communication systems, the data is transmitted in the form of a frame structure. Before the transmission of the data packets synchronization words are transmitted, which are known on the receiver side. Synchronization word and data packet together result in a data burst. The synchronization word at the beginning of the burst is firstly used to identify the burst. On the other hand, the optimum sampling phase for the received bit stream can be determined by means of this synchronization word. In the presence of a digital modulation method, this sampling phase is selected such that it is scanned in each case in the middle of the symbol duration and thus at the maximum opening of the eye diagram.

After the demodulation, a pulse-amplitude-modulated received signal is generated on the receiver side from a binary frequency-modulated received signal, which encodes the binary data. This received signal is fed to a comparator, which supplies the value 0 or the value 1 at its output, depending on whether the received signal is smaller or larger than zero. The actual conversion of the received signal into a sequence of discrete values is performed by periodically sampling the comparator output.

To determine the optimum sampling instant, it is advantageous to sample the output of the comparator several times within the symbol duration at a particular oversampling ratio (OSR). For each data symbol n different samples are determined in this way. Of these samples, only the value corresponding to the optimum sampling time is further processed, the remaining (n-1) values are ignored.

To determine the optimum sampling instant, it is known to compare the oversampled binary data with the synchronization word known at the receiver end at the beginning of the reception of a data burst. This is done by means of a correlator, which compares the input data stream with the synchronization word bit by bit and determines an associated correlation value. For undisturbed receive signals, the first and last occurrences of correlation are at the beginning and end of a symbol duration, respectively, and the sampling time is chosen halfway between these two times.

A disadvantage of this solution is that the determination of the optimal sampling phase is performed only once for each data burst, at the beginning of the reception of the data burst. The initially detected sample phase is then used to sample the entire data burst. Possible signal interference at the beginning of a burst causes the sampling phase to be initially set incorrectly. This erroneous sample phase is then used to sample the entire data burst, resulting in high bit error rates. A further disadvantage is that a possible drift of the time references of transmitter and receiver can not be compensated for by tracking the sampling phase, since the initially defined sampling phase always remains constant for an entire data burst.

In the German Offenlegungsschrift DE 101 07 144 A1 , which is hereby fully incorporated in the disclosure of the present application, describes an apparatus and method for determining and tracking the optimum sampling time for an oversampled input bitstream. In this case, it is assumed that an oversampled digital bit stream is present, with sampled values recorded per bit at n different sampling instants. The device described comprises a read-out unit, which reads the next succeeding bit from the oversampled digital bit stream at the optimum sampling time. In addition, the device comprises a unit for determining the correlation between the sequence of sampled data bits on the one hand and a comparison sequence on the other hand. The new optimum sampling time is determined by a unit for determining the new optimum sampling time as a function of the correlation values determined at the different sampling times. In this case, a continuous bit pattern is used as the comparison sequence, wherein the bit read out at the optimum sampling time is fed into the comparison sequence. The comparison sequence is generated by evaluating the received data stream. The currently read data bit is used to update the comparison sequence. By correlating this comparison sequence with the oversampled input data stream, a new optimal sampling time can be determined. The readout of the next following bit by the readout unit can then already take place at the newly determined optimum sampling time. This bit is also fed back into the comparison sequence, so that a constant redetermination and tracking of the optimum sampling time is made possible in the circulation process.

That in the mentioned German patent application DE 101 07 144 A1 However, initially described method can be applied only to received signals which are bivalent frequency modulated, in particular to bivalent (G) FSK modulated signals. The known method depends on the thresholding of the demodulated data or the pulse amplitude modulated values of the bivalent (G) FSK. With the method described, the sampling phase can not be determined without further measures in the case of higher-order modulation methods.

The publication US 5,329,242 describes a method and apparatus for recovering a message signal from a carrier signal. From this document it is particularly known to convert a value-continuous (analog) or value-discrete (eg 2 ^N -value) frequency-modulated signal into corresponding analog samples.

The publication WO 90/06031 describes digital circuits for increasing the reliability of a decoder for differentially phase modulated signals. One in the 2 illustrated embodiment of a circuit has a digital mixer 34 , a delay line 38 and a multiplexer 42 on which each of the signals 30 . 40 , I1 and I3 are supplied.

The publication US 5,307,380 describes a delay detection circuit for reproducing a digital signal from a received signal. In particular, from this document a device for the reconstruction of a comparison sequence is known in which an associated correlation value (for the received signal) is determined at each sampling time.

It is accordingly the object of the present invention to extend and adapt the known method for sampling time determination to a use for higher-order phase modulation methods. The method is intended to be applicable to phase modulation techniques such as π / 2 DPBSK modulation (Differential Phase Binary Shift Keying) or π / 4 DQPSK modulation (Differential Quaternary Shift Keying).

This object is achieved by a method having the characterizing features of patent claim 1. Advantageous developments and refinements are the subject of dependent claims.

In the present invention, a unit for determining the sampling phase is used, as described in German Offenlegungsschrift DE 101 07 144 A1 has been described. The invention relates to how the receive signals, which are phase-modulated in a specific way, are to be suitably processed in order to be processed in the unit for determining the sampling phase.

For an oversampled digital bit stream formed from a phase-modulated received signal, the optimum sampling time is determined and tracked, wherein
in a method step a) a n-fold oversampled digital sample stream is generated by a differential phase-modulated received signal,
in a method step b) samples are respectively multiplied by the conjugate-complex samples spaced by one symbol clock and an oversampled digital bit stream (RXDA _IN ) is generated from the obtained values (r _i ),
in a method step c), a next succeeding sample is read from the oversampled digital sample stream (RXDA _IN ) at the previous optimum sampling time, in a method step d) the sample (r [k ₀ ]) is fed into a comparison sequence, which is a continuous bit pattern is stored,
in a method step e) a correlation between the sequence of sampled samples and the comparison sequence is determined, wherein an associated correlation value is determined for each sampling time, and
in a method step f) a new optimum sampling time (t ₀ ) is determined from the correlation values determined at the different sampling times.

In this case, the process step b) can be carried out in two different ways.

On the one hand, the difference phase can be determined directly from the multiplication result and subjected to a comparison with predetermined threshold values, whereupon each difference phase is assigned a bit word consisting of N bits depending on the result of the comparison.

Secondly, the real and imaginary parts of the multiplication result can be subjected to a comparison with predetermined threshold values independently of each other, and depending on the comparison result, they can each be assigned a bit word consisting of N bits, and the bit phase can be the difference phase in the method step b) are determined.

The quantity N is determined by the significance of the modulation method.

In process step b) data values r _i can by multiplying the sample values z _{i +} z _i and _OSR by r _i = z _{i + OSR} · z _i *, or r _i = z _i · z _{i + OSR} *
where z _i * is the conjugate complex of z _i .

The method according to the invention is explained in more detail below with reference to the drawings. Show it:

1 an optimal sampling phase determining unit for an over-sampled bit stream according to the prior art;

2 an invention also known per se for determining the optimum sampling phase for an oversampled bitstream;

3 the processing of a 4-valued GFSK-modulated received signal for the processing of the data in the unit after the 2 ; and

4 the processing of a π / x-DXPSK-modulated received signal for processing in the unit of 2 ,

In 1 A sampling phase determination unit according to the prior art is shown, in which the sampling phase is determined at the beginning of a data burst for the entire data burst. For this purpose, the input data stream is correlated with the synchronization word known on the receiver side in order to derive the optimum sampling phase from the correlation result.

For this purpose, the pulse amplitude modulated received signal is sampled several times within a symbol duration T _bit corresponding to a certain oversampling ratio (OSR), so as to obtain n samples per received data symbol. In the in 1 In the example shown, n = 9, that is to say for every data symbol 9 Samples.

gegeben ist. Hierbei bezeichnet T_S die Samplezeit, also das Zeitintervall, zwischen zwei Abtastwerten. Jedes der Schieberegister 1, 2, ..., 5 umfasst n = 9 verschiedene Schieberegisterzellen zur Aufnahme der digitalisierten Abtastwerte. Die Vorschubrichtung der Schieberegister ist durch den Pfeil 6 gekennzeichnet.The oversampled digital bitstream RXDA _IN is shifted through an array of serially connected shift registers 1, 2, ..., 5, the clock frequency of the shift registers passing through

given is. Here, T _S denotes the sample time, ie the time interval between two samples. Each of the shift registers 1, 2,..., 5 comprises n = 9 different shift register cells for receiving the digitized samples. The feed direction of the shift registers is indicated by the arrow 6.

In each of the shift registers 1, 2, ..., 5 are the names Z ^-1 and Z ^-8 . Z ^-1 denotes a delay of one sample period T _S, and accordingly referred ^-8 Z a delay of eight sample times 8 · T _S. Overall, therefore, each of the shift registers 1, 2, ..., 5 causes a delay by 9 sample times, or (because of 9 · T _S = T _bit ) by a symbol time T _bit .

The shift register arrangement consisting of the shift registers 1, 2,..., 5 makes it possible to easily determine the sampling phase by selecting one of the n shift register cells of the shift register 2, from which the next following data symbol value is read out (7). The sampling phase is thus determined by selecting one of the n shift register cells of the shift register 2.

ausgelesen und der Einheit 8 zur Ermittlung der Korrelation zugeführt. Dort wird die Korrelation der Eingangsdatenfolge {(k·T_S – m·T_Bit)}_0≤m≤15 = {r(k·T_S), r(k·T_S – T_Bit), ..., r{k·TBit)} = {r₀, r₁, ..., r₁₄, r₁₅} mit dem bekannten, beispielsweise 16 Bit langen Synchronisationswort {s(m·T_Bit)}_0≤m≤15 = {s₀, s₁, ..., s₁₄, s₁₅} korreliert, um zu jeder Abtastphase k einen zugehörigen Korrelationswert zu ermitteln. Zu diesem Zweck wird das Synchronisationswort RXSYNC in die hierfür vorgesehenen Speicherzellen 10 eingeschrieben (9). Als Korrelationswert dient die Hamming-Distanz d(k) zwischen der Eingangsdatenfolge einerseits und dem Synchronisationswort andererseits. Die Hamming-Distanz wird zu jedem der Zeitpunkte k·T_S berechnet:

In order to determine the optimum sampling phase, the contents r ₀ , r ₁ ,..., R ₁₄ , r _{15 of} the respective first cell of the shift registers 2, 3,..., 5 with the sample frequency

read out and fed to the unit 8 for determining the correlation. There is the correlation of the input data sequence {(k * T _{S -m} * T _bit )} _0≤m≤15 = {r (k * T _S ), r (k * T _S -T _bit ), ..., r {k * Tbit)} = {r ₀ , r ₁ , ..., r ₁₄ , r ₁₅ } with the known, for example, 16-bit synchronization word {s (m · T _bit )} _0≤m≤15 = {s ₀ , s ₁ , ..., s ₁₄ , s ₁₅ } is correlated to determine an associated correlation value for each sampling phase k. For this purpose, the synchronization word RXSYNC in the memory cells provided for this purpose 10 enrolled (9). The Hamming distance d (k) between the input data sequence on the one hand and the synchronization word on the other hand serves as the correlation value. The Hamming distance is calculated at each of the times k · T _S :

The Hamming distance indicates in how many bits the sequence of received data {r (k * T _{s -m} * T _bit )} _0≤m≤15 and the comparison sequence {s (m · T _bit )} _0≤m≤15 differ. In the present example, both sequences are 16 bits long.

To determine if there is a sufficiently strong correlation between the input bit sequence and the comparison sequence, the Hamming distance becomes d (k) compared with a selectable threshold da. If d (k) ≤ d _max , the two sequences are correlated.

At the beginning of each data burst, the synchronization word is transmitted. Let k ₁ - T _{S be} the time at which correlation is present for the first time, ie d (k ₁ ) ≤ d _max . This time is called SYNC. The correlation flag f (k ₁ ) associated with the time k ₁ is set: f (k ₁ ) = 1

For the following 8 times k = k ₁ + 1, k ₁ + 2,..., K ₁ + 8, the associated Hamming distances d (k) are respectively determined and compared with d _max . If the threshold value d _{max is} undershot, the associated correlation flag is set:

The thus determined correlation flags f (k) with k = k ₁ + 1, k ₁ + 2, ..., k ₁ + 8 are from the unit 8th for determining the correlation in a correlation flag shift register 11 inscribed (12). The feed direction of the correlation flag shift register 11 is there by the arrow 13 given.

From the in the shift register 11 stored, 9-bit bit sequence of the correlation flags, the optimal sampling t ₀ = k ₀ × T _S + m × T _bit be determined.

The pulse amplitude modulated signal present before the oversampling may be asymmetrically deformed. In this case, it may be advantageous to adapt the sampling instant to the time of maximum amplitude by slightly shifting the sampling instant from the central sampling instant. This can be done by means of an arbitrarily selectable additional time offset k ₂ ε {-2; -1; 0; 1; 2; 3} take place.

In this respect, the time index k ₀ applies k ₀ = k ₁ + P + k ₂ , where P is the sample phase and k ₂ ε {-2; -1; 0; 1; 2; 3} denotes an arbitrary time offset.

First, the optimum sampling time t _{0 is selected} exactly in the middle between the time of the beginning of the correlation and the time of the last correlation. If k ₁ denotes the index of the first occurrence of correlation and k ₁ + n ₁ the index of the last occurrence of correlation (ie f (k ₁ ) = 1 and f (k ₁ + n ₁ ) = 1), then the result Sample phase P too

At the in 1 This is shown in the correlation flag shift register 11 stored bit pattern converted by means of a lookup table LUT in the associated sample phase P. The readout of the lookup table LUT occurs at the time when the rightmost shift register cell of the correlation flag shift register 11 takes the value 1 for the first time (ie at the time SYNC). The index n ₁ is then determined by the last (ie, leftmost) occurrence of a correlation flag with the value "1". The intervening correlation flag values denoted by "X" are irrelevant for the determination of n ₁ and P (so-called "do not care bits"). The column to the right of the lookup table LUT contains the sample phases P associated with the different correlation flag bit sequences.

The sample phase P becomes the sample hold 14 supplied and determined together with the parameters k ₀ and k ₂ , at which time the reading 7 a particular register cell of the shift register 2 should be done. The read-out value is held for a symbol period T _bit = 9 * T _S , and thus the sampled input signal RXDA _{Sampled is} generated. This signal can, for example, via a data conversion unit 15 a microcontroller μC are supplied.

In 2 shows the unit used for the inventive method for repeated redetermination of the sampling phase. As in the unit of 1 For example, a nine-times oversampled digital bit stream RXDA _{IN is put} into a series of shift registers connected in series 16 . 17 , ..., 20 fed. Each of the shift registers 16 . 17 , ..., 20 has nine memory cells and can therefore record nine consecutive samples. Each time a sample time T _S has elapsed, the contents of the shift registers are shifted further by one position to the right. The arrow 21 indicates the feed direction of the shift registers.

As with the unit of 1 has the unit 30 To determine the correlation, the task is to determine a correlation value between the input bit sequence {r ₀ , r ₁ ,..., r ₁₄ } and the comparison sequence at each sampling instant. Unlike in the prior art, the two episodes to be compared only comprise 15 bits each (instead of the previous 16 bits). The comparison sequence {s ₀ , s ₁ , ..., s ₁₄ } is in the comparison order shift register 22 stored. to first determination of the correlation, ie at the beginning of receiving a data burst contains the comparison sequence shift register 22 the lower 15 bits {s ₀ , s ₁ , ..., s ₁₄ } of the receiver-side known synchronization word, which is transmitted at the beginning of the data burst.

The unit 30 For determining the correlation, for each of the times k · T _S, the Hamming distance d (k) between the input bit sequence and the comparison sequence is determined. The time k ₁ · T _S denotes the time of first correlation, ie the time at which d (k ₁ ) ≦ d _max applies for the first time. The associated correlation flag f (k ₁ ) is set equal to 1, and this value is put into the correlation flag shift register 23 enrolled (24). Just like on the basis of 1 The associated correlation flags f (k) are also determined for the following eight Hamming distances d (k) with k = k ₁ + 1, k ₁ + 2,..., k ₁ + 8 and into the correlation flag shift register 23 enrolled. The inscribed values are from left to right according to the arrow 25 pushed through the shift register.

The in the correlation flag shift register 23 Stored bit patterns can be translated by means of the lookup table LUT into the sample phase P _k for the optimum sampling time t ₀ lying in the middle of the correlation interval. It applies t ₀ = k ₀ * T _S + m -T _bit with k ₀ = k ₁ + P _k + k ₂ , where k _{1 is} the time index for the first occurrence of correlation, P _{k is} the sample phase and k _{2 is} a freely selectable time offset with k ₂ ε {-2; -1; 0; 1; 2; 3}.

The thus determined sampling phase P _k becomes the sample and hold circuit 27 supplied; the reading 26 of the next bit of the input bit stream then already takes place at the sampling instant defined by P _k . The newly read-out bit r [k _0] is sampled as part of the input bit stream RXDA _Sampled on the Datenkonvertiereinheit 29 supplied to the microcontroller μC.

Unlike the unity of 1 the newly read bit r [k ₀ ] will also be in the compare order shift register 22 fed (arrow 28 ), resulting in the following new comparison sequence: {r [k ₀ ], s ₀ , s ₁ , ..., s ₁₃ }

The bit s _{14 of} the synchronization word is obtained by inserting r [k ₀ ] from the comparison sequence shift register 22 pushed out.

Instead of a comparison with the known synchronization word, the determination of the new sampling phase takes place according to the invention by comparing the input samples with a comparison sequence, which results from a decision-based analysis of the received data stream. The decision about the value of the data bit r [k ₀ ] is made by reading ( 26 ) of the input data stream with the previous sampling phase P _k hit.

The new sampling phase P _{k + 1} is then determined on the basis of a modified comparison sequence, which is generated based on the decision on r [k ₀ ]. The determination of the new sampling phase P _{k + 1} is carried out by correlating the input data stream with the new comparison sequence {r [k ₀ ], s ₀ , s ₁ , ..., s ₁₃ }.

Unlike the unity of 1 the bit r _{0 is} no longer out of the shift register 17 but from the shift register 18 read. This results in a certain time delay between readings 26 the required for the comparison sequence bit r [k ₀ ] on the one hand and the readout of the bit r ₀ from the input data stream, so that the value of r [k ₀ ], which is required for the comparison sequence, is already available when r ₀ arrives , Because of this time lag can be in the solution of the 2 the full sampling time interval from incipient to decreasing correlation between input and comparison sequences. It is advantageous if the comparison sequence shift register 22 in each case at the times k ₁ + m × T _bit is filled with zero, because in this way the onset of the correlation can be better tracked.

The newly determined sampling phase P _{k + 1} becomes the sample hold 27 fed. The next input bit can then already be read (26) with the new sampling phase P _{k + 1} .

In order to avoid that the readjustment, for example due to strongly disturbed data bits, repeatedly receives erroneous comparison patterns and thus the newly determined sampling phases are always faulty, a readjustment of the sampling phase P _{k + 1 is} only allowed within a certain range around the initially determined sampling phase P _initial become.

It can also be provided that the deviations of the newly determined sampling phases from the initially determined sampling phase P are _initially summed up over a certain period of time and that a readjustment is only carried out when the accumulated deviation exceeds a certain threshold. By this measure, an improved robustness of the control can be achieved.

The unity of 2 allows continuous readjustment of the sampling phase P _k and provides so that the individual incoming data symbols are scanned in the middle. This improves the decision for the individual data bits and reduces the bit error rate. In particular, a signal disturbance at the beginning of the data burst, ie during the transmission of the synchronization word, no longer results in erroneous sampling of the entire incoming data burst. A possible drift of the time references of transmitter and receiver can be compensated by the tracking of the sampling phase according to the invention.

Between the shift register 18 and the sample holding member 27 an additional tap is shown in dashed lines, so that one can perform processing of the symbols with the symbols shifted by OSR clocks in differential encoding.

In the 3 It is shown how a high-order frequency-modulated, in the present case a 4-valued GFSK-modulated received signal is to be processed in a manner not belonging to the invention to a unit after the 2 be fed and processed therein for the purpose of sampling time can.

In the left part of the picture 3 a pulse amplitude modulated signal is shown, which was generated from the frequency-modulated received signal. This pulse amplitude modulated signal is subjected to a threshold value comparison with predetermined thresholds 1, 2 and 3. The pulse amplitude modulated signal can be supplied, for example, to a threshold value detector in which the threshold values are set in such a way and which outputs a bit sequence at its output as a function of the result of the threshold value comparison. The right-hand part of the drawing shows how, by comparing the pulse-amplitude-modulated signal with the threshold values 1, 2 and 3, a bit word consisting of N = 2 bits is generated and output. In this partial image, the curve of the pulse amplitude modulated signal is redrawn and it can be seen that a new bit sequence is generated at those times when the curve is above or below the threshold values.

The threshold comparison is made at a certain sampling rate, which in turn is a multiple of the bit rate. The oversampled symbols are converted to a double sampling rate bit stream by assigning 2 bits to each symbol. This data stream thus obtained with the predetermined sampling rate can now be converted into the data in connection with the data in 2 described unit for determining the optimum sampling phase are guided based on the correlation method and thus the sampling time can be determined.

In the 4 It is shown how phase-modulated received signals are to be processed in order to determine in a sampling phase determination unit 2 to be processed. This method relates to differential π / x DxPSK phase modulated signals, where x = 2 or 4, for example. In the case of these phase-modulated methods, no conversion takes place by demodulation as in the frequency-modulated method in a pulse amplitude modulated signal, but it takes place by demodulation an image in the phase space (constellation diagram), as in the left part of the image 4 in which the oversampled complex-valued samples (samples) z _i are shown. Due to the differential encoding, the information about the bits in the transition from a state in the constellation diagram to the state subsequent to a bit (or symbol) clock is included. In order to be able to make a determination of the sampling instant, the oversampled samples which are separated by one bit clock, ie by OSR samples in the case of an oversampling, are multiplied together: r _i = z _{i + OSR} * z _i *, or r _i = z _i * z _{i + OSR} *, where z _i * is the conjugate complex of z _i . As is well known, the phases of x * (k) and x (k) differ in their sign. In this respect one obtains as phase of the expression x * (k) * y (k) the difference of the phases of y (k) and x (k).

The data stream thus obtained contains in phase thus the information about the bits. In order to be able to carry out a determination of the optimum sampling phase based on the correlation method, there are various possibilities, as described in the right-hand sub-image of FIG 4 are indicated. Here it is shown once again how the time-delayed samples z _i and Z _{i + OSR are converted} by multiplication into the above expressions r _i . Starting from these, the differential phase can now be determined directly for one thing, and then - as described above in connection with the frequency-modulated receive signals - be considered a pulse amplitude modulated signal and mapped to the possible differential phases given by the modulation. The correlation would then be performed on the difference phases associated with the synchronization word by the modulation. The other option already mentioned is that the real and imaginary parts are fed separately to a threshold value formation, and the phase determination then takes place therefrom. Subsequently, as described above, the correlation can take place.

In addition, other alternatives are conceivable. What is essential, however, is the transfer of the complex-valued input samples into the phase information which is assigned to the bits by the modulation.

For the higher-order modulation methods, too, the correlation can not only be made on binary data, but also multivalue quantization can be performed.

Claims (4)

Method for determining and tracking the optimum sampling instant for an oversampled digital bit stream (RXDA _IN ) formed from a phase-modulated received signal, characterized in that a) a n-times oversampled digital sample stream is generated by a differential phase-modulated received signal; b) multiplying samples by the conjugate-complex samples spaced one symbol clock apart, and generating an oversampled digital bit stream (RXDA _IN ) from the obtained values (r _i ); c) reading out a next succeeding sample from the oversampled digital sample stream (RXDA _IN ) at the previous optimal sample time; d) the sample value (r [k ₀ )) is fed into a comparison sequence which is stored as a continuous bit pattern; e) a correlation between the sequence of sampled samples and the comparison sequence is determined, wherein an associated correlation value is determined at each sampling instant; and f) a new optimum sampling time (t ₀ ) is determined from the correlation values determined at the different sampling instants. A method according to claim 1, characterized in that - in step b) from the multiplication result directly the difference phase is determined and the difference phase is subjected to comparison with predetermined thresholds, and - each difference phase depending on the comparison result assigned to an existing N bits bit word becomes. Method according to Claim 2, characterized in that - in method step b), the real and imaginary parts of the multiplication result are subjected independently to a comparison with predetermined threshold values and, depending on the comparison result, they are each assigned a bit word consisting of N bits, and - off the thus determined bit words, the difference phase is determined at the different sampling times. Method according to one of the preceding claims, characterized in that - in method step b), data values r _{i are} obtained from the sampled values z _{i + OSR} and z _i r _i = z _{i + OSR} * z _i * or r _i = z _i * z _{i + OSR} * be calculated.

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