DE10304848A1 - Depletion layer field effect transistor has gate region around cylinder axis enclosed by depletion layer from first end surface and enclosed by substrate region associated with sink connection - Google Patents

Depletion layer field effect transistor has gate region around cylinder axis enclosed by depletion layer from first end surface and enclosed by substrate region associated with sink connection Download PDF

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DE10304848A1
DE10304848A1 DE2003104848 DE10304848A DE10304848A1 DE 10304848 A1 DE10304848 A1 DE 10304848A1 DE 2003104848 DE2003104848 DE 2003104848 DE 10304848 A DE10304848 A DE 10304848A DE 10304848 A1 DE10304848 A1 DE 10304848A1
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effect transistor
depletion layer
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field effect
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Ludger Marwitz
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Siemens AG
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1066—Gate region of field-effect devices with PN junction gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/7722—Field effect transistors using static field induced regions, e.g. SIT, PBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/808—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a PN junction gate, e.g. PN homojunction gate
    • H01L29/8083—Vertical transistors

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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
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  • General Physics & Mathematics (AREA)
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  • Junction Field-Effect Transistors (AREA)

Abstract

The device is constructed in accordance with cylindrical symmetry with a gate region arranged essentially around the cylinder axis from a first end surface and enclosed by a depletion layer from the first end surface. The depletion layer is enclosed by a substrate region associated with the sink connection and the source connection is essentially arranged on the cylinder axis at a distance from the depletion layer region on a second end surface. The device has source (S), sink (D) and gate (G) connections and is constructed in accordance with the symmetry of a cylinder, whereby a gate region (GB) is arranged essentially around the cylinder axis from a first end surface and enclosed by a depletion layer from the first end surface. The depletion layer is enclosed by a substrate region (SB) associated with the sink connection and the source connection is essentially arranged on the cylinder axis at a distance from the depletion layer region on a second end surface.

Description

Die Erfindung bezieht sich auf einen Sperrschicht-Feldeffekttransistor mit einem Quellen-Anschluss, einem Senken-Anschluss und einem Gate-Anschluss, wie er allgemein unter der Bezeichnung "JFET" für Junction Field Effect Transistor geläufig ist.The invention relates to a JFET with a source connection, a drain connection and a gate connection, as he's commonly called "JFET" for junction Field effect transistor common is.

Sperrschicht-Feldeffekttransistoren nach dem Stand der Technik haben allgemein den Nachteil, dass deren Strom-Spannungskennlinie nicht linear ist. Im einzelnen handelt es sich um die Kennlinie, bei der eine Spannung zwischen der Quelle und dem Gatter des Feldeffekttransistors gegen den Senkenstrom aufgetragen ist. Werden solche Transistoren als Verstärker-Bauelemente benutzt, muss diese Kennlinie durch geeignete Maßnahmen linearisiert werden. Zu diesen Maßnahmen gehört eine Rückkopplung eines von dem Sperrschicht-Feldeffekttransistor verstärkten Signals zu einer Ausgleichschaltung, so dass externe Bauelemente zur Linearisierung des Sperrschicht-Feldeffekttransistors erforderlich sind. Die erforderliche Rückkopplung bewirkt außerdem dass der Sperrschicht-Feldeffekttransistor hinsichtlich der Verarbeitung höherer Frequenzen beschränkt ist.Junction field effect transistors according to the prior art generally have the disadvantage that their Current-voltage characteristic is not linear. In particular, it is the characteristic curve at which a voltage between the source and the gate of the field effect transistor is plotted against the sink current. Such transistors as amplifier components used, this characteristic must be linearized using suitable measures. About these measures heard a feedback one of the junction field effect transistor increased Signal to an equalization circuit so that external components required to linearize the junction field effect transistor are. The feedback required also causes that the junction field effect transistor in terms of processing higher Frequencies limited is.

Ausgehend hiervon liegt der Erfindung die Aufgabe zugrunde, einen Sperrschicht-Feldeffekttransistor zu schaffen, bei dem die oben genannte Kennlinie im wesentlichen linear verläuft, abgesehen von einem üblicher Weise auftretenden Sättigungsbereich.The invention is based on this based on the task of a junction field effect transistor create, in which the above-mentioned characteristic curve is essentially linear runs, aside from a more common one Way occurring saturation range.

Diese Aufgabe wird bei dem eingangs genannten Sperrschicht-Feldeffekttransistor dadurch gelöst, dass der Sperrschicht-Feldeffekttransistor gemäß einer Symmetrie eines Zylinders aufgebaut ist, wobei ein dem Gatter-Anschluss zugeordneter Gatter-Bereich von einer ersten Endfläche aus im wesentlichen um die Achse des Zylinders herum angeordnet ist, der Gatter-Bereich von der ersten Endfläche aus von einem Sperrschicht-Bereich umgeben ist, der Sperrschicht-Bereich von der ersten Endfläche aus von einem dem Senken-Anschluss zugeordneten Senken-Bereich umgeben ist und der Quellen-Anschluss im wesentlichen auf der Zylinderachse in einem Abstand zu dem Sperrschicht-Bereich auf einer zweiten Endfläche angeordnet ist.This task is at the beginning called junction field effect transistor solved by that the junction field effect transistor according to one Symmetry of a cylinder is built, with a gate connection assigned gate area from a first end face is arranged essentially around the axis of the cylinder, the gate area from the first end face from a junction area is surrounded, the barrier layer area from the first end surface surrounded by a sink area assigned to the sink connection and the source connection is essentially on the cylinder axis spaced from the junction area on a second end surface is.

Berechnungen des Erfinders, die später erläutert werden, zeigen, dass bei Einhaltung der Zylindersymmetrie für den Sperrschicht-Feldeffekttransistor der Senkenstrom von der Spannung zwischen Quelle- und Gatter-Anschluss im wesentlichen linear abhängt.Calculations by the inventor, which will be explained later show that if the cylinder symmetry for the junction field effect transistor is observed the sink current from the voltage between the source and gate connection depends essentially linearly.

Dabei kann bevorzugt ein Substrat für den Sperrschicht-Feldeffekttransistor n-leitend und der Gatter-Bereich p+-dotiert sein. Ein Ausführungsbeispiel der Erfindung wird nachfolgend anhand der Figuren näher erläutert.In this case, a substrate for the junction field-effect transistor can preferably be n-conducting and the gate region p + -doped. An embodiment of the invention is explained below with reference to the figures.

Es zeigen:Show it:

1 eine Querschnitts-Ansicht durch einen linearen Sperrschicht-Feldeffekttransistor ohne angelegte Spannung, 1 3 shows a cross-sectional view through a linear junction field-effect transistor without applied voltage,

2 eine Draufsicht auf den Sperrschicht-Feldeffekttransistor von 1, 2 a plan view of the junction field effect transistor of 1 .

3 eine Querschnitts-Ansicht durch einen linearen Sperrschicht-Feldeffekttransistor bei angelegter Spannung und 3 a cross-sectional view through a linear junction field effect transistor with applied voltage and

4 eine Draufsicht auf den linearen Sperrschicht-Feldeffekttransistor von 3. 4 a plan view of the linear junction field effect transistor of 3 ,

Der Sperrschicht-Feldeffekttransistor (Junction Field Effect Transistor; JFET) gemäß 1 und 2 weist eine allgemeine Zylindersymmetrie auf. Eine erste Endfläche 1 des Sperrschicht-Feldeffekttransistors trägt einen Gatter-Anschluss G, der im wesentlichen auf der Zylinderachse angeordnet ist, sowie einen Senken-Anschluss D. Auf einer der ersten Endfläche 1 gegenüberliegenden zweiten Endfläche 2 ist ein Quellen-Anschluss S vorgesehen, der sich auf der Zylinderachse befindet und geerdet ist.The junction field effect transistor (JFET) according to 1 and 2 has a general cylindrical symmetry. A first end face 1 of the junction field-effect transistor carries a gate connection G, which is arranged essentially on the cylinder axis, and a drain connection D. A source connection S is provided on a second end face 2 opposite the first end face 1 is on the cylinder axis and is grounded.

Dem Gatter-Anschluss G zugeordnet ist ein Gatter-Bereich GB zylindrischer Form, der sich entlang der Zylinderachse erstreckt, p+-dotiert ist und in einem Abstand zum Quellen-Anschluss S endet.Associated with the gate connection G is a gate region GB of cylindrical shape, which extends along the cylinder axis, is p + -doped and ends at a distance from the source connection S.

Der Gatter-Bereich GB ist, wie aus den 3 und 4 hervorgeht, von der ersten Endfläche 1 aus von einem Sperrschicht-Bereich DL umgeben, der in einer Höhe x1 in einem Abstand w(x1) zur Zylinderachse endet. Der Sperrschicht-Bereich DL ist allgemein kegelstumpfförmig, wobei die kleinere Endfläche des Kegelstumpfes dem Quellen-Anschluss S zugewandt ist.The gate area GB is as from the 3 and 4 emerges from the first end face 1 surrounded by a barrier layer region DL, which ends at a height x1 at a distance w (x1) from the cylinder axis. The junction region DL is generally frusto-conical, the smaller end surface of the truncated cone facing the source connection S.

Bei angelegter positiver Spannung an der Senke D und negativer Spannung am Gatter G, sowie geerdeter Quelle S, bildet sich um den zylinderförmigen Gatter-Bereich GB der kegelstumpfförmige Sperrschichtbereich DL aus, durch den der leitende Substrat-Bereich SB des Transistors verkleinert wird und der Stromfluss von der Quelle S zur Senke D gesteuert werden kann.When positive voltage is applied to the sink D and negative voltage is applied to the gate G, and the source S is grounded, the frustoconical barrier layer region DL is formed around the cylindrical gate region GB, through which the conductive substrate region SB of the transistor is reduced and the current flow from source S to sink D can be controlled.

Ein dem Senken-Anschluss D zugeordneter Substrat-Bereich SB ist von der ersten Endfläche 1 bis zu der zweiten Endfläche 2 zylinderförmig und umgibt den Sperrschicht-Bereich DL, wobei für den Substrat-Bereich SB n-Dotierung vorliegt.A assigned to the sink connection D. Substrate region SB is cylindrical and from the first end surface 1 to the second end surface 2 surrounds the barrier layer area DL, with n-doping for the substrate area SB is present.

Die Zylindersymmetrie des Sperrschicht-Feldeffekttransistors geht besonders deutlich aus der 4 hervor. Dabei ist der Gatter-Anschluss G in der Mitte kreisförmig ausgebildet. Ein Durchmesser des Gatter-Bereichs GB übertrifft denjenigen des Gatter-Anschlusses G. Der Sperrschichtbereich DL umfasst wiederum den Gatterbereich GB. Der Substrat-Bereich SB umfasst dabei den Sperrschicht-Bereich DL. Der Senken-Anschluss D ist ringförmig über dem Substrat-Bereich SB ausgebildet, während der Sperrschicht-Feldeffekttransistor insgesamt eine zylindrische äußere Form hat.The cylindrical symmetry of the junction field-effect transistor is particularly clear from the 4 out. The gate connection G is circular in the middle. A diameter of the gate area GB exceeds that of the gate connection G. The junction area DL in turn comprises the gate area GB. The substrate area SB comprises the barrier layer area DL. The drain terminal D is designed in a ring shape above the substrate region SB, while the junction field-effect transistor has an overall cylindrical outer shape.

Die Herleitung des gewünschten linearen Zusammenhangs zwischen einer Spannung USG, die zwischen dem Gatter-Anschluss G und dem Quellen-Anschluss S anliegt, und einem Senken-Strom ID ergibt sich wie folgt:
Die nachfolgende Herleitung bezieht sich auf das Fachbuch mit dem Titel "Elektronische Bauelemente und Netzwerke I", von Unger, Schulz, Weinhausen; Erscheinungsjahr 1985, Verlag Friedr. Vieweg & Sohn, Braunschweig/Wiesbaden, Kapitel 5.1. Zum besseren Verständnis der Herleitung wird insbesondere auf die Seiten 142 – 151 aus diesem Fachbuch verwiesen.The derivation of the desired linear relationship between a voltage USG which is present between the gate connection G and the source connection S and a sink current I D results as follows:
The following derivation refers to the specialist book with the title "Electronic Components and Networks I" by Unger, Schulz, Weinhausen; Year of publication 1985, Verlag Friedr. Vieweg & Sohn, Braunschweig / Wiesbaden, chapter 5.1. For a better understanding of the derivation, reference is made in particular to pages 142-151 of this specialist book.

Nach dem dort näher dargestellten Modell für einen Sperrschicht-Feldeffekttransistor ergibt sich hinsichtlich eines Anlaufbereichs in einem Kanal zwischen Quelle und Senke der folgende Zusammenhang:

Figure 00040001
mit der Stromdichte J, der Spannung Uk (x), die an einem Wirkwiderstand des Kanals abfällt und der spezifischen Leitfähigkeit σ. Die x-Koordinate ist definiert durch die Richtung von dem Senken-Anschluss D zu dem Quellen-Anschluss S und wird in 3 angegeben.According to the model for a junction field-effect transistor shown in more detail there, the following relationship results with regard to a start-up area in a channel between source and sink:
Figure 00040001
with the current density J, the voltage Uk (x), which drops across an effective resistance of the channel and the specific conductivity σ. The x coordinate is defined by the direction from the sink port D to the source port S and is shown in FIG 3 specified.

Ein ortsunabhängiger Senkenstrom (Drainstrom) ergibt sich durch Multiplikation der Stromdichte J mit einem stromführenden Querschnitt des Sperrschicht-Feldeffekttransistors. Dieser stromführende Querschnitt ist bei der Zylindersymmetrie des Sperrschicht-Feldeffekttransistors gegeben durch: Q = n·d2 – π w(x)2 (2)mit d gleich dem Radius des Sperrschicht-Feldeffekttransistors und w(x) dem Radius des Sperrschicht-Bereichs auf der Höhe x, der nicht stromführend ist. Diese Größen sind ebenfalls in 3 veranschaulicht, wobei w aufgrund der Kegelstumpfform des Sperrschicht-Bereichs eine Funktion der x-Koordinate ist.A location-independent sink current (drain current) is obtained by multiplying the current density J by a current-carrying cross section of the junction field-effect transistor. In the case of the cylindrical symmetry of the junction field-effect transistor, this current-carrying cross section is given by: Q = nd2 - π w (x) 2 (2) where d is the radius of the junction field-effect transistor and w (x) is the radius of the junction region at height x which is not live. These sizes are also in 3 illustrates, where w is a function of the x coordinate due to the truncated cone shape of the junction region.

Damit ergibt sich für den Senkstrom ID:

Figure 00050001
This results in the lower current I D :
Figure 00050001

Für den Grenzverlauf des Sperrschicht-Bereichs w(x) gilt näherungsweise der folgende Zusammenhang:

Figure 00050002
mit der materialspezifischen Diffusions-Spannung UD, der Spannung zwischen Quellen-Anschluss und Gatter-Anschluss USG und dem sogenannten "Pinch Off"-Potential VPO.The following relationship approximately applies to the boundary course of the junction region w (x):
Figure 00050002
with the material-specific diffusion voltage U D , the voltage between the source connection and gate connection U SG and the so-called "pinch-off" potential V PO .

Einsetzen von Gleichung (4) in Gleichung (3) in Bezug auf w(x) führt zu:Substituting equation (4) into equation (3) in relation to w (x) leads to:

Figure 00060001
Figure 00060001

Für das Wegintegral zwischen einem Punkt x1 zwischen Gatter-Anschluss G und Quellen-Anschluss S und einem Wert 1, der durch die Länge des Sperrschicht-Feldeffekttransistors zwischen den beiden Endflächen definiert ist, ergibt sich:

Figure 00060002
For the path integral between a point x1 between gate connection G and source connection S and a value 1, which is defined by the length of the junction field-effect transistor between the two end faces, the following results:
Figure 00060002

Da die Quelle geerdet ist, gilt Uk(x = 1) = O, so dass

Figure 00060003
Since the source is grounded, Uk (x = 1) = O, so that
Figure 00060003

Unterhalb eines Sättigungsbereiches des Sperrschicht-Feldeffekttransistors gilt Uk(x1) = UDS, mit x1 = 0, so dass

Figure 00060004
Below a saturation range of the junction field-effect transistor, Uk (x1) = U DS applies, with x1 = 0, so that
Figure 00060004

Unterhalb der Sättigung des Sperrschicht-Feldeffekttransistors liegt somit ein linearer Zusammenhang zwischen dem Senkenstrom ID und der Spannung zwischen Quelle und Gatter USG vor, denn es gilt:

Figure 00060005
Below the saturation of the junction field-effect transistor, there is therefore a linear relationship between the sink current I D and the voltage between the source and the gate U SG , because the following applies:
Figure 00060005

Claims (3)

Sperrschicht-Feldeffekttransistor (JFET) mit einem Quellen-Anschluss (S), einem Senken-Anschluss (D) und einem Gatter-Anschluss (G), dadurch gekennzeichnet, dass der Sperrschicht-Feldeffekttransistor (JFET) gemäß einer Symmetrie eines Zylinders aufgebaut ist, wobei ein dem Gatter-Anschluss (G) zugeordneter Gatter-Bereich (GB) von einer ersten Endfläche (1) aus im wesentlichen um die Achse des Zylinders herum angeordnet ist, der Gatter-Bereich (GB) von der ersten Endfläche (1) aus von einem Sperrschicht-Bereich ( DL) umgeben ist, der Sperrschicht-Bereich ( DL) von der ersten Endfläche (1) aus von einem dem Senken-Anschluss (D) zugeordneten Substrat-Bereich ( SB) umgeben ist und der Quellen-Anschluss (S) im wesentlichen auf der Zylinderachse in einem Abstand zu dem Sperrschicht-Bereich DL) auf einer zweiten Endfläche (2) angeordnet ist.Junction field effect transistor (JFET) with a source connection (S), a drain connection (D) and a gate connection (G), characterized in that the junction field effect transistor (JFET) is constructed according to a symmetry of a cylinder, wherein a gate area (GB) assigned to the gate connection (G) is arranged from a first end face (1) essentially around the axis of the cylinder, the gate area (GB) from the first end face (1) is surrounded by a barrier layer area (DL), the barrier layer area (DL) is surrounded by a substrate area (SB) assigned to the drain connection (D) from the first end face (1) and the source connection ( S) is arranged essentially on the cylinder axis at a distance from the barrier layer region DL) on a second end surface (2). Sperrschicht-Feldeffekttransistor nach Anspruch 1, dadurch gekennzeichnet, dass ein Substrat für den Sperrschicht-Feldeffekttransistor (JFET) n-leitend, der Gatter-Bereich (GB) p+-dotiert ist.Junction field effect transistor according to claim 1, characterized in that a substrate for the junction field effect transistor (JFET) is n-type, the gate region (GB) is p + -doped. Sperrschicht-Feldeffekttransistor (JFET) nach Anspruch 1 oder 2, dadurch gekennzeichnet, dass der Sperrschicht-Bereich ( DL), der den Gatter-Bereich (GB) umgibt, im wesentlichen kegelstumpfförmig ausgebildet ist, wobei die kleinere Endfläche des Kegelstumpfes dem Quellen-Anschluss (S) zugewandt ist, der Gatter-Bereich (GB) zylinderförmig ist und der Substrat-Bereich (SB) eine zylinderförmige Mantelfläche aufweist und in Zylinderachsennähe zwischen dem Sperrschicht-Bereich ( DL) und dem Quellen-Anschluss (S) verläuft.A junction field effect transistor (JFET) according to claim 1 or 2, characterized in that the junction area (DL), which surrounds the gate area (GB), is substantially frustoconical is the smaller end face of the truncated cone facing the source connector (S) the gate area (GB) is cylindrical and the substrate area (SB) a cylindrical one lateral surface has and in Close to the cylinder axis between the junction area (DL) and the source connector (S) runs.
DE2003104848 2003-02-06 2003-02-06 Depletion layer field effect transistor has gate region around cylinder axis enclosed by depletion layer from first end surface and enclosed by substrate region associated with sink connection Withdrawn DE10304848A1 (en)

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DE2003104848 DE10304848A1 (en) 2003-02-06 2003-02-06 Depletion layer field effect transistor has gate region around cylinder axis enclosed by depletion layer from first end surface and enclosed by substrate region associated with sink connection
PCT/EP2004/000577 WO2004070849A1 (en) 2003-02-06 2004-01-23 Depletion layer field effect transistor
TW93102397A TW200423413A (en) 2003-02-06 2004-02-03 Barrier-layer field-effect-transistor

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3930300A (en) * 1973-04-04 1976-01-06 Harris Corporation Junction field effect transistor
US4507845A (en) * 1983-09-12 1985-04-02 Trw Inc. Method of making field effect transistors with opposed source _and gate regions
US4951099A (en) * 1982-02-09 1990-08-21 Trw Inc. Opposed gate-source transistor

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3930300A (en) * 1973-04-04 1976-01-06 Harris Corporation Junction field effect transistor
US4951099A (en) * 1982-02-09 1990-08-21 Trw Inc. Opposed gate-source transistor
US4507845A (en) * 1983-09-12 1985-04-02 Trw Inc. Method of making field effect transistors with opposed source _and gate regions

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