DE10262164B4 - Computersystem mit einer hierarchischen Cacheanordnung - Google Patents

Computersystem mit einer hierarchischen Cacheanordnung Download PDF

Info

Publication number
DE10262164B4
DE10262164B4 DE10262164A DE10262164A DE10262164B4 DE 10262164 B4 DE10262164 B4 DE 10262164B4 DE 10262164 A DE10262164 A DE 10262164A DE 10262164 A DE10262164 A DE 10262164A DE 10262164 B4 DE10262164 B4 DE 10262164B4
Authority
DE
Germany
Prior art keywords
cache
cache line
group
cache lines
lines
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE10262164A
Other languages
German (de)
English (en)
Inventor
Blaine D. Fort Collins Gaither
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hewlett Packard Development Co LP
Original Assignee
Hewlett Packard Development Co LP
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Development Co LP filed Critical Hewlett Packard Development Co LP
Priority to DE10232926A priority Critical patent/DE10232926B4/de
Application granted granted Critical
Publication of DE10262164B4 publication Critical patent/DE10262164B4/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0817—Cache consistency protocols using directory methods
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0813—Multiuser, multiprocessor or multiprocessing cache systems with a network or matrix configuration

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Multi Processors (AREA)
DE10262164A 2001-07-31 2002-07-19 Computersystem mit einer hierarchischen Cacheanordnung Expired - Fee Related DE10262164B4 (de)

Priority Applications (1)

Application Number Priority Date Filing Date Title
DE10232926A DE10232926B4 (de) 2001-07-31 2002-07-19 Verfahren zum Aufrechterhalten der Kohärenz in einer hierarchischen Cacheanordnung eines Computersystems

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/919,309 US6662277B2 (en) 2001-07-31 2001-07-31 Cache system with groups of lines and with coherency for both single lines and groups of lines
US09/919,309 2001-07-31
DE10232926A DE10232926B4 (de) 2001-07-31 2002-07-19 Verfahren zum Aufrechterhalten der Kohärenz in einer hierarchischen Cacheanordnung eines Computersystems

Publications (1)

Publication Number Publication Date
DE10262164B4 true DE10262164B4 (de) 2010-11-11

Family

ID=25441869

Family Applications (2)

Application Number Title Priority Date Filing Date
DE10262164A Expired - Fee Related DE10262164B4 (de) 2001-07-31 2002-07-19 Computersystem mit einer hierarchischen Cacheanordnung
DE10232926A Expired - Fee Related DE10232926B4 (de) 2001-07-31 2002-07-19 Verfahren zum Aufrechterhalten der Kohärenz in einer hierarchischen Cacheanordnung eines Computersystems

Family Applications After (1)

Application Number Title Priority Date Filing Date
DE10232926A Expired - Fee Related DE10232926B4 (de) 2001-07-31 2002-07-19 Verfahren zum Aufrechterhalten der Kohärenz in einer hierarchischen Cacheanordnung eines Computersystems

Country Status (3)

Country Link
US (2) US6662277B2 (https=)
JP (1) JP2003067246A (https=)
DE (2) DE10262164B4 (https=)

Families Citing this family (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7222220B2 (en) * 2001-05-01 2007-05-22 Sun Microsystems, Inc. Multiprocessing system employing address switches to control mixed broadcast snooping and directory based coherency protocols transparent to active devices
US7210006B2 (en) * 2002-06-28 2007-04-24 Sun Microsystems, Inc. Computer system supporting read-to-write-back transactions for I/O devices
US7162588B2 (en) * 2002-08-23 2007-01-09 Koninklijke Philips Electronics N.V. Processor prefetch to match memory bus protocol characteristics
US8185602B2 (en) 2002-11-05 2012-05-22 Newisys, Inc. Transaction processing using multiple protocol engines in systems having multiple multi-processor clusters
US6996645B1 (en) * 2002-12-27 2006-02-07 Unisys Corporation Method and apparatus for spawning multiple requests from a single entry of a queue
US8751753B1 (en) 2003-04-09 2014-06-10 Guillermo J. Rozas Coherence de-coupling buffer
US7636815B1 (en) 2003-04-09 2009-12-22 Klaiber Alexander C System and method for handling direct memory accesses
US7363432B2 (en) * 2004-03-25 2008-04-22 International Business Machines Corporation Method and apparatus for directory-based coherence with distributed directory management
US7321956B2 (en) * 2004-03-25 2008-01-22 International Business Machines Corporation Method and apparatus for directory-based coherence with distributed directory management utilizing prefetch caches
US7434008B2 (en) * 2004-04-23 2008-10-07 Hewlett-Packard Development Company, L.P. System and method for coherency filtering
US7454576B2 (en) * 2004-12-27 2008-11-18 Intel Corporation System and method for cache coherency in a cache with different cache location lengths
US7536513B2 (en) * 2005-03-31 2009-05-19 International Business Machines Corporation Data processing system, cache system and method for issuing a request on an interconnect fabric without reference to a lower level cache based upon a tagged cache state
US7971002B1 (en) 2005-04-07 2011-06-28 Guillermo Rozas Maintaining instruction coherency in a translation-based computer system architecture
US7581068B2 (en) * 2006-06-29 2009-08-25 Intel Corporation Exclusive ownership snoop filter
US8688890B2 (en) * 2006-12-05 2014-04-01 Hewlett-Packard Development Company, L.P. Bit ordering for communicating an address on a serial fabric
US8539164B2 (en) * 2007-04-30 2013-09-17 Hewlett-Packard Development Company, L.P. Cache coherency within multiprocessor computer system
US20080307169A1 (en) * 2007-06-06 2008-12-11 Duane Arlyn Averill Method, Apparatus, System and Program Product Supporting Improved Access Latency for a Sectored Directory
US20110004729A1 (en) * 2007-12-19 2011-01-06 3Leaf Systems, Inc. Block Caching for Cache-Coherent Distributed Shared Memory
US20090198910A1 (en) * 2008-02-01 2009-08-06 Arimilli Ravi K Data processing system, processor and method that support a touch of a partial cache line of data
US8117401B2 (en) * 2008-02-01 2012-02-14 International Business Machines Corporation Interconnect operation indicating acceptability of partial data delivery
US8140771B2 (en) 2008-02-01 2012-03-20 International Business Machines Corporation Partial cache line storage-modifying operation based upon a hint
US8255635B2 (en) * 2008-02-01 2012-08-28 International Business Machines Corporation Claiming coherency ownership of a partial cache line of data
US8250307B2 (en) * 2008-02-01 2012-08-21 International Business Machines Corporation Sourcing differing amounts of prefetch data in response to data prefetch requests
US8024527B2 (en) * 2008-02-01 2011-09-20 International Business Machines Corporation Partial cache line accesses based on memory access patterns
US8108619B2 (en) * 2008-02-01 2012-01-31 International Business Machines Corporation Cache management for partial cache line operations
US8266381B2 (en) * 2008-02-01 2012-09-11 International Business Machines Corporation Varying an amount of data retrieved from memory based upon an instruction hint
US8117390B2 (en) * 2009-04-15 2012-02-14 International Business Machines Corporation Updating partial cache lines in a data processing system
US8140759B2 (en) * 2009-04-16 2012-03-20 International Business Machines Corporation Specifying an access hint for prefetching partial cache block data in a cache hierarchy
US9274955B2 (en) * 2012-08-17 2016-03-01 Futurewei Technologies, Inc. Reduced scalable cache directory
US20140223100A1 (en) * 2013-02-07 2014-08-07 Alex J. Chen Range based collection cache
US9596279B2 (en) * 2013-02-08 2017-03-14 Dell Products L.P. Cloud-based streaming data receiver and persister
US9141680B2 (en) 2013-02-11 2015-09-22 Dell Products L.P. Data consistency and rollback for cloud analytics
US9191432B2 (en) 2013-02-11 2015-11-17 Dell Products L.P. SAAS network-based backup system
US9442993B2 (en) 2013-02-11 2016-09-13 Dell Products L.P. Metadata manager for analytics system
US20140281270A1 (en) * 2013-03-15 2014-09-18 Henk G. Neefs Mechanism to improve input/output write bandwidth in scalable systems utilizing directory based coherecy
US20150074357A1 (en) * 2013-09-09 2015-03-12 Qualcomm Incorporated Direct snoop intervention
US10102000B2 (en) * 2016-04-01 2018-10-16 Intel Corporation Apparatus and method for non-serializing split locks

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5150472A (en) * 1989-10-20 1992-09-22 International Business Machines Corp. Cache management method and apparatus for shared, sequentially-accessed, data
US5404483A (en) * 1990-06-29 1995-04-04 Digital Equipment Corporation Processor and method for delaying the processing of cache coherency transactions during outstanding cache fills
US5787475A (en) * 1992-07-21 1998-07-28 Digital Equipment Corporation Controlled prefetching of data requested by a peripheral
US5666514A (en) * 1994-07-01 1997-09-09 Board Of Trustees Of The Leland Stanford Junior University Cache memory containing extra status bits to indicate memory regions where logging of data should occur
US5615334A (en) * 1994-10-07 1997-03-25 Industrial Technology Research Institute Memory reflection system and method for reducing bus utilization and device idle time in the event of faults
US6049847A (en) * 1996-09-16 2000-04-11 Corollary, Inc. System and method for maintaining memory coherency in a computer system having multiple system buses
US5832232A (en) * 1996-12-16 1998-11-03 Intel Corporation Method and apparatus for providing user-based flow control in a network system
US6035376A (en) * 1997-10-21 2000-03-07 Apple Computer, Inc. System and method for changing the states of directory-based caches and memories from read/write to read-only
US6049845A (en) * 1997-11-05 2000-04-11 Unisys Corporation System and method for providing speculative arbitration for transferring data
US6330591B1 (en) * 1998-03-09 2001-12-11 Lsi Logic Corporation High speed serial line transceivers integrated into a cache controller to support coherent memory transactions in a loosely coupled network
US6189078B1 (en) * 1998-12-22 2001-02-13 Unisys Corporation System and method for increasing data transfer throughput for cache purge transactions using multiple data response indicators to maintain processor consistency
US6405322B1 (en) * 1999-04-13 2002-06-11 Hewlett-Packard Company System and method for recovery from address errors
US6266744B1 (en) * 1999-05-18 2001-07-24 Advanced Micro Devices, Inc. Store to load forwarding using a dependency link file
US6374332B1 (en) * 1999-09-30 2002-04-16 Unisys Corporation Cache control system for performing multiple outstanding ownership requests
US6493809B1 (en) * 2000-01-28 2002-12-10 International Business Machines Corporation Maintaining order of write operations in a multiprocessor for memory consistency
US6412046B1 (en) * 2000-05-01 2002-06-25 Hewlett Packard Company Verification of cache prefetch mechanism
US6647453B1 (en) * 2000-08-31 2003-11-11 Hewlett-Packard Development Company, L.P. System and method for providing forward progress and avoiding starvation and livelock in a multiprocessor computer system
US6711662B2 (en) * 2001-03-29 2004-03-23 Intel Corporation Multiprocessor cache coherence management

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
NICHTS ERMITTELT *

Also Published As

Publication number Publication date
JP2003067246A (ja) 2003-03-07
DE10232926A1 (de) 2003-03-06
US7310708B2 (en) 2007-12-18
DE10232926B4 (de) 2006-04-13
US20030028730A1 (en) 2003-02-06
US20040039879A1 (en) 2004-02-26
US6662277B2 (en) 2003-12-09

Similar Documents

Publication Publication Date Title
DE10262164B4 (de) Computersystem mit einer hierarchischen Cacheanordnung
DE69130086T2 (de) Mehrstufeneinschluss in mehrstufigen Cache-Speicherhierarchien
DE69900797T2 (de) Cache-Speicherkohärenzprotokoll mit unabhängiger Implementierung von optimierten Cache-Speicheroperationen
DE102009022151B4 (de) Verringern von Invalidierungstransaktionen aus einem Snoop-Filter
DE112008002018B4 (de) Bereitstellen eines gemeinsam genutzten Inklusiv-Cache bei Mehrkern-Cache-Clustern
DE102007030116B4 (de) Snoop-Filter mit ausschließlicher Inhaberschaft
DE68924206T2 (de) Verfahren und Einrichtung zum Filtern von Ungültigkeitserklärungsanforderungen.
DE69127111T2 (de) Verfahren zum Nachladen aufgeschobener Datenauslagerungen in einen Copy-back Daten-Cachespeicher
DE3856552T2 (de) Multiprozessor-Digitaldatenverarbeitungssystem und Verfahren zum Betreiben dieses Systems
DE102007052853B4 (de) Zeilentauschschema zur Verringerung von Rückinvalidierungen in einem Snoopfilter
DE69736544T2 (de) Verfahren zur Verminderung der Anzahl von Kohärenz-Zyklen in einem verzeichnisbasierten Cachekohärenz-Speichersystem unter Verwendung eines Speicherzustands-Cachespeichers
DE102013201079A1 (de) Mechanismus des Weiterleitungsfortschritts für Speichervorgänge beim Vorhandensein einer Überlastung in einem System, das Belastungen durch Zustandsänderungen begünstigt
DE10219623A1 (de) System und Verfahren zur Speicherentscheidung unter Verwendung von mehreren Warteschlangen
DE102008048627A1 (de) Zuteilen von Platz in dedizierten Cache-Wegen
DE112009000373T5 (de) Technik, um Information zwischen unterschiedlichen Kohärenz-Domains von Caches zu nutzen
DE112005002268T5 (de) Verfahren und Vorrichtung für eine vorwärtslaufende Victim-Auswahl zum Verringern eines unerwünschten Ersatzverhaltens in inklusiven Caches
DE112009000836T5 (de) Adaptive Cache-Organisation für Chip-Multiprozessoren
DE112013000889T5 (de) Weiterleitungsfortschritts-Mechanismus für Speichervorgänge bei Vorhandensein von Ladekonflikten in einem Ladevorgänge begünstigenden System
DE102007048601A1 (de) Datenspeicherung in einem Schaltsystem, das mehrere Prozessoren eines Computersystems koppelt
DE10006430B4 (de) Verfahren zur Aufrechterhaltung einer Kohärenz für ein Multi-Prozessor-System
DE112005002180T5 (de) Lösen von Cachekonflikten
DE102006030879B4 (de) System zum Reduzieren der Latenzzeit von exklusiven Leseanforderungen in einem symmetrischen Multiprozessorsystem
DE102016222041B4 (de) Ungültigmachen eines umsetzungseintrags in einem multithread-datenverarbeitungssystem
DE69130626T2 (de) Verfahren zur Verwaltung einer Cache-Speicheranordnung
DE102021108478B4 (de) Vorrichtung und Steuerung zur Cache-Verzeichnis-CAM-Fehlererkennung und - Korrektur

Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
Q172 Divided out of (supplement):

Ref document number: 10232926

Country of ref document: DE

Kind code of ref document: P

8110 Request for examination paragraph 44
AC Divided out of

Ref document number: 10232926

Country of ref document: DE

Kind code of ref document: P

AC Divided out of

Ref document number: 10232926

Country of ref document: DE

Kind code of ref document: P

8364 No opposition during term of opposition
R020 Patent grant now final

Effective date: 20110211

R119 Application deemed withdrawn, or ip right lapsed, due to non-payment of renewal fee

Effective date: 20130201