DE10256154A1 - System and method for compensating high-speed non-linearities in heterodyne interferometers - Google Patents

Abstract

A system and method for compensating for the non-linearity of the high-speed type, which is manifested in heterodyne interferometer position data, comprises receiving a plurality of groups of digital position values. A plurality of groups of digital phase values from a measurement channel are received. A first group of the digital position values and digital phase values is digitally processed to generate a plurality of block data values. The plurality of block data values are digitally processed to generate at least one quasi-static non-linearity parameter. A second group of the digital position values is compensated based on the at least one quasi-static non-linearity parameter.

Description

This invention is related to the US patent application, serial number 10 / 003.798 entitled October 26, 2001 "Phase digitizer" was filed, and with the US Patent application, serial number 10 / 010.175, which was filed on November 2001 with the title "System and procedure for Interferometer nonlinearity compensation " related.

This condition generally relates to Interferometer. This invention relates more particularly to System and method for heterodyne Interferometer compensation of a type of nonlinearity that occurs at high Speeds occurs.

A light leakage loss between rays in one Interferometer in metrology produces measurement results from Ideally, periodically deviate what is called non-linearity is known.

A known technique for compensating for non-linearity involved in a homodyne interferometer Balancing the two in-phase and quadrature signals within of the interferometer for offset, gain and one Orthogonality. The signals are digitized with respect to their imbalance, and it becomes an analog Electronics used to offset and gain To inject compensation. All compensation components are contained within the interferometer itself. at a heterodyne interferometer are not in phase and balance the quadrature signal. So that's one Compensation method on a heterodyne interferometer not applicable.

It would be desirable to have a system and method for Nonlinearity compensation of Interferometer position data using a digital numeric To create processing where the non-linearity of a type that occurs at high speeds.

It is an object of the present invention, a system and a method for the compensation of high-speed Nonlinearities of heterodyne interferometers too create.

This object is achieved by a method according to claim 1, a compensation system according to claim 11 and heterodyne interferometer system for displacement measurement according to Claim 22 solved.

One form of the present invention provides a method to compensate for a nonlinearity of the High-speed type that are in heterodyne Interferometer position data manifested. A plurality of groups of digital position values are received. A majority of Groups of digital phase values from a measuring channel receive. A first group of digital position values and the digital phase values are digitally processed to generate a plurality of block data values. The A plurality of block data values are digitally processed to at least one quasi-static non-linearity parameter to create. A second group of digital Position values are based on the at least one quasi-static Nonlinearity parameters compensated.

Preferred embodiments of the present invention are referred to below with reference to the enclosed Drawings explained in more detail. Show it:

FIG. 1 is an electrical block diagram illustrating a known heterodyne interferometer system for displacement measurement;

Fig. 2 is a functional block diagram illustrating a high-speed non-linearity compensation system according to an embodiment of the present invention;

Fig. 3 is a diagram illustrating a position data word, which has been output by the interferometer of FIG. 1;

FIG. 4 is an electrical schematic diagram illustrating an embodiment of the block data generator shown in FIG. 2;

5A is an electrical schematic diagram illustrating a modulo-320 counter for generating counter signals for controlling the operation of the block data generator shown in Figure 4,..;

Fig. 5B is a diagram illustrating control signals for controlling the operation of the block data generator shown in Fig. 4;

Figure 6 is a diagram of a group of 320 position data words partitioned into ten blocks of 32 words each; and

FIG. 7 is an electrical block diagram illustrating one embodiment of the compensation processing block shown in FIG. 2.

In the detailed description of the preferred embodiments is attached to the Reference is made to drawings which form a part hereof, and on which specific by means of representation Exemplary embodiments are shown in which the invention is practiced can be. It should be noted that others Examples used and structural or logical Changes can be made without dated Depart from the scope of the present invention. The The following detailed description should not be considered apply restrictively, and the scope of protection of the present invention is by the appended claims Are defined.

I. INTERFEROMETRY SYSTEM FOR SHIFT MEASUREMENT

The non-linearity compensation system and method of present invention is in connection with a heterodyne interferometry system for displacement measurement discussed.

A typical interferometer system for displacement measurement consists of a frequency-stabilized laser light source, an interferometer optics and measuring electronics. In metrology, which is based on homodyne interferometry, the phase progression function φ (t) is directly proportional to the object offset in time t, usually by the factor λ / 4. This means that a UI change (UI = unit interval) represents an object movement of a quarter of the wavelength of the light wave. A UI represents a light wave interference fringe or 2π rad. When mixing while maintaining a phase, a path of λ / 4 manifests as an interference fringe. In metrology, which is based on heterodyne interferometry, there are two channels: one Doppler shifted (measuring channel) and the other non-shifted (reference channel). The difference between the two-phase progression functions φ _M (t) and φ _R (t) of the two channels is proportional to the object offset up to an arbitrary constant. The phase progression functions for both channels increase monotonically over time.

Fig. 1 is an electrical block diagram 100 illustrating a known heterodyne interferometer system for displacement measurement. The interferometer system 100 comprises a laser 102 , an interferometer 108 , measurement and processing electronics 112 and a fiber optic pickup 114 . The interferometer 108 comprises a stationary retroreflector 104 , a PBS (PBS = polarizing beam splitter = polarization beam splitter) and a movable retroreflector 110 .

Laser 102 generates a pair of collinear, orthogonally polarized optical beams of the same intensity and different frequencies F ₁ and F ₂ that differ in frequency by F _R , which is a reference frequency (also referred to as a split frequency). The optical rays move through interferometer 108 . The polarizing beam splitter 106 reflects one polarization of the incoming light to the stationary retroreflector 104 and guides the other polarization of the light to the movable retroreflector 110 . The reflectors 104 and 110 send the light back to the polarizing beam splitter 106 where one beam is transmitted and the other beam is reflected so that the two beams are again collinear. The linear movement of the movable retroreflector 110 results in a corresponding change in the phase difference between the two beams. The rays output by the interferometer 108 reach the fiber optic pickup 114 . In the fiber optic pickup 114 , the beams output from the interferometer 108 are mixed, and the mixed beam is coupled to an optical fiber 113 . The mixed beam is called the measurement signal and the mixture is represented by the following Equation I: Equation I

in which:
⊗ indicates a mix operation; and
the line over F ₁ indicates that the signal has shifted Doppler.

The measurement and processing electronics 112 contains a fiber optic receiver that generates an electrical measurement signal that corresponds to the optical measurement signal. The measurement signal has a frequency that is equal to the reference frequency F _R plus the Doppler shift frequency, as shown in Equation II below: Equation II F _M = F _R + nν / λ

in which:
ν is the speed of the interferometer element whose position is being measured (the sign of ν indicates the direction of movement);
λ is the wavelength of the light emitted by laser 102 ; and
n is 2, 4, etc. is dependent on the number of passes that the light makes through the interferometer 108 . In the exemplary embodiments of the present invention, n = 4.

In the example system of FIG. 4, the movement of the retroreflector 110 produces the Doppler shift, and n = 2. The laser 102 also outputs a reference signal at the reference frequency (F _R ) via a fiber optic cable 111 , which is connected to a fiber optic receiver in the measurement and Processing electronics 112 runs. The reference signal is generated by mixing the two beams from the laser 102 (F ₁ and F ₂ ), which is represented by Equation III below: Equation III reference signal = F ₁ ⊗ F ₂

The measurement and processing electronics 112 includes a fiber optic receiver that generates an electrical reference signal corresponding to the optical reference signal. The reference signal has a frequency that is equal to the reference frequency F _R.

Measurement and processing electronics 112 measure and accumulate the phase difference between the reference signal and the measurement signal and process the difference to provide position and speed output signals.

II. NONLINEARITY

In less ideal situations, light leakage occurs between laser beams 102 , causing a small amount of one frequency to be present in the other frequency. By symbolizing the ideal case with a capital letter and the leakage with a lower case letter, the non-ideal situation can be symbolized using the following equation IV and equation V: Equation IV

Equation V reference signal: (F ₁ + f ₂ ) ⊗ (F ₂ + f ₁ )

Mixing produces signals of many frequencies. The measurement signal has six mixed components:

The reference signal also has six mixed components:

R1: F ₁ ⊗ F ₂ ; R2: F ₁ ⊗ f ₂ ; R3: f ₁ ⊗ F ₂ ; R4: f ₁ ⊗ F ₁ ; R5: f ₂ ⊗ F ₂ ; R6: f ₁ ⊗ f ₂

The signals M1 and R1 are the desired measuring or Reference signals, not the non-linearity. Typically are M1 and R1 are the dominant components.

Signals M6 and R6 are mixed products of two typically small signals that only effects second Create order. The signals M6 and R6 can be ignored become.

The signals R2, R3, R4 and R5 are static parameters. The Signals R2 and R3 have the same frequency as that ideal signal R1, which is the reference or partial frequency is. The combined effect of R2 and R3 is said to be one inconsistent constant phase shift to the reference signal cause. The signals R4 and R5 are "stable" signals, that mix with each other, which only results in a static DC amplitude shift leads. A "constant" Signal is a signal that is not Doppler shifted. at an AC-coupled circuit generate R4 and R5 no effect and can be ignored.

The non-linearity caused by M2 and M3 is at moderate speeds (e.g. below about 50 mm / sec) on obvious. M2 and M3 generate one Interference signal at the reference frequency, which interferes with the measurement signal M1, to cause non-linearity. The temporal frequency the nonlinearity is the Doppler frequency, and therefore is the spatial frequency of the nonlinearity invariant (she is always a period at λ / 4 of the distance traveled Distance). The non-linearity caused by M2 and M3 is also with the position data for a period of 1 UI or one "Streak", the λ / 4 of the distance traveled represents, periodically. For a HeNe laser, λ is 633 nm. The spatial frequency invariance property of a Nonlinearity of the M2 and M3 types facilitates compensation.

The signals M4 and M5 are of the non-linearity type, which is observed at a high speed of the measurement object away from the light source. The mixed product of M4 has the form shown in Equation VI below: Equation VI

in which:
p _{1 is} a position parameter; and
λ is the wavelength of the light emitted by laser 102 .

Similarly, the mixed product of M5 has the form shown in Equation VII below: Equation VII

in which:
p _{2 is} a position parameter; and
λ is the wavelength of the light emitted by laser 102 .

The position parameters p ₁ and p ₂ can have different origins, but are scaled almost identically, since F _{1 is} only a few megahertz of F2 in one exemplary embodiment. The temporal frequency of M4 and M5 is the same and is equal to the Doppler frequency f _Doppler = f _R - f _M. The M4 and M5 signals interfere with the measurement signal at f _M - f _Doppler , which produces a non-linearity on the temporal frequency of 2.f _M - f _R. In one embodiment, the M4 and M5 types of non-linearity are only seen when the measurement frequency approaches half of the reference frequency, which happens when the object is moving rapidly within a small range of speeds from the source (e.g. about 0.5 m / sec). Unfortunately, neither the temporal nor the spatial frequency of the M4 and M5 types of nonlinearity is invariant, which makes their compensation more complex. In addition to the position data, the measuring channel reference frequency is required. One embodiment of the present invention compensates for the non-linearity caused by signals M4 and M5.

The nonlinearity disturbance Δφ (t), (in UI), as a function of time is shown in Equation VIII below: Equation VIII

in which:
r is the ratio of the orders of magnitude of the combined interfering M4 / M5 signal to that of the ideal signal M1; and
θ is a phase offset between the phase progression of (2f _M- f _R ) and the non-linearity pattern of the position data at the same frequency.

III. NON LINEARITY COMPENSATION A. Overview of the compensation system

In one embodiment of the present invention, the measured position data output by the interferometer system 100 and the phase progression of the measurement channel are processed, and two most suitable, quasi-static non-linearity parameters are generated to compensate for the data in the near future. Continuing the process indefinitely, all data is compensated for after an initial latency period. In one form of the invention, the non-linearity magnitude and in-phase phase parameters are determined from the 320 consecutive position data words and the 320 measurement channel phase progression words and used to compensate for the position data words that immediately follow. One form of the invention is a fully digital process that is skipped in a "leapfrog" fashion, thereby compensating for all future data using the periodically updated non-linearity parameters.

Fig. 2 is a functional block diagram 200 illustrating a non-linearity compensation system according to an embodiment of the present invention. Fig. 2 shows a phase digitizing section 100 P 100 of the interferometer system. The phase digitizing section 100 includes a P Meßkanalphasendigitalisierer 208 M a Referenzkanalphasendigitalisierer R 208 and the ALU 207 (Arithmetic Logic Unit ALU = Arithmetic Logic Unit). The measurement channel phase digitizer 208 M generates measurement channel phase data 209 M based on a received measurement signal. The reference channel phase digitizer 208 R generates reference channel phase data 209 R based on a received reference signal. The ALU 207 generates observed position data 204 based on the difference between the measurement channel phase data 209 M and the reference channel phase data 209 R.

The non-linearity compensation system 200 includes a compensation processing block 206 , a block data generator 210 , a parameter generator 212, and ALUs 217 and 220 . The compensation processing block 206 includes a block RAM table 206 A and an ALU 206 B. In one embodiment, the non-linearity compensation system 200 compensates for non-linearity of the M4 and M5 types in uncompensated position data 202 , which includes observed position data 204 , by the interferometer system 100 are output, and can also include expanded position data (e.g. expanded by extrapolation).

The observed position data 204 (p (j)) from the interferometer system 100 are supplied to the ALU 220 and the block data generator 210 . The ALU 220 also receives measurement channel phase data 209 M from the interferometer system 100 . The ALU 220 sums the observed position data 204 (p (j)) and the measurement channel phase data 209 M. The sum of the observed position data 204 (p (j)) and the measurement channel phase data 209 M is the non-linearity phase progression 219 (Ψ _NL (j)) that to the ALU 217 and the block data generator 210 .

In one embodiment, both the observed position data 204 (p (j)) and the nonlinear phase progression 219 (Ψ _NL (j)) are output at a microsecond rate of 3.2 and used by the block data generator 210 in groups of 320 to get 21 sums for each Generate group. These sums are in turn used by the parameter generator 212, (which are collectively referred to as non-linearity parameters 214) to the non-linearity parameters 214 M and 214 P to construct. The "j" in p (j) is an index for identifying the observed position data words and corresponding words of the measurement channel phase data 209 M at a microsecond rate of 3.2. In one embodiment, the nonlinearity parameter 214 includes a NL-size parameter (or NL-amount parameters) 214 M (V _NL) (NL = non-linearity = non-linearity) and a NL- phase offset parameters 214 P (θ _NL). The block RAM table 206 A is synthesized from the non-linearity size parameter 214 M (V _NL ). The non-linearity phase offset parameter 214 P (θ _NL ) is provided to the ALU 217 .

The ALU 217 subtracts the non-linearity phase offset parameter 214 P (θ _NL ) from the non-linearity phase progression 219 (Ψ _NL (j)) to form the offset-removed phase progression parameter 218 (φ _NL (j), which the block RAM table 206 A continuously addressed.

The uncompensated position data 202 is provided to the compensation processing block 206 . The ALU 206 B subtracts the compensation values obtained from the block RAM table 216 A from the uncompensated position data 202 in order to generate the compensated position data. The incoming data 202 is nonlinearly compensated for a higher, lower, or the same interferometer output rate of 3.2 microseconds. In the meantime, the "future" uncompensated non-linearity phase progression data 219 (Ψ _NL (j)) and the position data 204 (p (j)) are used by the block data generator 210 and the parameter generator 212 to generate further non-linearity parameters 214, among others to compensate for future position data. After an initial latency period, all data is compensated.

Since the non-linearity parameters 214 M and 214 P are quasi-static and are continuously updated, the process acts as a tracking filter, whereby corresponding parameters 214 are generated from the most recent position data 204 . In one form of the invention, the compensation performed by the compensation processing block 206 moves at a nanosecond speed.

In one embodiment, block data generator 210 detects when adverse conditions for an accurate measurement occur and generates an updated lock signal 216 . When an updated lock signal is generated, parameter generator 212 stops updating nonlinearity parameters 214 . During this period, the position data is compensated by the compensation processing block 206 using the existing non-linearity parameters 214 . Updating of non-linearity parameters 214 continues as the measurement conditions improve.

In one embodiment, the functions performed by the non-linearity compensation system 200 are limited to digital numerical calculation by hardware, firmware, or a combination, and the system 200 does not include optical or analog electrical circuitry. In one form of the invention, the compensation system 200 is implemented using FPGAs (FPGA = field programmable gate array) and / or one or more DSP processors.

Fig. 3 is a diagram illustrating an observed position data word 300 that has been output by the interferometer system 100. The position data word 300 comprises 32 bits. The most significant 22 bits (W1-22) of word 300 represent the path of several of a whole stripe of λ / 4. The least significant 10 bits (F1-10) of word 300 represent the fraction of a stripe.

B. Block data generation

FIG. 4 is an electrical schematic diagram illustrating one embodiment of the block data generator 210 shown in FIG. 2. Block data generator 210 includes a cosine lookup table 402 , a sine lookup table 404 , arithmetic logic units 406 A- 406 U (collectively referred to as ALUs 406 ), a bit shifter 408 , a multiplexer 410 , a bit shifter 412 , a multiplexer 414 , a bit shifter 418 , a multiplexer 420 , register 421 , an up counter 422 , a bit shifter 424 , an accumulator 426 and a modulo 320 counter and a signal generator 428 . In one embodiment, the digital circuits shown in FIG. 4 are clocked synchronously at a microsecond rate of 3.2. The clock circuit has been omitted in Figure 4 to simplify the illustration of the invention.

The observed position data words 300 , 32 bits wide, arrive at the word on terminal 416 at 3.2 microsecond intervals. The fraction of the position data words 300 is added to the fraction of the measurement channel phase progression data 209 M (φ _M (j)) on the ALU 220 . In one embodiment, block data generator 210 processes the received words of position data 204 (p (j)) and measurement channel phase data 209 M (φ _m (j)) in groups of 320 words and generates 21 output data blocks for each set of 320 words of position data 204 and 320 words of the measurement channel phase data 209 M.

The modulo 320 counter and signal generator 428 includes the modulo 320 counter 500 (shown in FIG. 5A) and logic gates 510 , 512 , 514 , 516 and 517 (shown in FIG. 5B). The processing performed by block data generator 210 is scheduled by modulo 320 counter 500 . The modulo 320 counter 500 has a cascade of three counters - a modulo 32 counter 502 , a modulo 2 counter 504 and a modulo 5 counter 506 . The modulo 32 counter 502 and the modulo 2 counter 504 are traditional binary up counters. The modulo 5 counter 506 counts 3-4-5-6-7 in an incessantly recurring sequence.

The clock-in input (Cin) of the modulo-32 counter 502 is coupled to a clock signal of 3.2 microseconds. The TC output (TC = terminal count) of the modulo-32 counter 502 is coupled to the clock-on input of the modulo-2 counter 504 . The output signal (Q) of the modulo 32 counter 502 is the five least significant bits (Q0-Q4) of the counter 500 . The connection count output of the modulo 2 counter 504 is coupled to the clock on input of the modulo 5 counter 506 . The output signal (Q) of the modulo-2 counter 504 is the fourth most significant bit (Q5) of the counter 500 . The output signal (Q) of the modulo 5 counter 506 are the three most significant bits (Q6-Q8) of the counter 500 .

A group clock signal is generated every 1024 microseconds at the port count of the modulo 5 counter 506 . The four most significant bits (Q5-Q8) of counter 500 and the most significant two bits (NLF1 and NLF2) of the fractions of nonlinear phase 219 (Ψ _NL ) are logically combined to provide ten signals to control the 21 ALUs 406 shown in the following Table I are shown to generate: Table I

In Table I above, "+" shows a logical OR- Link "⊕" shows a logical EXCLUSIVE-OR- Shortcut and "." shows a logical AND operation.

Figure 5B is a diagram illustrating the ten control signals listed in Table I and the logic gates for generating some of the signals. As shown in FIG. 5B, the signal CE.D is obtained by EXCLUSIVE-ORing the counter bits Q5 and Q7 with an EXCLUSIVE-OR gate 510 and then performing a logical ORing on the OR gate 512 with respect to the counter bit Q6 and the output of the EXCLUSIVE OR gate 510 . The SGN signal. D is a constant logic 1. The signal CE.L is generated by performing a logical AND operation on the counter bits Q6 and Q7 with the AND gate 514 . The signal SGN.L is generated from the counter bit Q8. The signal CE.Q is generated from the counter bit Q6. The SGN signal. Q is generated from counter bit Q7. The signal CE.24 is generated from the second most significant fraction bit NLF2 of the nonlinear phase 219 (Ψ _NL ). The signal CE.13 is generated by inverting with the inverter 516 of the second most significant fraction bit NLF2 of the non-linear phase 219 (Ψ _NL ). The signals SGN.24 and SGN.13 are generated from the complement of the most significant fraction bit NLF1 of the nonlinear phase 219 (Ψ _NL ) by the inverter 517 , which generates the complement.

Of the ten signals shown in FIG. 5B, the SGN.x signals are coupled to the corresponding SGN.x (polarity) inputs of the ALUs 406 and the CE.x signals are with the corresponding CE. x (clock enable) inputs of ALUs 406 coupled, where "x" identifies the special SGN and CE signals (e.g., D, L, Q, 13, or 24) that are coupled to a special ALU 406 . For example, as shown in FIG. 4, the ALU 406 A includes a clock enable input CE.D and a polarity input SGN.D, which indicates that the signals CE.D and SGN.D are with these inputs of the ALU 406 A are coupled. The connecting lines are not shown in FIG. 4 in order to simplify the illustration of the invention.

Counter arrangement 500 , shown in FIG. 5A, effectively partitions a group of 320 input words 300 into ten sequential blocks of 32 words each, numbered block 1 through block 10. Fig. 6 is a diagram of a group 600 of 320 words, position data 300, which in ten blocks 602 A- 602 J (collectively referred to as blocks 602) are partitioned from each 32 words.

A CE.x signal enables the corresponding ALUs 406 if it is TRUE. A SGN.x signal if it is TRUE specifies an increment for an enabled ALU 406 and a decrement if the signal is FALSE. The CE.x and SGN.x signals interfere with the operation of the ALUs 406 , as shown in Table II below: Table II ALUs business 1.ALUs 406 A (CD), 406 F (SD) and 406 K (PD) D: increment in blocks 1, 2, 4, 5, 6, 7, 9, 10; blocked in blocks 3 and 8. 2.ALUs 406 B (CL), 406 G (SL) and 406 L (PL) L: decrement in blocks 1, 2; blocked in blocks 3, 4, 5, 6, 7, 8; Increment in blocks 9, 10. 3. ALUs 406 C (CQ), 406 H (SQ) and 406 M (PQ) Q: increment in blocks 1, 2, 9, 10; blocked in blocks 3, 4, 7, 8; Decrement by double the values in blocks 5, 6.

As shown in Table III below, regardless of the particular block 602 being processed, the following ALUs 406 only operate on the logical values of the most significant two fraction bits (NLF1, NLE2) of the nonlinear phase 219 (Ψ _NL ): Table III ALUs business 1.ALUs 406 D (C24), 406 I (S24), 406 N (P24), 406 P (I24), 406 R (J24), 406 T (K24) "24": 406P increment to (0, 1); Decrement on (1, 1); locked to (0, 0) and (1, 0). 2.ALUs 406 E (C13), 406 J (S13), 406 O (P13), 406 Q (I13), 406 S (J13), 406 U (K13) "13": increment to (0, 0); Decrement to (1, 0); locked to (0, 1) and (1, 1).

The position data words 300 , which are received at the connection 416 , each 32 bits wide, are with the input signals of the ALUs 406 K (PD), 406 L (PL), 406 N (P24) and 406 O (P13), connected to bit shifter 418 and multiplexer 420 . A second input signal (input signal B) of the multiplexer 420 is the position data word 300 , which is multiplied by 2 by shifting by one bit with the bit shifter 418 . The multiplexed position data output by the multiplexer 420 is connected to the ALU 406 M (PQ). The multiplexer 420 is controlled by the same control bit SGN.Q as the ALU 406 M (PQ). This arrangement results in the value of the ALU 406 M (PQ) being incremented by the position data word 300 on the TRUE SGN.Q, but is decremented by twice the position data word 300 on the FALSE SGN.Q.

For summation purposes, the width of the position data words 300 can be increased from 32 to 24 bits without disadvantage by subtracting a constant integer, e.g. B. the "whole" part of the last data word 300 from the last group 600 , from each of the 320 subsequent position data words 400 .

The most significant eight bits (F1-F8) of the fraction of the words of the position data 204 , which are received at the connection 416 , are added by the AlU 220 to the fraction of the measurement channel phase progression words 209 M (φ _M (j)). The sum, designated as ΨNL (J) (and referred to as a non-linearity phase progression 219 ) addresses two look-up tables - the cosine look-up table 402 and the sine look-up table 404 . Lookup tables 402 and 404 each span an entire period in the 8-bit address space. Therefore, there are 256 entries in each table 402 and 404 from one period. Each entry in tables 402 and 404 is ten bits wide.

The output of the cosine table 402 is connected to the inputs of the ALUs 406 A (CD), 406 B (CL), 406 D (C24) and 406 E (C13), the bit shifter 408 and the multiplexer 410 . A second input (input B) of multiplexer 410 is the output of cosine table 402 , which is multiplied by 2 by shifting by one bit with bit shifter 408 . The multiplexed position data output by the multiplexer 410 are connected to the ALU 406 C (CQ). The multiplexer 410 is controlled by the same control bit SGN.Q as the ALU 406 C (CQ). This arrangement causes the value of the ALU 406 C (CQ) to be around the output value of the table 402 on the TRUE SGN. Q is incremented, but is decremented by twice the output value of table 402 on the WRONG SGN.Q.

The output of the sine table 404 is connected to the inputs of the ALUs 406 F (SD), 406 G (SL), 406 I (S24) and 406 J (S13), the bit shifter 412 and the multiplexer 414 . A second input (input B) of multiplexer 414 is the output of sine table 404 , which is multiplied by 2 by shifting by one bit with bit shifter 412 . The multiplexed position data output by the multiplexer 414 is connected to the ALU 406 H (SQ). The multiplexer 414 is controlled by the same control bit SGN.Q as the ALU 406 H (SQ). This arrangement results in the value of the ALU 406 H (SQ) being incremented by the output value of table 404 on a TRUE SGN.Q, but decremented by twice the output value of table 404 on a FALSE SGN.Q.

In addition to processing the position data words 300 and the measurement channel phase words 209 M, the block data generator 210 208 also synthesizes three digital sequences I, J and K with a 320 cycle length (1,024 microseconds). The digital sequences I, J and K are repeated once per group 600 of 320 clocks at 3.2 microseconds or 1024 microseconds.

Sequence I is a constant logic 1 and is connected to the input signals of ALUs 406 P (I24) and 406 Q ( 113 ). Sequence I is one bit wide. Therefore, ALUs 406 P (I24) and 406 Q (I13) could be simple counters in an alternative embodiment. Sequence I adds up to 2 ⁸ in operation D and zero in operation L and Q. Operations D, L and Q are added up in Table II above.

Sequence J progresses linearly from -159.5 to +159.5 by +1 per step. Sequence J has nine bits from up counter 422 concatenated with a least significant bit of a constant logic 1. The sequence J is ten bits wide and is connected to the input signals of the ALUs 406 R (J24) and 406 S (J13). Sequence J adds up to 2 ¹⁴ in operation L and to zero in operation D and Q.

The sequence K is square and is numerically equal to J ² - 9.045.25 at each stage. The sequence K is 16 bits wide and is connected to the input signals of the ALUs 406 T (K24) and 406 U (K13). The value 9,045.25 is equal to (64.127.129 - 96.191.193 + 160.321.319) / (12.128), which ensures that K sums to zero when blocks 1, 2, 4, 5, 6, 7, 9 and 10 can be summed. Sequence K is loaded by loading 16,395 into accumulator 426 at the beginning of a new group 600 of position data words 300 and by accumulating (2.J-1) at each stage, which is double the value of counter 422 alone, ie without the 1st that is chained with the least significant bit. J is multiplied by 2 by shifting J by one bit with bit shifter 424 . The sequence K adds up to 2 ²¹ in operation Q and to zero in operation D and L.

The connection count output of the modulo 5 counter 506 generates a group clock signal every 1024 microseconds, which indicates the end of a group 600 of the position data words 300 . The group clock signal from the modulo 5 counter 506 is coupled to the 21 registers 421 . Each of the 21 registers 421 is also coupled to the output of the 21 ALUs 406 . When the group clock signal is received by the registers 421 , all 21 output signals of the ALUs 406 are buffered in the 21 registers 421 . The ALUs 406 are then reset to zero and the up counter 422 and accumulator 426 are loaded with the values 160 and 16,395, respectively. After the ALUs 406 have been reset, they are receptive to new entries again.

C. Generation of non-linearity parameters (order of magnitude V _NL and phase θ _NL )

The 21 values that are latched by registers 421 from ALUs 406 are I ₂₄ , J ₂₄ , K ₂₄ , C ₂₄ , S ₂₄ , P ₂₄ , I ₁₃ , J ₁₃ , K ₁₃ , C ₁₃ , S ₁₃ , P ₁₃ , P _D , P _L , P _Q , C _D , C _L , C _Q , S _D , S _L and S _Q created by the ALUs 406 P, 406 R, 406 T, 406 D, 406 I, 406 N, 406 Q, 406 S, 406 U, 406 E, 406 J, 406 O, 406 K, 406 L, 406 M, 406 A, 406 B, 406 C, 406 F, 406 G and 406 H respectively. The 21 values are digitally processed by parameter generator 212 to order the magnitude V _NL and phase θ _NL of any nonlinearity present in the signal using the mathematical procedure shown in Equations IX through XIX below. to produce.

The six sizes P ₂₄ ', C ₂₄ ', S ₂₄ ', P ₁₃ ', C ₁₃ 'and S ₁₃ ' are generated as follows: Equation IX

Equation X

Equation XI

Equation XII

Equation XIII

Equation XIV

From the six quantities that are calculated in equations XI to XIV, the non-linearity parameters V _NL and θ _{NL are} generated, as shown in the following equations XV to XIX: Equation XV det = -C ₂₄ '.S ¹³ ' + C ₁₃ '.S ₂₄ ' equation XVI A _NL = -S ₁₃ 'P ₂₄ ' + S ₂₄ 'P ₁₃ ' equation XVII B _NL = C ₁₃ 'P ₂₄ ' - C ₂₄ 'P ₁₃ ' equation XVIII non-linearity order V _NL = (A _NL ² + B _NL ² ) ^S / det equation XIX nonlinearity phase θ _NL = arctangent (B _NL / A _NL ) / 2π

Both the linearity magnitude V _NL and the phase θ _NL are expressed in the UI when a UI represents λ / 4. The peak position deviation from the ideal is V _NL and the position of the periodic pattern is given by the phase BNL.

In one embodiment, only fixed point calculations are performed by the compensation system 200 , and division operations are limited to powers of 2. In one form of the invention, the process performed by compensation system 200 is implemented with either hardware or firmware, or a combination of hardware and firmware.

D. Nonlinearity compensation using generated parameters

The non-linearity pattern, which is an object of the embodiments of the present invention, is a result of SSB modulation (SSB modulation = single sideband modulation) and is not a single sine curve. Specifically, Δφ (φ), the phase deviation from the ideal as a function of the nonlinearity phase φ in UI, is given by Equation XX below: Equation XX

in which:
r is the ratio of the disturbing signal magnitude to the ideal signal magnitude; and
the angle θ is a phase difference between the nonlinearity periodicity Δφ (φ) and the nonlinearity phase progression φ. The block regression process measures the phase offset as θ _NL .

For small deviations, Δ (φ) is well approximated by Equations XXI to XXIV below: Equation XXI

Equation XXII

Equation XXIII Δφ (φ) ≍ V _NL .cos2π (φ-θ _NL ). [1 + 2π.V _NL Sin2π (φ-θ _NL )] Equation XXIV Δφ (φ) ≍ V _NL .cos2π (φ-θ _NL ) + π.V _NL ² sin4π (φ-θ _NL )

The quantity r / 2π in equation XXII is measured as V _NL , the order of magnitude in equations XXIII and XXIV, and 9 in equation XXII appears as the phase of deviation θ _NL in equations XXIII and XXIV. Both quantities V _NL and θ _NL are determined in one embodiment using the block regression method described above. The values of V _NL and θ _NL are estimated exactly using the cosine term only. The sine element, which is orthogonal at twice the frequency, does not have to be involved in the block regression estimate, but does play a role in determining the actual compensation value.

Although the non-linearity parameters (order V _NL and phase θ _NL ) are derived from the measured data arriving at a rate of one every 3.2 microseconds, they can be used to position the data at a rate for the next 1024 microseconds to compensate.

The following equation XXV can be described as the phase deviation Δφ (j) at any time stage j as a function of the ideal non-linear phase φ (j): Equation XXV Δφ (j) ≍ V _NL .cos2πφ (j) + π.V _NL ² .sin4πφ (j)

where V _{NL is} a measured value.

Equation XXV shows the expected non-linearity phase deviation Δφ (j) in view of the ideal phase φ (j). The value θ _NL is also a measured value. It is subtracted from the non-linearity phase progression (ΨNL (j)) to produce a non-offset non-linearity phase progression φN _L (j). In practice, the ideal φ (j) is not available. However, φ _NL (j) is inherently subject to non-linearity perturbation and differs from the ideal φ (j) by an unknown amount Δφ (j), as shown in Equation XXVI below: Equation XXVI θ _NL (j) = φ (j) + Δφ (j)

The phase deviation ΔΦ _NL (j) based on the falsified argument Φ _NL (j) is: Equation XXVII Δφ _NL (j) ≍ V _NL .cos2πφ _NL (j) + π.V _NL ² sin4πφ _NL (j)

However, this quantity in equation XXVII is not exact the compensation required because it is based on a falsified argument based.

Assuming that the changes near the range between φ _NL (j) and φ j) are piecewise linear, these two are also related, as shown in Equation XXVIII below: Equation XXVIII Δφ (j) = Δφ _NL (j ) - Δ'φ _NL .Δφ (j)

The desired deviation Δφ (j) can be solved as follows: Equation XXIX

For small values of V _NL (e.g. V _NL «1/2 _Π ) the use of 1 / (1 - δ) ≍ 1 + δ and omission of all terms involving V _NL ³ or higher can ΔΦ ( j), as shown in equations XXX and XXXI below: Equation XXX Δφ (j) ≍ (V _NL .cos [2πφ _NL (j)] + πV _NL ² sin [4πφ _NL (j)]). (1 + 2πV _NL sin [2πφ _NL (j)]) equation XXXI Δφ (φ _NL ) = V _NL .cos2πφ _NL + 2π.V _NL ² .sin4πφ _NL

Therefore, the desired phase deviation ΔΦ (j) from the distorted phase Φ _NL (j) can be constructed almost exactly up to the second harmonic by equation XXXI.

In one embodiment, ΔΦ is computed to a single read / write memory table 206 A (shown in FIG. 7) that has 256 entries spanning a period of Φ _NL and is addressable by the eight most significant fraction bits NLF1-NLF8 of Φ _NL , According to equation XXXI, each entry in table 206 A is eight bits wide.

FIG. 7 is an electrical block diagram that illustrates the compensation processing block 206 shown in FIG. 2 in greater detail. The compensation processing block 206 includes a RAM table generator 702 , a RAM table 206 A, and an ALU 206 B. In one form of the invention, RAM table 206A includes 256 values for ΔΦ that are derived from Equation XXXI using fractional φ values spanning a period can be calculated. The various values for Δφ in RAM table 206 A are represented by Δφ (φ _NL ) where the relationship is as in equation XXXI. The RAM table 206 A is generated by the RAM table generator 702 based on a non-linearity parameter V _NL provided by the parameter generator 212 . The other non-linearity parameter Φ _NL , which is also provided by parameter generator 212 , is subtracted from the currently observed non-linearity data words Ψ _NL (j) by ALU 217 to generate the non-linear phase progression φ _NL (j). RAM table generator 702 updates the Δφ (j) values stored in RAM table 704 whenever a new value for V _{NL is} received. As described above, V _NL and φ _NL are calculated every 1024 microseconds (ie every 320 position data words 300 and the corresponding measurement channel phase progression words 209 M).

At any given time index j, the (corrupted) phase φ _NL (j) addresses table 205 A. The RAM table 206 A is addressable by the eight most significant fraction bits NLF1-NLF8 of the nonlinear phase progression φ _NL (j). The Aφ values, which are addressed by the nonlinearity phase φ _NL (j) at a rate of 3.2 microseconds, are output to the ALU 706 by the RAM table 206A . The value output by table 206 A is exactly the compensation that is currently required. The ALU 206 B subtracts the value output by the table 206 A from the current position data word to obtain the compensated data word regardless of the rate of the position data words that are compensated. The ALU 206 B subtracts the Aφ values obtained from the RAM table 206 A from the received position data, which in one embodiment include position data measured or observed and extrapolated position data.

The non-linearity progression φ _NL (j), which is derived from the observed position data by subtracting an offset θ _NL , determines the non-linearity that is present at any time regardless of the data rate of the uncompensated position data. The mathematical representation of the compensation process for extrapolated position data is shown in Equation XXXII below: Equation XXXII p _ideal (i) = p (i) - V _NL .cos2πφ _NL (j) - 2π.V _NL ² .sin4πφ _NL (j)

in which
i stands for any data rate; and
j stands for the observed data rate.

E. Update suspension from Nonlinearity parameters

In one embodiment, when the measurement channel frequency approaches half of the reference channel frequency within ± 7.8125 kHz or within multiples of 312.500 kHz ± 7.8125 kHz, the update of the quasi-static non-linearity parameters θ _NL and V _{NL is} canceled. If one of these speed conditions is present, block data generator 210 (shown in FIG. 2) sends an update inhibit signal 216 to parameter generator 212 , indicating that the update of the non-linearity parameters should be canceled. In one form of the invention, the test for the absence of the above speed conditions is: (1) A group of 320 non-linearity phase data words 219 must have at least eight "quadrant" transitions within 1024 microseconds; and (2) the set of 320 nonlinearity phase data words 219 must not dwell on any quadrant for more than 128 microseconds.

A "quadrant" is defined by the most significant two bits (NLF1 and NLF2) of the fraction of the non-linearity phase data words, as shown in Table IV below: Table IV (NLF1, NLF2) Surname 0.0 1st quadrant 0.1 2nd quadrant 1.0 3rd quadrant 1.1 4th quadrant

The non-linearity parameters _{NL NL} and V _NL are updated when one or both of the above two tests are met. If none of the tests are met, the update of the non-linearity parameters is canceled. The nonlinearity parameter values calculated before the cancellation are retained and used to continuously compensate for new position data. Updating of the non-linearity parameters is resumed only when either or both of the above two tests are met.

For some metrology systems, if the difference between twice the measuring channel frequency and the Is high, a tracking filter eliminates the Interfering effect of the leak signal and it is not a significant one Non-linearity in the data. An embodiment the present invention circumvents the compensation process during such high frequency difference conditions.

Embodiments of the present invention are mainly applicable to heterodyne interferometers. At a The embodiment is the interferometer itself in has not been modified in any way. Rather, they are resulting measurement data by the interferometer are spent, processed, and two most appropriate quasi-static non-linearity parameters are generated, to compensate for the data in the near future. at the process will continue indefinitely after a initial latency period compensated for all data. The Embodiments of the invention involve only one digital numerical calculation by hardware, software or a combination of the same. With a form of Invention is not an optical or analog electrical Circuit structure used. In one embodiment won't be a Fourier transform or any other Spectral analysis method used.

Claims (25)

1. A method of compensating ( 200 ) for a non-linearity of the high-speed type, which is manifested in heterodyne interferometer position data, the method comprising the following steps:
Receiving a plurality of groups of digital position values ( 204 );
Receiving a plurality of groups of digital phase values ( 209 M) from a measurement channel ( 208 M);
digitally processing ( 210 ) a first group of the digital position values and digital phase values to generate a plurality of block data values;
digitally processing ( 212 ) the plurality of block data values to generate at least one quasi-static non-linearity parameter ( 214 ); and
Compensate ( 206 ) a second group of the digital position values based on the at least one quasi-static non-linearity parameter. 2. The method according to claim 1, wherein the first group comprises only measured digital position values ( 204 ) and digital phase values ( 209 M). 3. The method according to claim 1 or 2, wherein the second group comprises only measured digital position values ( 204 M). 4. The method according to any one of claims 1 to 3, wherein the second group comprises measured digital position values and extrapolated digital position values ( 204 ). 5. The method according to any one of claims 1 to 4, in which each group of digital position values 320 Position data words includes. 6. The method according to claim 5, wherein the first group processed in ten blocks of 32 words each becomes. 7. The method of claim 6, wherein each Position data word is 32 bits. 8. The method according to any one of claims 1 to 7, in which the at least a quasi-static Nonlinearity parameters based on a block regression technique is produced. 9. The method according to any one of claims 1 to 8, wherein the at least one non-linearity parameter comprises a non-linearity magnitude parameter ( 214 M) and a non-linearity phase parameter ( 214 P). 10. The method according to any one of claims 1 to 9, in which the temporal frequency of the nonlinearity, the is compensated for the difference between the Measuring channel frequency and the Doppler frequency is. 11. Compensation system ( 200 ) for compensating for a non-linearity of a high-speed type with heterodyne interferometer position data, the system having the following features:
a first input ( 416 ) for receiving a plurality of groups ( 600 ) of digital position values ( 300 ), each digital position value comprising an integer section and a fraction section;
a second input for receiving a plurality of groups of phase values ( 209 M) from a measuring channel ( 208 M);
a digital position data processor ( 210 ) for digitally processing a first group of digital position values and measurement channel phase values and for generating a plurality of data values;
a digital data processor ( 212 ) for processing the plurality of data values and generating at least one non-linearity parameter ( 214 ); and
a digital compensator ( 206 ) for compensating a second group of the digital position values based on the at least one non-linearity parameter. 12. Compensation system according to claim 11, wherein the digital position data processor has the following features:
a cosine lookup table ( 402 ) for providing cosine values corresponding to a fraction of the sum of the received digital position values and measurement channel phase values;
a sine lookup table ( 404 ) for providing sine values corresponding to a fraction of the sum of the received digital position values and measurement channel phase values;
a first plurality of arithmetic logic units (ALUs) ( 406 A- 406 J) for arithmetically processing the cosine and sine values, each ALU in the first plurality configured to output one of the plurality of data values based on the arithmetic processing; and
a second plurality of ALUs ( 406 K- 406 O) for arithmetically processing received digital position values, each ALU in the second plurality configured to output one of the plurality of data values based on the arithmetic processing. 13. Compensation system according to claim 12, wherein the digital position data processor further comprises:
a plurality of registers ( 421 ) coupled to the ALUs in the first and second plurality to store the plurality of data values. 14. Compensation system according to claim 13, wherein the digital position data processor further comprises:
a counter ( 428 ) coupled to the plurality of registers, the counter configured to cause the registers to store the plurality of data values at the end of each group of digital position values. 15. The compensation system of claim 14, wherein the counter is configured to generate signals to control the operation of the first and second plurality of ALUs ( 406 K- 406 O). 16. Compensation system according to one of claims 12 to 15, further comprising the following features:
a digital sequence generator ( 422-426 ) for generating a plurality of digital sequences; and
a third plurality of ALUs ( 406 P- 406 U) coupled to the digital sequence generator for arithmetically processing the digital sequences, each ALU in the third plurality configured to output one of the plurality of data values based on the arithmetic processing , 17. Compensation system according to claim 16, wherein the Majority of digital sequences a constant Sequence, a linearly increasing sequence with a Mean of zero and a quadratic sequence with comprises an average of zero, and wherein the Summation of one of the sequences to a value of one Power of 2 leads and the summation of each of the remaining sequences leads to a value of zero. 18. Compensation system according to one of claims 11 to 17, in which each group of digital position values comprises 320 position data words and in which each group of measurement phase values comprises 320 measurement phase words. 19. Compensation system according to claim 18, wherein each Position data word is 32 bits. 20. Compensation system according to one of claims 11 to 19, in which the at least one Nonlinearity parameter one nonlinearity magnitude parameter and one Nonlinearity phase parameters included. 21. Compensation system according to one of claims 11 to 20 at which the temporal frequency of the Nonlinearity that is compensated for the difference between the Measuring channel frequency and the Doppler frequency is. 22. A heterodyne interferometer system ( 100 ) for displacement measurement, which has the following features:
a light source ( 102 ) for generating at least one light beam;
an interferometer ( 108 ) for generating an optical measurement signal based on the at least one light beam;
a receiver ( 112 ) for receiving the optical measurement signal and an optical reference signal, the receiver configured to receive an analog measurement signal based on the optical measurement signal and configured to generate an analog reference signal based on the optical reference signal;
a controller ( 100 P) for generating a plurality of groups of digital position values ( 204 ) and measurement channel phase values ( 209 M) based on the analog measurement signal and the analog reference signal; and
at least one digital signal processor ( 200 ) coupled to the controller for digitally processing each group of digital position values and measurement channel phase values and generating a plurality of data values for each group being processed, the at least one digital signal processor configured to support the plurality digitally process data values for each processed group to generate at least one non-linearity parameter for each processed group, the at least one digital signal processor configured to compensate for the digital position values based on the at least one non-linearity parameter ( 214 ) for non-linearity, wherein the non-linearity that is compensated for is of a type that occurs at relatively high speeds. 23. The interferometer system ( 100 ) according to claim 22, wherein each group of digital position values comprises 320 position data words and each group of measurement channel phase values comprises corresponding 320 data words. The interferometer system ( 100 ) of claim 22 or 23, wherein at least the one non-linearity parameter ( 214 ) comprises a non-linearity magnitude parameter and a non-linearity phase parameter. 25. Interferometer system ( 100 ) according to one of claims 22 to 24, wherein the temporal frequency of the non-linearity that is compensated for is the difference between the measurement signal frequency and the Doppler frequency.