DE10247227A1 - Processing data stream in radio receiver using Viterbi- and software based procedures divides data flow for series of sequentially-overlapping execution stages - Google Patents

Abstract

Both computer procedures are repeated. Results of the second procedure form inputs for the first, using the following stages. The data flow is divided into processing sections (I1, I2, I3, I4, r1, r2, r4, r4; a1, a2, ap). The first computer procedure is carried out for a specific processing stage (r1; a1) and (b2) overlapping in time with execution of the first computer procedure, execution of the second computer procedure for another processing stage (I2; a2). An Independent claim is included for corresponding decoding equipment.

Description

Method and device for processing a Data stream in a radio receiver using software and hardware procedures

The invention relates to a method and a device for processing a data stream in one radio receiver using software and hardware procedures.

Be in a cellphone receiver a multitude of different processing steps and calculation procedures executed to reconstruct the transmitted signal from a received radio signal. The following are only those after an analog-digital conversion of the received signal Processing steps considered. Before the equalization of the received Symbols become a derotation, a DC correction, a power standardization as well as a pre-filtering of the symbols. Furthermore, the adaptive Equalization an estimate of channel parameters of the transmission channel ahead. Viterbi equalization requires transition metrics and state metrics are calculated, the ACS (Add Compare Select) operations based on the calculated State and transition metrics carried out are calculated, state vectors and for calculating the soft output values Trace back operations performed become. Subsequently have to the soft output values are deinterleaved and depunctured. it includes the channel decoding. Since the channel decoding also done according to the Viterbi algorithm, are part of channel decoding also state metrics and transition metrics to calculate and perform ACS and trace-back operations.

In principle, all of the above tasks can with a DSP (Digital Signal Processor). In practice it is however it is not possible do all the signal processing from a DSP leave because DSPs with the for this required high computing capacity is not available or are far too expensive and also show too high a power consumption. For this reason DSP hardware modules (e.g. in the form of coprocessors) assigned, which certain, recurring computing procedures in hardware To run. These task-specific hardware modules, often too as "dedicated hardware", "hardware supports" or task-specific Data paths ("dedicated data paths ") are hard-wired circuits that are made by hard-wiring Predefined calculation procedure faster and usually with less Power consumption than when processed by a processor take care of.

When defining a recipient concept is thus first to think, which of the known calculation procedures in software (i.e. by processing a data processing program in one DSP) and which of the calculation procedures in hardware (i.e. by means of a suitably designed task-specific hardware module) accomplished should be. Furthermore, the data transfer between the DSP and the hardware modules and the timing of the various Specify calculation procedures in hardware and software.

Regarding the latter Aspect in the prior art is a sequential processing of Hardware and software computing procedures known. That is, during the Calculation of result values in a hardware module by the DSP for further processing is required is the calculation procedure for further processing of the calculated result values in the DSP is deactivated. First if the hardware module the needed Has delivered results, the calculation procedure for further calculation of the result values started in the DSP. The opposite is true just like that. If a calculation procedure is carried out in the DSP, its result values that takes place in a hardware module Hardware module its activity only when the computation procedure in the DSP has ended and the values to be processed are available.

The invention is based on the object Procedure to specify which in a radio receiver in which certain Arithmetic steps in software and certain other arithmetic steps in hardware accomplished an improvement in the interaction between hardware and software enables. Furthermore, a device with an improved interaction should between hardware and software computing procedures are created.

The basis of the invention The task is solved by the features of the independent claims.

According to claim 1, the method according to the invention for processing a data stream in a radio receiver comprises at least a first computing procedure, which takes place in hardware and includes the execution of Viterbi-ACS operations, and at least a second computing procedure, which is carried out on a software basis by means of a processor , Both calculation procedures are carried out repeatedly, and the result values of the second calculation procedure represent input values for the first calculation procedure. According to the invention, the data stream to be processed is divided into a plurality of processing sections. The first calculation procedure is carried out for a specific processing section and overlaps in time with the execution of the first calculation procedure, the second calculation procedure is carried out for another processing section.

In other words, both arithmetic procedures executed simultaneously with each other. The simultaneous execution of the two calculation procedures results in a gain in process time, which is in diverse Way can be exploited. On the software side, a DSP with a comparatively lower one can be used computing capacity be used. This can both reduce electricity consumption as well as a reduced chip area can be achieved. Powerful DSPs generally have a higher power consumption as dedicated hardware. In the dedicated hardware, only the Functionality realized, the ones to deal with the intended task is required without - as with DSP - on one preferably to target general coverage of functions.

An advantageous embodiment of the Invention is characterized in that the second calculation procedure with input values that were used in an earlier execution of the first calculation procedure for one already processed processing section were obtained, is fed and calculates result values, the input values for executing the first Calculation procedure for one later processing section to be processed. In this case the division of the data stream into processing sections and their temporal processing order can be made so that a simultaneous and toothed version of the calculation procedures possible is.

The method according to the invention is preferably used for equalizing a signal, the first calculation procedure comprising, as result values, the calculation of soft output values and / or hard output values in the Viterbi equalization of symbols on the basis of calculated channel parameters, and the second calculation procedure comprises the update of channel parameters as result values on the basis of equalized symbols (soft output values and / or hard output values). The calculation or update of channel parameters on the basis of equalized symbols is also known as channel tracking ("channel tracking") and, for example, in the patent application DE 100 50 330.6 described. Channel tracking makes it possible to take fluctuations in the power of the received signal into account when equalizing.

The division takes place during equalization of the signal to be equalized into a plurality of processing sections preferably in the following way: if this is within a Time slot transmitted Signal a training sequence mitambel with known in the receiver Symbols, the processing sections are bilateral the training sequence mitambel arranged. The first calculation procedure then alternates Processing sections arranged to the right and left of the training sequence mitamble equalized sequentially by reception symbols.

By alternating right and processing sections arranged to the left of the training sequence is guaranteed that the channel parameters calculated in the second calculation procedure not for the equalization of the current (i.e. during the first calculation procedure) processed processing section but only for the equalization of the subsequent processing section are required. As a result, despite the fact that the earnings values of both Arithmetic procedures are required by the other arithmetic procedure as input values a simultaneous execution the calculation procedures are maintained.

Before the parallel processing according to the invention the first and second calculation procedures according to steps b1 and b2 the invention appropriately preprocessing the symbols of all processing sections of the time slot through a pure software processing sequence in front. The preprocessing can preferably derotate the steps correcting the symbols and / or DC correcting the symbols and / or performance standards of symbols and / or performing one estimate of channel parameters based on the training sequence and / or Pre-filter the channel parameters and symbols.

The method according to the invention is not only to the Viterbi equalization limited, but can also advantageously be used for Viterbi channel decoding of the rectified symbols. In this case, marks is a preferred method design in that the first calculation procedure Viterbi channel decoding of deinterleaved and depunctured Data includes, and the second arithmetic procedure the deinterleaving and Deposition of data (soft output values) includes.

Advantageous further developments of Invention are in the subclaims specified.

The invention is described below of embodiments explained with reference to the drawing. In this shows:

1 a circuit for performing Viterbi calculations in the form of function blocks;

2 the architecture of a receiver circuit including a DSP, a hardware circuit for Viterbi equalization and a hardware circuit for channel decoding;

3 a schematic representation of processing sections in the data structure of a burst for equalization of the same;

4 a diagram illustrating the timing of the computing procedures performed in hardware and software during the equalization;

5 a schematic representation of processing sections in the data structure of a data block for channel decoding the same; and

6 a diagram that shows the temporal sequence of the computing procedures carried out in hardware and in software during the channel decoding.

1 shows the general structure of a Viterbi calculation unit consisting of a unit for calculating transition metric values BMU (Branch Metric Unit), a unit for performing ACS operations, ACS, and a unit for performing trace-back operations with respect to the determined paths SMU (Survivor Memory Unit). A Viterbi calculation unit of the structure shown is used both in equalizers (data detectors) and in channel decoders.

The general functioning of Viterbi calculation units are known and will only be here briefly explained:

In general, the Viterbi calculation is based on the idea of using a recursive method to determine a shortest path through a state diagram (so-called trellis diagram) in which the states of a shift register are plotted over time. In the case of equalization, the shift register represents the channel memory, while in the case of channel decoding the shift register of the channel encoder contained in the transmitter is considered. In both cases, one data unit (for the equalizer: one symbol; for the encoder: one bit) is inserted into the corresponding shift register per time step, thereby changing the state of the shift register. The values of the data units that are supplied to the respective shift register in each time step can be considered as possible receive values. The probability of these data units occurring as received values is determined time by time using the Viterbi recursion. The unit BMU calculates transition probabilities for each possible transition in the (channel encoder or equalizer) trellis diagram, which are referred to as transition metric values. The calculation of these transition metric values is based on that of the Viterbi calculation unit currently at one input 1 available information, ie in the case of equalization on the received symbols and the channel parameters determined by a channel estimator, and in the case of channel decoding on the soft output values output by the equalizer.

The transition metric values calculated in the BMU unit for calculating the transition metric values are transmitted via the data connection 2 fed to the ACS unit. In the ACS unit, the transition metric values are added to the respective state metrics of the previous states (so-called "ADD" operation), and the sums obtained in this way are compared (so-called "COMPARE" operation). The transition whose sum of the transition metric value and the metric of the previous state is minimal is selected (so-called "SELECT" operation) and forms the extension of the path ending in the previous state into the target state. These three operations are called ACS operations and are performed by the ACS unit.

In both Viterbi equalization and Viterbi decoding, the ACS step is carried out cyclically for all target states within each time step, as is done by the loop 3 in 1 is indicated.

After the metrics of all target states have been determined for a specific time step in the trellis diagram, the associated winner-state transitions of the unit SMU via the data connection 4 communicated. The SMU unit carries out a trace-back operation to determine a data bit (channel decoding) or symbol (equalization) which is a certain number of time steps away. The trace-back operation is based on the fact that the individual paths converge in the backward direction in time in the trellis diagram, that is to say that data bits / data symbols which were determined for a transition which was carried out a long time ago are more reliable for surviving paths (whether a path survives or not, it only turns out after a certain number of further time steps have been processed).

In the case of channel decoding, the unit gives SMU over the data link 5 decoded data bits. In the case of equalization, the data connection 5 Soft output values and hard output values provided.

The based 1 Computational steps explained are carried out partly in hardware (from a hardware module) and partly in software (from a processor). This requires interfaces between the hardware and the processor.

2 shows the architecture of a receiver circuit with an equalizer and a channel decoder, which uses a digital signal processor DSP and a hardware module connected to the DSP via an interface for the equalization and the channel decoding. The DSP is connected to two Viterbi computing circuits RW1 and RW2 via one or more configuration registers CONFIG. The first hardware circuit RW1 serves to equalize the received data signal, the second hardware circuit RW2 performs channel decoding. The hardware circuits RW1 and RW2 can perform an equalization or channel decoding both, for example, according to the GSM (Global System for Mobile Communications) standard and also according to the EDGE (Enhanced Data Services for GSM Evolution) standard.

The first hardware circuit RW1 is ready Via a first bidirectional data connection DL1 with a first volatile data memory RAM1 and via a second bidirectional data connection DL2 with a second volatile data memory RAM2 in a data exchange connection. Corresponding third and fourth bidirectional data connections DL3 and DL4 are provided between the second hardware circuit RW2 and the first data memory RAM1 and the second hardware circuit RW2 and the second data memory RAM2.

Both hardware circuits RW1 and RW2 can further on two volatile Access data memory RAMW1 and RAMW2. As will be explained in more detail, are intermediate result values in the data memories RAMW1 and RAMW2 stored in the equalization and / or channel decoding in the Hardware circuits RW1 and RW2 occur. Access from the DSP is via two Interfaces I / O_DEC and I / O_EQ, via a central data bus DB and over the internal data buses DB1 (RAM1), DB2 (RAM2), DB3 (RAMW1) and DB4 (RAMW2). The I / O_DEC interface is for access by the DSP during a Channel decoding process and the interface I / O_EQ is for the access of the DSPs during an equalization process.

The hardware circuits RW1, RW2, the data memories RAM1, RAM2, RAMW1 and RAMW2 as well as the data buses DB3, DB4 and the data connections DL1, DL2, DL3, DL4 can be constructive be summarized in the form of a separate arithmetic processor.

1. Viterbi equalizer

• – Datenpfad zur Durchführung der ACS-Operationen,
• – Datenpfad zur Berechnung von Übergangsmetrikwerten,
• – Datenpfad zur Berechnung von Soft-Output-Werten,
• – Datenpfad zur Berechnung neuer Zustandsvektoren,
• – Datenpfad zur Berechnung von Adressen der Partialsummen für Übergangsmetrikwerten, und
• – Datenpfad zur Berechnung von hart entschiedenen Datensymbolen.

The design of the first hardware circuit RW1 for equalization of symbols is described in international application WO 02/03637 A1, which is added to the content of the present document by reference. The first hardware circuit RW1 accordingly comprises the following hardware data paths in a manner not shown here:

• - data path for performing the ACS operations,
• - data path for calculating transition metric values,
• - data path for the calculation of soft output values,
• - data path for the calculation of new state vectors,
• - Data path for calculating addresses of the partial sums for transition metric values, and
• - Data path for the calculation of hard decided data symbols.

The storage organization is like follows:

• – die vom Empfänger empfangenen Datensymbole x_k, mit k wird der Zeitschritt-Index bezeichnet;
• – vorausberechnete Partialsummen der Übergangsmetrikwerte bestehend aus Produkten von Kanalparametern h_i und Symbolen s_n des im Sender verwendeten Symbolalphabets: h_i·s_n; wobei i= 0, 1, ..., L, der Index der Kanalparameter ist (L bezeichnet die Anzahl der Speicherplätze des den Übertragungskanal modellierenden Schieberegisters) und n = 0, 1, ..., N der Symbolindex ist (wobei N+1 die Wertigkeit des Symbolalphabetes ist). Z.B. gilt für das bei EDGE verwendete achtwertige 8PSK-Modulationsalphabet s_n = exp(j·n·2π/8), wobei j die imaginäre Einheit ist.

The first volatile data memory RAM1 serves as an input memory for the hardware circuit RW1. The following sizes are stored in RAM1:

• - The data symbols received by the receiver x _k , with k the time step index is called;
• - Predicted partial sums of the transition metric values consisting of products of channel parameters h _i and symbols s _n of the symbol alphabet used in the transmitter: h _i · s _n ; where i = 0, 1, ..., L, is the index of the channel parameters (L denotes the number of memory locations of the shift register modeling the transmission channel) and n = 0, 1, ..., N is the symbol index (where N + 1 is the value of the symbol alphabet). For example, for the eight-valued 8PSK modulation alphabet used at EDGE, s _n = exp (j · n · 2π / 8), where j is the imaginary unit.

• – die berechneten Hard-Output-Werte HO_k für jeden Zeitschritt k: im Fall von 8PSK werden für jedes empfangene Datensymbol x_k drei Hard-Output-Werte HO_k (Bits) berechnet, da 8PSK-Symbole durch drei Bit codiert sind;
• – die Soft-Output-Werte SO_k für jeden Zeitschritt k: im Fall von 8PSK werden für jedes empfangene Datensymbol x_k drei Datenwörter berechnet, wobei jedes Datenwort die Konfidenz eines hart entschiedenen Bits angibt.

The second volatile data memory RAM2 serves as an output memory for the hardware circuit RW1. The following quantities are stored in RAM2:

• - The calculated hard output values HO _k for each time step k: in the case of 8PSK, three hard output values HO _k (bits) are calculated for each received data symbol x _k , since 8PSK symbols are coded by three bits;
• The soft output values SO _k for each time step k: in the case of 8PSK, three data words are calculated for each received data symbol x _k , each data word indicating the confidence of a hard-decided bit.

• – "alte" Übergangsmetrikwerte im Zeitschritt k–1 vom Zustand m in den Zustand m' : I_k–1 (m→m');
• – "alte" Metrikwerte im Zeitschritt k–1 zu jedem Zustand m: M_k–1 (m);
• – "alte" Zustandsvektoren im Zeitschritt k–1 zu jedem Zustand m: Z_k–1 (m).

The first volatile data memory RAMW1 serves as an intermediate value memory for recursive trellis processing by processing the ACS operations. The following sizes are stored in RAMW1:

• - "old" transition metric values in time step k – 1 from state m to state m ': I _{k – 1} (m → m');
• - "old" metric values in time step k – 1 for each state m: M _{k – 1} (m);
• - "Old" state vectors in time step k – 1 for each state m: Z _{k – 1} (m).

• – "neue" Übergangsmetriken im Zeitschritt k vom Zustand m in den Zustand m' : I_k (m→m');
• – "neue" Metrikwerte im Zeitschritt k zu jedem Zustand m: M_k (m);
• – "neue" Zustandsvektoren im Zeitschritt k zu jedem Zustand m: Z_k (m).

The second volatile data memory RAMW2 serves as an intermediate value memory in the recursive trellis processing by processing the ACS operations. The following sizes are stored in RAMW2:

• - "New" transition metrics in time step k from state m to state m ': I _k (m → m');
• - "New" metric values in time step k for each state m: M _k (m);
• - "New" state vectors in time step k for each state m: Z _k (m).

With the time step transition k → k + 1 after completion of the trellis processing for time step k, "new" transition metric values, metric values and state vectors become "old" transition metric values, metric values and state vectors. The at the intermediate result memory RAMW1 and RAMW2 then interchange their function, ie the intermediate value memory RAMW2 now contains the previously calculated, now "old" variables and the intermediate value memory RAMW2 is deleted and is used to store the "new" variables to be calculated.

It is clear that the entire in 1 Viterbi calculation shown in the in 2 circuit shown is executed in hardware. In general, however, not all of the computing steps to be carried out in Viterbi processing have to be carried out in hardware in the present invention, but it is also possible to implement only partial steps (for example the ACS operations) in hardware.

3 shows the data structure of a signal transmitted to the receiver within a time slot. The signal transmitted within a time slot is also referred to as a burst. In the middle of the burst there is a training sequence TS consisting of symbols that are known in the receiver. The burst has the sections D_r and D_l on the right and left of the training sequence TS. Sections D_r and D_l contain the data symbols to be reconstructed in the receiver.

In the EDGE standard, the time slot duration is 576 μs. Each section D_r or D_l of the burst comprises e.g. 58 symbols.

4 shows the processing of the symbols contained in sections D_l and D_r in the in 2 Receiver circuit shown, wherein processing procedures that are carried out on a software basis are shown below the time axis t, while processing procedures that are carried out in hardware (ie in the hardware circuit RW1) are shown above the time axis t.

First, in the preprocessing steps v1, v2, ..., v5 software calculation procedures executed. During this period is the hardware circuit RW1 inactive.

In the first software preprocessing step v1, the symbols obtained are derotated. at 8PSK modulation is used to derotate the received symbols with a phase increment of π / 4.

In the second software preprocessing step v2 a DC voltage correction is carried out. In doing so, a DC component, if any, from the one received by the Excludes symbols formed burst. Essentially done DC correction by signal averaging over a certain number of Symbols (possibly also via several bursts) and a subsequent subtraction of the averaging calculated DC offsets from each symbol received.

In the third software preprocessing step v3 there is an optional power balancing, which is essentially a scaling which represents symbols at a certain desired signal level.

The subsequent channel estimation in the fourth software processing step v4 is carried out by comparing the received symbols of the training sequence TS with the symbols known in the receiver. This comparison results in the channel properties, which are represented in the form of the channel parameters h ₀ , h ₁ , ..., h _L (for previous L time steps (taps), where “0” denotes the current point in time or time step). The channel parameters h ₀ , h ₁ , ..., h _L are the filter coefficients of the model filter which models the time-variant transmission channel.

This is followed in the fifth software preprocessing step v5 a prefiltering of the channel parameters and the symbols received. With the pre-filter, the energy which is distributed throughout the channel impulse response, in the first Channel parameters concentrated: From the estimated channel impulse response, its Energy is not necessarily concentrated in the first channel parameters a so-called pre-filter is calculated. From the estimated channel impulse response and the pre-filter is calculated a new channel impulse response, the Energy is now concentrated in the first channel parameters. This new channel impulse response is used in Viterbi equalization. The received symbols are also filtered with the prefilter.

After a little more than 200 μs, all preprocessing steps v1, v2, ..., v5 to be carried out in software have been processed. In particular, the (pre-filtered) channel parameters h ₀ , h ₁ , ..., h _{L are} determined. A parallel processing of software and hardware computing procedures then takes place in the manner according to the invention.

The following control parameters held in the configuration register CONFIG are provided for initializing the hardware circuit RW1 and for performing the segmental equalization. The control parameters can be controlled by the DSP: b_Mode: Choice between EDGE and GSM equalization; b_numb: Number of symbols x _k in a segment l_1, ..., l_4 or r_1, ..., r_4; B_r / l: Choice between equalization of the right or left half burst D_r or D_l; B_start: Starting the hardware circuit RW1 to carry out the first computing procedure implemented in hardware; b_dat_in: Setting the address pointer of the input memory RAM1 to the base value for data symbols in order to write the received data symbols x _k into the input memory RAM1; b_par_in: Setting the address pointer of the input memory RAM1 to the base value for partial sums of the transition metric values in order to write the calculated or updated products h _i · s _n into the input memory RAM1; b_hard_out: Setting the address pointer of the output memory RAM2 to the base value for hard output values in order to read them from the output memory RAM2; b_soft_out: Setting the address pointer of the memory RAM2 to the base value soft output values in order to read them from the output memory RAM2;

All but b_numb Control parameters binary, i.e. by setting a bit in the CONFIG configuration memory adjustable.

For initialization, the DSP suitable parameters for b_mod and b_numb.

Then a segmental equalization of the in 3 shown bursts performed. For this purpose, the sections D_l and D_r of the in 3 data structure shown divided into individual segments l_1, l_2, l_3, l_4 or r_1, r_2, r_3, r_4. The two segments l_1 and r_1 are arranged on the left and right adjacent to the training sequence TS, the segments l_2 and r_2 or l_3 and r_3 or l_4 and r_4 are connected on both sides in the order mentioned and are each symmetrical to the training sequence TS.

First, the symbols of segment l_1 are equalized in hardware processing step h1. For this, b_r / l is set to "left" and the input memory RAM1 is loaded with received data symbols x _k and products h _i · s _n by the control using the bits b_dat_in and b_par_in.

Hardware processing step h1 is started by setting bit b_start. As part of the equalization, the in 2 hardware circuit RW1 shown calculates the hard output values HO _k and the soft output values SO _k for the symbols of the segment l_1 and the corresponding state vectors Z _k . For this purpose, the hardware circuit RW1 carries out a trellis processing in the manner already described, ie it is based on the transmitted products h _i · s _n (which are determined in the preprocessing step v4 on the basis of the training sequence TS and filtered in the preprocessing step v5 Channel parameters include) the transition metric values I _k (m → m ') are calculated for each state transition m → m', and new state metrics M _k (m '), state vectors Z _k (m') and pro are calculated by repeated execution of the ACS operations Time step k calculates one (GSM) or three (EDGE) hard output value (s) HO _k and one (GSM) or three (EDGE) soft output value (e) SO _k for an equalized symbol, which are written into the output memory RAM2 step by time during processing. The processing extends over b_numb time steps.

After the processing of the symbols of the segment l_1 by means of the hardware calculation procedure in the hardware processing step h1, the hard output values HO _k and the soft output values SO _{k of} the processed segment l_1 are transferred to the DSP. The readout of the RAM2 output memory is controlled by setting the b_hard_out and b_soft_out bits.

The DSP then uses a second computing procedure to further process the transmitted soft output values SO _k during the software processing step s1.

The second calculation procedure performed by the software comprises two processing sequences. To the the channel parameters determined in the preprocessing step v4 become one updated. The update of channel parameters based on equalized Data symbols are known and, as already mentioned, as Channel tracking (Channel Tracking).

It also includes the second Arithmetic procedure a prefilter operation. Using the pre-filter operation the updated channel parameters and the symbols of the data segment prefiltered l_2.

After the software processing step s1 are updated and pre-filtered channel parameters and pre-filtered received symbols ready. These channel parameters give the properties of the transmission channel while the time period in which the symbols of segment l_1 are transmitted again, better than that originally in the preprocessing step v4 determined channel parameters that are based on the training sequence Orient TS.

Simultaneously or at least overlap in time pend with software processing step s1, the first calculation procedure in hardware processing step h2 is repeated. The calculation is now based on the symbols of the segment r_1. The transition metric values are calculated on the basis of the channel parameters calculated in the preprocessing step v5 (original, based on the training sequence). This means that when loading the input memory RAM1, only new data symbols x _k (for segment r_1) have to be written into RAM1 (the address pointer being set to the base address for data symbols by b_dat_in), while the memory area for the products h _i · is not written. s _{n of} the transition metric values takes place (the bit b_par_in is not set).

The hardware processing step h3 and the software processing step s2 are then carried out simultaneously or at least overlapping in time. For this purpose, the data symbols x _{k of} the segment l_2 and the updated products h _i · _{n n} calculated in the software processing step s1 are first loaded into the input memory RAM1 (b_dat_in and b_par_in are set). In the hardware processing step h3, the symbols of the segment l_2 are now processed using the updated channel parameters (contained in the products h _i · s _n ). Since the symbols of segment l_2 are temporally adjacent to the symbols of segment l_1, which were used for channel tracking, a better equalization result is obtained than if the channel parameters calculated in preprocessing step v4 were used. On the other hand, in the software processing step s2 carried out in parallel, channel parameters which have already been updated are calculated on the basis of the soft output values SO _k calculated in the hardware processing step h2 for the equalization of the symbols of the segment r_2 which subsequently ensues.

In the parallel processing steps s3, h4 and s4, h5 and s5, h6 and s6, h7, the two calculation procedures in software / hardware for processing all segments of the in 3 data structure shown repeated. The statements in brackets under the software processing steps s1, s2, ..., s6 denote the processing sections for which updated channel parameters are calculated. With the final equalization of the symbols of the segment r_4 in the hardware processing step h8 by means of the updated channel parameters calculated in the software processing step s6, the equalization of the symbols of the burst under consideration is completed.

It is pointed out that additional buffers (not shown) must be provided in the hardware which, after a hardware processing step hi, i = 1, 2,..., State vectors Z _k (m) and metrics M _k (m ) of the last processed time step k in order to enable a continuation of the equalization process for the symbols of the neighboring segment in the next but one hardware processing step hi + 2. The initial state vectors Z _k (m) and the initial metric values M _k (m) of the processing step hi + 2 are the final status vectors Z _k (m) and final metric values M _k (m) of the processing step hi.

The output memory RAM2, which, as already mentioned, contains the hard output values HO _k and soft output values SO _k for B_numb time steps k calculated for the equalization, is read out after each hardware processing step hi. The read soft output values SO _k are stored in an external memory (not shown) for the duration of a data block (for example 4 bursts).

2. Channel decoding

In the subsequent channel decoding, a parallel processing of software and hardware processing steps is also carried out. This is explained below using the 5 and 6 explained.

6 shows the processing of a data block of equalized soft output values SO _k in the in 2 Receiver circuit shown, wherein processing procedures that are carried out on a software basis are shown below the time axis t and processing procedures that are carried out in hardware are shown above the time axis t.

First, in a preprocessing step v, the soft output values SO _k are deinterleaved. The deinterleaving is carried out for the entire data block. In the case of deinterleaving, the block-by-block interleaving is canceled again.

5 schematically shows the data stream consisting of the soft output values SO _k equalized and deinterleaved over the duration of a data block. This data stream is divided into individual segments a1, a2, ..., ap (p is the selectable total number of segments).

Subsequently, two processing sequences are carried out in the software processing step s1. On the one hand, the deinterleaved soft output values SO _k of segment a1 are de-punctured. In the case of depuncturing, puncturing of the data stream by the transmitter is reversed again.

As is well known, is under Puncture the intended omission ("sticking out") of certain bits in the transmitter understood from the channel coded bit stream. The bits to be omitted are specified by a puncturing scheme. Dotting with variable Dotting schemes enabled a rate adjustment of the channel coded data stream with variable Code rate.

This is understood as depuncturing receiver-side To refill of the data stream with zeros at the dotted positions.

The second, optional processing step relates to combining the deinterleaved, depunctured soft output values SO _k with IR (incremental redundancy) in an ARQ (Automatic Repeat Request) mode.

ARQ means that data blocks received incorrectly automatically be requested again. Data blocks received incorrectly Data blocks, where channel decoding fails. If the received again Data block is error-free, it is successfully decoded and it there is nothing left to do However, the second transmission can received data block would not be decoded, a third transmission would have to be requested. IR is an approach that at least addresses this can sometimes be avoided: A combination of the two individually non-decodable data blocks can namely result in a decodable data block.

There are different possibilities the combination of two non-decodable data blocks. A easy way is e.g. arithmetic averaging, i.e. the pairwise addition of the corresponding soft output values with the following Division by the value 2.

After the software processing step s1, deinterleaved, depunctured and possibly combined soft output values SO _k are available. These are subjected to channel decoding by means of the hardware circuit RW2 in the hardware processing step h1.

• – Datenpfad zur Berechnung von Übergangsmetrikwerten;
• – Datenpfad zur Durchführung von ACS-Operationen.

The construction of the RW2 hardware circuit for Viterbi channel decoding is in the German patent application DE 100 64 102 A1 described, which is added by reference to the content of this document. The second hardware circuit RW2 accordingly comprises the following hardware data paths in a manner not shown here:

• - Data path for calculating transition metric values;
• - Data path for performing ACS operations.

The data memory RAM2, which, as already mentioned, contains the hard output values HO _k calculated during the equalization and the soft output values SO _k , serves as an input memory for the hardware circuit RW2. For the hardware processing step h1, it accepts the deinterleaved, depunctured and possibly combined soft output values SO _k that go back to the segment a1 for carrying out the Viterbi channel decoding.

Using the data path for calculating transition metric values, the transition metric values for the channel decoding are calculated in a known manner from the deinterleaved, depunctured and possibly combined soft output values SO _k . The combination of the soft output values required for this depends on the code rate used on the transmitter side and the generator polynomial used on the transmitter side channel coding and is in the European patent application EP 1 223 679 A1 described in more detail, which is added by reference to the content of this document. The transition metric values are processed by the data path in order to perform ACS operations in a likewise known manner. The resulting metric values are temporarily stored in the volatile memories RAMW1 and RAMW2. For each trellis state, those decision values of the ACS operations that are transferred to the DSP for a traceback step are determined.

At the same time or at least overlapping in time with the hardware processing step h1, the first calculation procedure is repeated in the software processing step s2. The calculation is now based on the deinterleaved soft output values SO _k of segment a2.

After the software processing step s2 has ended, the calculated deinterleaved, depunctured and possibly combined soft output values SO _{k are written} into the memory RAM2 of the receiver and read out by the hardware circuit RW2. The hardware processing step h2 is started, while at the same time or overlapping in time with the hardware processing step h2, the data of the segment a3 is already being processed in the DSP (software processing step s3).

Control of the hardware circuit RW2 through the DSP is also about the configuration register CONFIG, by means of appropriate Control parameters (data words and bits) as for the case of equalization have been explained in detail.

In the following parallel processing steps h3, s4 and h4, s5, ... the two calculation procedures in software / hardware for processing all segments a1, a2, ..., ap des in 5 shown deinterleaved data blocks repeated. The channel decoding of the data block under consideration is completed with the final channel decoding of the deinterleaved soft output values SO _{k of} the segment ap in the hardware processing step hp.

Claims (15)

Method for processing a data stream in a radio receiver by means of at least one first computing procedure, which takes place in hardware (RW1, RW2) and comprises the execution of Viterbi-ACS operations, and at least one second computing procedure, which is based on software by means of a processor (DSP ) is carried out, the two calculation procedures being carried out repeatedly and result values of the second calculation procedure being input values for the first calculation procedure, with the steps: (a) dividing the data stream into a plurality of processing sections (l_1, l_2, l_3, l_4, r_1, r_2, r_3, r_4; a1, a2, ..., ap); (b1) executing the first calculation procedure for a specific processing section (r_1; a1); and (b2) overlapping in time with the execution of the first calculation procedure, execution of the second calculation procedure for another processing section (I_2; a2). A method according to claim 1, characterized in that the second calculation procedure - with input values at an earlier one execution the first calculation procedure for an already processed processing section (l_1) has been received, is fed, and - to Calculation of result values, the input values for the execution of the first calculation procedure for one later to be processed processing section (I_2) is executed. A method according to claim 1 or 2, characterized in that that the method is used to equalize a signal, where - the first calculation procedure as result values the calculation of soft output values and / or hard output values in the Viterbi equalization of symbols based on calculated channel parameters, and - the second Calculation procedure as result values, the update of channel parameters based on equalized symbols. A method according to claim 3, characterized in - that the second calculation procedure further pre-filtering both the channel parameters as well as the symbols to be equalized. A method according to claim 3 or 4, characterized in - that this Signal transmitted within a time slot includes a training sequence mitambel (TS) with symbols known in the receiver, - that the Processing sections (l_1, l_2, l_3, l_4; r_1, r_2, r_3, r_4) are arranged on both sides of the training sequence mitambel (TS), and - that alternating Processing sections arranged to the right and left of the training sequence mitambel (TS) (l_1, l_2, l_3, l_4; r_1, r_2, r_3, r_4) consecutively in time be equalized by means of the first calculation procedure. A method according to claim 5, characterized in that the first calculation procedure in addition to the calculation of soft output values and / or hard output values for the equalized symbols includes: - the calculation of transition metrics, - the calculation of state metrics by executing the ACS operations, and - the Calculation of state vectors. Method according to one of claims 3 to 6, characterized in that that before steps b1 and b2 preprocessing of the symbols all processing sections (l_1, l_2, l_3, l_4, r_1 2, r_3, r_4) through a pure software processing flow (v1, v2, v3, v4, v5) is made. A method according to claim 7, characterized in that preprocessing includes the steps: - Derotate (v1) the symbols and / or - DC correction (v2) the symbols and / or - standardize performance (v3) the symbols and / or - performing one estimate of channel parameters (v4) based on the training sequence (TS), and / or - pre-filter (v5) the channel parameters and the symbols to be equalized. A method according to claim 1, characterized in that the method for channel decoding a data stream exists equalized from soft output values. A method according to claim 9, characterized in that the first arithmetic procedure de-interleaved the Viterbi channel decoding and depunctured data and the second calculation procedure includes Deinterleaving and depuncturing of data includes. A method according to claim 9 or 10, characterized in that that the second calculation procedure furthermore the combination of deinterleaved and depunctured data at incremental redundancy. Method according to one of claims 9 to 11, characterized in that that preprocessing of the data before steps b1 and b2 all processing sections (a1, a2, ..., ap) through a pure software processing sequence (v) is made. Device for equalizing a transmitted over a disturbed channel Signal according to the method of one of claims 3 to 8, with - one hardwired first hardware circuit (RW1) to run the first calculation procedure, and - a digital signal processor (DSP) to run the second calculation procedure. Device according to claim 13, characterized in that the first hardware circuit (RW1) comprises: a first hardware data path for implementation ACS operations which calculate state metrics, - a second hardware data path for calculating transition metric values, - a third hardware data path for calculating soft output values and / or hard output values for the equalized symbols, and - a fourth hardware data path for calculating state vectors. Device for decoding channels via one disturbed Channel transmitted Signals according to the method of claims 9 to 12, with - one hardwired second hardware circuit (RW2) to run the first calculation procedure, and - a digital signal processor (DSP) to run the second calculation procedure.